CN101097965A - 非易失性存储器件及其制造方法 - Google Patents

非易失性存储器件及其制造方法 Download PDF

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CN101097965A
CN101097965A CNA2006101680262A CN200610168026A CN101097965A CN 101097965 A CN101097965 A CN 101097965A CN A2006101680262 A CNA2006101680262 A CN A2006101680262A CN 200610168026 A CN200610168026 A CN 200610168026A CN 101097965 A CN101097965 A CN 101097965A
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崔殷硕
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SK Hynix Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40117Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/512Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

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Abstract

一种具有多晶硅氧化物氮化物氧化物半导体(SONOS)结构的非易失性存储器及其制造方法,其中电荷捕获层在水平方向上被物理分隔。朝向源极和漏极捕获电荷的电荷捕获层被物理分离。这基本上可以防止两侧的电荷相互移动。因此,尽管单元尺寸减小,还是可以防止两侧电荷之间的干扰。

Description

非易失性存储器件及其制造方法
技术领域
本发明一般性涉及非易失性存储器件,具体涉及具有多晶硅氧化物氮化物氧化物半导体(SONOS)结构的非易失性存储器件及其制造方法,其中电荷捕获层被水平物理分离。
背景技术
近年来,非易失性半导体存储器(NVSM)大致分为浮动栅极系列和金属绝缘体半导体(MIS)系列,其中根据工艺技术,两次或三次层叠两种或更多种介电层。
浮动栅极系列通过采用势阱来实现存储特性。浮动栅极系列的典型实例是EPROM隧道氧化物(ETO)结构,其被广泛用作快闪电可擦除可编程只读存储器(EEPROM)。MIS系列采用存在于介电层本体、介电层介电层界面和介电层-半导体界面的阱(trap)来执行存储功能。MIS系列的典型实例是广泛用作快闪EEPROM的金属/多晶硅氧化物氮化物氧化物半导体(MONOS/SONOS)。
SONOS和一般的快闪存储器的区别是:在一般快闪存储器中,电荷储存在浮动栅极中,而在SONOS中,电荷根据结构储存在氮化物层中。
此外,在一般的快闪存储器中,使用多晶硅来形成浮动栅极。这样,如果在多晶硅中存在任何一个缺陷的话,电荷的保留时间就明显减少。相反,在SONOS中,如上所述使用氮化物层来替代多晶硅。因此,对制造过程中的缺陷的敏感性相对要小。
另外,在一般的快闪存储器中,在浮动栅极下方形成厚度约70的隧道氧化物。这对于实现低电压高速操作存在限制。然而,在SONOS中,在氮化物层下方形成直接隧道氧化物。因此,可以实现具备低电压、低功率和高速操作的存储器件。
以下将参考图1来说明具有SONOS结构的现有快闪存储器件。
参考图1,在半导体衬底10上顺序形成隧道氧化物层11、电荷捕获层12、阻挡栅极(氧化物层)13和用于栅极的电极14。接着,通过蚀刻过程形成字线图案。在SONOS结构的快闪存储单元中,因为同样的电场(E-field)施加在整个阻挡氧化物层13(即绝缘层)、储存电荷的电荷捕获层12和隧道氧化物层11的复合层上,所以不能对绝缘层分别施加不同的电场。
在此,如果向用于栅极的电极14施加电压以擦除储存在电荷捕获层12中的电荷,则储存在氮化物层12中的电荷利用Fowler-Nordheim(F-N)隧道电流通过隧道氧化物层11移向半导体衬底10,并随后被擦除。
当存储单元的尺寸减小时,变得难以在SONOS结构中分离在源极区15和漏极区16捕获的电荷。如果电荷密度增加以实现多层级,则干扰现象就变得更显著,这导致对集成度的限制。
发明内容
因此,本发明解决上述问题,并提供具有SONOS结构的非易失性存储器件,其中朝向源极和漏极捕获电荷的电荷捕获层被物理分隔,以防止在电荷捕获层两侧的电荷相互移动,并且尽管单元尺寸减小,但是可以防止两侧的电荷之间的干扰,以及提供制造该非易失性存储器件的方法。
根据一个方面,本发明提供一种非易失性存储器件,包括栅极,其中分别在半导体衬底上方形成栅极绝缘层、电荷捕获层、阻挡氧化物层和栅极电极。电荷捕获层被缓冲层物理分离。
根据另一实施方案,本发明提供一种制造非易失性存储器件的方法,包括以下步骤:在半导体衬底上方分别沉积栅极绝缘层、缓冲层、阻挡氧化物层和栅极电极;蚀刻栅极电极、阻挡氧化物层、缓冲层和栅极绝缘层来形成栅极;执行离子注入过程,从而在半导体衬底内形成源极和漏极区;通过选择性蚀刻缓冲层两侧来选择性形成缓冲层凹陷图案;和在缓冲层凹陷图案中形成电荷捕获层。
附图说明
图1是具有SONOS结构的现有快闪存储器件的截面图;和
图2-5是说明根据本发明实施方案的制造具有SONOS结构的半导体存储器件的方法的截面图。
具体实施方式
以下,将参考附图详细说明本发明的具体实施方案。
图2-5是说明根据本发明实施方案的制造具有SONOS结构的非易失性存储器件的方法的截面图。
参考图2,在半导体衬底100上顺序形成栅极绝缘层101、缓冲层102、阻挡氧化物层103和栅极电极104。缓冲层102可以使用氧化硅层或氮化硅层形成。阻挡氧化物层103可以使用高介电层来形成,例如Al2O3、HfO2、Ta2O5、ZrO2、La2O3或TiO2或者它们的组合。此外,可以使用氧化硅层来替代阻挡氧化物层103。栅极电极104可以使用掺杂杂质的多晶硅来形成。栅极电极104可以使用过渡金属氮化物例如TiN、TaN、TiCN、TaCN、TiSiN、TaSiN、WN或RuTiN来形成。缓冲层102优选形成为20-1000的厚度。
参考图3,通过蚀刻过程顺序部分蚀刻栅极电极104、阻挡氧化物层103、缓冲层102和栅极绝缘层101,形成栅极图案。执行离子注入过程,从而在暴露的半导体衬底100中形成源极区105和漏极区106。
参考图4,执行蚀刻过程以使暴露的缓冲层102的侧面凹陷,从而形成空隙。优选凹陷深度是栅极图案长度的1/20-1/2或更小。
接着,在全部表面上沉积电荷捕获层107。电荷捕获层107优选形成为完全间隙填充通过蚀刻缓冲层102得到的空隙。而且,可以使用氮化硅层或金属氧化物层来形成电荷捕获层107。
可以在沉积电荷捕获层107的过程之后执行源极区105和漏极区106的形成过程。
参考图5,执行蚀刻过程以使电荷捕获层107仅仅保留在缓冲层102的两侧。也就是说,优选电荷捕获层107被缓冲层102物理分隔。由此,由于具有物理上性质不同的层即缓冲层102,使得捕获电荷的电荷捕获层107在栅极两侧被水平分成两层。
可以在蚀刻电荷捕获层107的过程之后执行源极区105和漏极区106的形成过程。
根据本发明,朝向源极和漏极捕获电荷的电荷捕获层被物理分离。基本上可以防止两侧电荷相互移动。因此,尽管单元尺寸减小,但依然可以防止两侧电荷之间的干扰。
虽然已经参考各种实施方案进行了前述说明,但是本领域技术人员可以进行变化和更改而不偏离本发明的精神和范围。

Claims (16)

1.一种非易失性存储器件,包含:
栅极,其中分别在半导体衬底上方形成栅极绝缘层、电荷捕获层、阻挡氧化物层和栅极电极,
其中所述电荷捕获层被缓冲层物理分离。
2.权利要求1的非易失性存储器件,其中所述电荷捕获层是氮化硅层或金属氧化物层。
3.权利要求1的非易失性存储器件,其中所述缓冲层是介电层。
4.权利要求3的非易失性存储器件,其中所述介电层是氧化硅层或氮化硅层。
5.权利要求1的非易失性存储器件,其中所述缓冲层的宽度比栅极宽度小1/10。
6.权利要求1的非易失性存储器件,其中所述缓冲层具有20-1000的厚度。
7.一种制造非易失性存储器件的方法,包括以下步骤:
在半导体衬底上方分别沉积栅极绝缘层、缓冲层、阻挡氧化物层和栅极电极;
蚀刻栅极电极、阻挡氧化物层、缓冲层和栅极绝缘层以形成栅极;
执行离子注入过程,从而在半导体衬底内形成源极和漏极区;
通过选择性蚀刻缓冲层两侧来选择性形成缓冲层凹陷图案;和
在缓冲层凹陷图案中形成电荷捕获层。
8.权利要求7的方法,包括使用氧化硅层或氮化硅层来形成所述缓冲层。
9.权利要求7的方法,包括使所述缓冲层形成20-1000的厚度。
10.权利要求7的方法,包括使用高介电层形成阻挡氧化物层。
11.权利要求10的方法,其中所述高介电层选自Al2O3、HfO2、Ta2O5、ZrO2、La2O3、TiO2和其组合。
12.权利要求7的方法,其中在选择性蚀刻过程中,所述缓冲层两侧每一侧的凹陷厚度是栅极宽度的1/20-1/2。
13.权利要求7的方法,包括使用过渡金属氮化物或掺杂杂质的多晶硅来形成栅极电极。
14.权利要求13的方法,其中所述过渡金属氮化物是TiN、TaN、TiCN、TaCN、TiSiN、TaSiN、WN或RuTiN。
15.权利要求7的方法,其中形成电荷捕获层的步骤包括以下步骤:
在缓冲层的凹陷图案、栅极和半导体衬底上沉积电荷捕获材料;和蚀刻所述电荷捕获材料,其中电荷捕获材料仅保留在缓冲层的凹陷图案上。
16.权利要求15的方法,包括在沉积电荷捕获材料的步骤或形成电荷捕获层的步骤之后,执行离子注入过程。
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CN102693984A (zh) * 2011-03-21 2012-09-26 中国科学院微电子研究所 一种多值非挥发存储器及其制备方法
CN102693984B (zh) * 2011-03-21 2015-04-15 中国科学院微电子研究所 一种多值非挥发存储器及其制备方法
CN102280377A (zh) * 2011-08-26 2011-12-14 上海宏力半导体制造有限公司 Sonos结构及其制作方法
CN102280377B (zh) * 2011-08-26 2015-11-11 上海华虹宏力半导体制造有限公司 Sonos结构及其制作方法
CN102496566A (zh) * 2011-11-29 2012-06-13 无锡中微晶园电子有限公司 用于sonos存储芯片批产工艺中的存储管多晶刻蚀方法
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CN105047670B (zh) * 2015-06-29 2018-04-17 上海华虹宏力半导体制造有限公司 Sonos器件的制造方法
CN108122993A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 半导体装置的制造方法
CN108122993B (zh) * 2016-11-29 2022-10-18 台湾积体电路制造股份有限公司 半导体装置的制造方法与半导体装置

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