CN101097887A - 制造半导体器件的方法 - Google Patents

制造半导体器件的方法 Download PDF

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CN101097887A
CN101097887A CNA2006101732182A CN200610173218A CN101097887A CN 101097887 A CN101097887 A CN 101097887A CN A2006101732182 A CNA2006101732182 A CN A2006101732182A CN 200610173218 A CN200610173218 A CN 200610173218A CN 101097887 A CN101097887 A CN 101097887A
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etching
nitride
layer
coating
oxide skin
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赵挥元
洪承希
金奭中
郑哲谟
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种制造半导体器件的方法，所述方法包括下列步骤，在半导体衬底上形成层间绝缘层和蚀刻-停止氮化物层，对蚀刻-停止氮化物层和层间绝缘层进行来形成接触孔，在接触孔内形成接触，在包含接触的整个表面上形成氧化物层，以蚀刻-停止氮化物层作为目标蚀刻氧化物层，由此形成沟槽，通过所述沟槽暴露所述接触和与接触邻近的蚀刻-停止氮化物层，并且在沟槽中形成位线。

Description

制造半导体器件的方法
技术领域
本发明涉及半导体器件，更具体而言，涉及制造半导体器件的方法，所述方法可以通过减少位线之间的电容来减少RC延迟。
背景技术
图1A-1C是描述制造半导体器件的常规方法的横截面图。
参考图1A，在形成有结构(未显示)的半导体衬底10上形成层间绝缘层11。在层间绝缘层11内形成接触孔，通过所述接触孔暴露半导体衬底10的特定部分。用导电层填充接触孔，由此形成下接触12。
在包含下接触12的整个表面上依次形成蚀刻-停止氮化物层13和氧化层14。
参考图1B，使用蚀刻-停止氮化物层13作为停止层蚀刻氧化物层14，由此形成沟槽15。通过过蚀刻方法除去沟槽15下面的蚀刻-停止氮化物层13，由此暴露出下接触12和与下接触12邻近的层间绝缘层11的特定部分。此时，将蚀刻-停止氮化物层13下面的层间绝缘层11蚀刻至期望的特定厚度。
参考图1C，在包含沟槽15的整个表面上形成阻挡金属层(未显示)。形成导电层来填充沟槽15。进行抛光过程使氧化物层14暴露出，因此形成位线16。
在现有技术中，蚀刻-停止氮化物层13的总厚度位于位线16之间。氮化物层的介电常数比氧化物层的介电常数高两倍，造成位线电容增大。因此，增加了RC延迟。
发明内容
本发明涉及制造半导体器件的方法，所述方法可以通过减少位线之间的电容来减少RC延迟。
在一个实施方案中，制造半导体器件的方法包括下列步骤：在半导体衬底上形成层间绝缘层和蚀刻-停止氮化物层，对蚀刻-停止氮化物层和层间绝缘层进行蚀刻以形成接触孔，在接触孔内形成接触，在包含接触的整个表面上形成氧化物层，采用蚀刻-停止氮化物层作为目标蚀刻氧化物层，由此形成沟槽，通过所述沟槽暴露所述接触和与所述接触邻近的蚀刻-停止氮化物层，并且在沟槽中形成位线。
附图说明
图1A-1C是说明制造半导体器件的常规方法的横截面图。
图2A-2C是说明根据本发明的一个实施方案制造半导体器件的方法的横截面图。
具体实施方式
下面参考附图描述了根据本发明的具体实施方案。
图2A-2C是说明根据本发明的一个实施方案制造半导体器件的方法的横截面图。
参考图2A，在半导体衬底20上依次形成层间绝缘层21和蚀刻-停止氮化物层22，所述半导体20具有形成在其中的结构。
对蚀刻-停止氮化物层22和层间绝缘层21进行蚀刻以形成接触孔，通过所述接触孔暴露半导体衬底20的部分。用导电层填充接触孔来形成下接触23。
在包含下接触23的整个表面上形成氧化物层24。氧化物层24可以包含常规(general)氧化物层，但是优选包含这样一种氧化物层，这种氧化物层中加入了F(氟)(也就是说，F氧化物层)，具有约为3.7的介电常数，低于常规氧化物层约为4.2的介电常数。
参考图2B，使用蚀刻-停止氮化物层22作为停止层蚀刻氧化物层24，从而形成沟槽25，通过沟槽25暴露下接触23和与下接触23邻近的蚀刻-停止氮化物层22的特定部分。此时，还将蚀刻-停止氮化物层22蚀刻至厚度位约10-200。
由于对沟槽25的蚀刻停止在蚀刻-停止氮化物层22，所以沟槽25具有恒定的深度。
参考图2C，在包含沟槽25的整个表面上形成阻挡金属层(未显示)。形成导电层来填充沟槽25。进行抛光过程使氧化物层24暴露出，从而形成位线26。
将具有低介电常数的氧化物层24填充在位线26之间。具有高介电常数的蚀刻-停止氮化物层22的部分很小。因此，在形成具有相同厚度的位线的情况下，位线电容可以降低约10％。
在现有技术中，在位线之间存在厚度为约300的蚀刻-停止氮化物层和厚度为约1200的氧化物层。因此，位线间电容Cb是300×氮化物层的介电常数(8)+1200×氧化物层的介电常数(4.2)，也就是约7740。
然而，在本发明中，在位线之间存在具有厚度h(指图2B)的氮化物层和具有厚度(1500-h)的氧化物层。因此，位线间电容Cb变为h×氮化物层的介电常数(8)+(1500-h)×氧化物层的介电常数(4.2)。
因此，当h是150时，位线间电容为6870。因此，优点是位线间电容减少约7.7％。当h是100时，位线间电容为6680。因此，优点是位线间电容减少约10.3％。
此外，如果使用具有低介电常数的FSG(介电常数为3.7)作为氧化物层，可以更有效地减少位线电容。
如上所述，本发明具有下列优点。
形成蚀刻-停止氮化物层之后，形成了下接触。当蚀刻沟槽时，蚀刻去掉蚀刻-停止氮化物层的一部分，以减少存在于位线之间的氮化物层的厚度。因此，可以降低位线电容和减少RC延迟。
此外，使用加入低介电常数的氟(F)的氧化物层作为氧化物层。所以可以降低位线间电容并且还减少RC延迟。
本发明的独特的实施方案是说明性的不是限制性的。允许各种替换和等同形式。其它的增加、减少或修改应该落入权利要求书定义的本发明的范围内。

Claims (4)

1.一种制造半导体器件的方法，所述方法包括下列步骤：
在半导体衬底上形成层间绝缘层和蚀刻-停止氮化物层，对蚀刻-停止氮化物层和层间绝缘层进行蚀刻以形成接触孔；
在接触孔内形成接触；
在包含接触的整个表面上形成氧化物层；
使用蚀刻-停止氮化物层作为目标蚀刻氧化物层，因此形成沟槽，通过所述沟槽暴露接触和与接触邻近的蚀刻-停止氮化物层；和
在沟槽内形成位线。
2.权利要求1的方法，其中所述氧化物层包括含有加入的氟(F)的氧化物层。
3.权利要求1的方法，包括在蚀刻沟槽时对蚀刻-停止氮化物层的一部分进行蚀刻。
4.权利要求3的方法，包括蚀刻氮化物层至厚度为10-200。
CNA2006101732182A 2006-06-28 2006-12-30 制造半导体器件的方法 Pending CN101097887A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489869A (zh) * 2012-06-13 2014-01-01 爱思开海力士有限公司 半导体存储器件、存储系统及其制造方法

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US6020269A (en) * 1998-12-02 2000-02-01 Advanced Micro Devices, Inc. Ultra-thin resist and nitride/oxide hard mask for metal etch
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KR100716651B1 (ko) 2004-06-07 2007-05-09 주식회사 하이닉스반도체 반도체 소자 제조 방법
KR100637965B1 (ko) 2004-12-22 2006-10-23 동부일렉트로닉스 주식회사 Ｆｓｇ 절연막을 이용한 반도체 소자의 금속 배선 형성 방법
KR100632115B1 (ko) 2004-12-29 2006-10-04 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 형성 방법
KR100632653B1 (ko) * 2005-04-22 2006-10-12 주식회사 하이닉스반도체 반도체 소자의 비트라인 형성방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489869A (zh) * 2012-06-13 2014-01-01 爱思开海力士有限公司 半导体存储器件、存储系统及其制造方法
CN103489869B (zh) * 2012-06-13 2017-11-28 爱思开海力士有限公司 半导体存储器件、存储系统及其制造方法

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