CN101036120A - 频率和电压缩放架构 - Google Patents
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Abstract
一种用于缩放至少一个微处理器的时钟域的频率和操作电压的方法和装置。尤其,本发明涉及把微处理器划分成时钟域和单独控制每个时钟域的频率和操作电压的技术。
Description
技术领域
本发明的实施例涉及微处理器架构领域。尤其,本发明的实施例涉及一种缩放微处理器内的各种功能单元的频率和操作电压的技术。
背景技术
为了帮助降低微处理器的功率,同时最小化对性能的影响,已经开发了用于降低处理器时钟频率的现有技术。在这些现有技术中,存在把处理器分成多个时钟域的架构。例如,一种现有技术具有用于整数管线的单独时钟域、用于浮点管线的单独时钟域、以及用于存储器存取逻辑的单独时钟域。
由于控制每个时钟域所需要的线路的开销,对每条管线和/或存储器存取群集使用单独时钟域能引起维护处理器性能的挑战。
附图说明
通过示例来例示出实施例和发明,但不受附图的限制,附图中相同的引用指示类似的元件,其中:
图1示出了根据本发明的一个实施例的时钟和电压缩放架构。
图2示出了能在其中使用本发明的一个实施例的前端总线计算机系统。
图3示出了能在其中使用本发明的一个实施例的点对点计算机系统。
发明详述
本发明的实施例涉及用于微处理器的频率和电压控制架构。尤其,本发明的实施例涉及在微处理器中多个时钟域之间分配和控制时钟和操作电压的技术,以使每个域的频率和操作电压能被单独地控制。
图1示出了根据本发明的一个实施例的时钟和电压域架构。尤其,图1示出了已经被划分成三个基本时钟域的处理器架构100:前端域101,具有跟踪高速缓冲存储器102、分支预测器103、重命名单元104、解码单元105、定序器106、自由表107、重命名表108、以及重新排序缓冲器(ROB)109;数个后端域110,具有存储器排序缓冲器(MOB)111、一级高速缓冲存储器112、物理寄存器文件113、发出队列(issue queue)114、总线接口116以及执行单元115;以及存储器域,包括二级高速缓冲存储器119。在一个实施例中,总线接口是前端总线接口,而在其他实施例中,它是点对点总线接口。
前端域、后端域和存储器域各具有至少一个先进先出(FIFO)队列117,用以帮助同步各个时钟域之间的信息交换。在本发明的一个实施例中,至少某些同步队列是在处理器内提供其他功能的队列,然而在其他实施例中,同步队列被用于时钟域控制架构。除了时钟域,本发明的一个实施例把处理器分成彼此可被单独控制的电压域。在至少一个实施例中,时钟域和电压域是相同的并且包括相同的功能单元,然而,在其他实施例中,时钟域和电压域不是相同的并且可包括不同的功能单元。
在本发明的一个实施例中,各个时钟域中的每个时钟能被同步于参考时钟。然而,在其他实施例中,每个域时钟可不与其他域时钟同步。此外,在至少一个实施例中,后端域可通过被称为“交叉开关(crossbar)”的信号相互通信。
为了控制每个时钟域和电压域,本发明的一个实施例试图通过在某些时间间隔确定每个域的能量和性能来最小化每个域的能量和延迟的平方(delay2)的乘积。在至少一个实施例中,可通过计算在第一时间间隔期间域的能量和延迟以及估算在后一时间间隔域的能量和延迟,在两个时间间隔确定能量和性能。然后,可通过最小化第一时间间隔的能量和延迟的平方(delay2)的乘积与后一时间间隔的能量和延迟的平方(delay2)的乘积的比率,来选择所述后一时间间隔的频率和电压对。
例如,在本发明的一个实施例中,对于间隔n+1,处理器能量“E”根据以下的等式被估算:
在以上的等式中,“EFE,n”是在时间间隔“n”的前端域的能量,“En+1”是在时间间隔n+1的前端的能量,“Vn+1”是在时间间隔n+1的前端域的操作电压,“Vn”是在时间间隔n的前端域的操作电压。
作为前端域的频率的函数的处理器的性能能通过使用给定的时间间隔的前端域的时钟频率、前端取指令的速率、微操作(解码的指令)被送交后续管线级的速率来估算。在一个实施例中,根据以下等式估算时间间隔n+1的性能估算“Tn+1”:
在以上的等式中,“pn”是第n个时间间隔的前端队列中的输入项的平均数,“b”是分支错误预测率。值“1+b”是可被装载的取指令队列的速率的指示器,而“1-pn”是队列中输入项的平均数的指示器。“Tn”是在间隔“n”的前端的性能,“fn”是在间隔n的前端域的频率,以及“fn+1”是在下一时间间隔的前端域的频率。
一旦处理器的能量和性能根据以上的等式被计算,在一个实施例中,前端域频率和电压能在每个时间间隔n的末端为下一个时间间隔n+1被调整。在一个实施例中,可根据以下比率做出频率和电压的选择:
被选择用于间隔n+1的频率和电压是那些最小化以上比率的频率和电压。如果发现两对或两对以上的频率和电压产生相同的值R,那么在一个实施例中选择具有最小频率的那对。然后,对于间隔n+1,前端域的频率和操作电压可被设定成适当的值,并且对下一个间隔重复该过程。
每个后端频率和操作电压可通过与对前端相同的方式被估算,估算是通过按照每个后端域的操作电压和频率的函数估算处理器的能量和性能,以及选择将间隔n+1和间隔n之间的能量性能乘积的比率最小化的频率和操作电压而进行的。在一个实施例中,处理器能量“En”作为后端域能量“EBE,n”的函数根据以下等式被估算:
作为每个后端域的频率的函数的处理器的性能可在每个间隔n+1通过以下等式被计算:
其中,
以及,
在以上的等式中,mn是对于间隔n的二级高速缓冲存储器失败数除以调拨的微操作数,Lq,n是对于包含执行单元的所有后端域的所有微操作发出队列的平均使用。一旦处理器的能量和性能根据以上的等式被计算,在一个实施例中,后端域频率和电压能在每个时间间隔n的末端为下一个时间间隔n+1被调整。在一个实施例中,频率和电压的选择可根据以下的比率做出:
被选择刚于间隔n+1的频率和电压是那些最小化以上比率的频率和电压。如果发现两对或两对以上的频率和电压产生相同的值R,那么在一个实施例中选择具有最小频率的那对。然后,对于间隔n+1,后端域的频率和操作电压可被设定成适当的值,并且对下一个间隔重复该过程。
图2示出了本发明的一个实施例可在其中被使用的前端总线(FSB)计算机系统。处理器205访问来自一级(L1)高速缓冲存储器210和主存储器215的数据。在本发明的其他实施例中,高速缓冲存储器可以是二级(L2)高速缓冲存储器或其他计算机系统存储器分级结构内的存储器。此外,在某些实施例中,图2的计算机系统既可包括L1高速缓冲存储器也可包括L2高速缓冲存储器,该计算机系统包括相容(inclusive)高速缓冲存储器分级结构,其中相干的数据能在L1和L2高速缓冲存储器中共享。
在图2的处理器内示出的是本发明的一个实施例206。然而,本发明的其他的实施例可在系统内诸如分离总线代理之类的其他设备内被实现,或者以硬件、软件、或它们的组合的方式分布在系统中。
主存储器可以各种存储器源来实现,诸如动态随机存取存储器(DRAM)、硬盘驱动器(HDD)220、或通过包括各种存储设备和技术的网络接口230从计算机系统远程定位的存储源。高速缓冲存储器可位于处理器内或靠近处理器,诸如在处理器的局部总线207上。此外,高速缓冲存储器可包括诸如6晶体管(6T)单元的相对快的存储器单元,或其他具有接近相等的或更快的访问速度的存储单元。
图2的计算机系统可以是诸如微处理器的总线代理的点对点(PtP)网络,这些总线代理在PtP网络上通过用于每个代理的总线信号通信。在每个总线代理中或者至少与之相关联的是是本发明的至少一个实施例206,使得存储操作能在总线代理之间以迅速的方式被推动。
图3示出了以点对点(PtP)配置安排的计算机系统。尤其,图3显示了其中处理器、存储器、以及输入/输出设备由多个点对点接口相互连接的系统。
图3的系统也包括多个处理器,为了清楚只显示其中的两个处理器370、380。处理器370、380中的每个处理器可包括与存储器22、24连接的本地存储器控制器集线器(MCH)372、382。处理器370、380可使用PtP接口电路378、388通过点对点(PtP)接口350交换数据。处理器370、380中的每个处理器可使用点对点接口电路376、394、386、398通过各PtP接口352、354与芯片组390交换数据。芯片组390也可通过高性能图形接口339与高性能图形电路338交换数据。
本发明的至少一个实施例可位于图3的每个PtP总线代理中的PtP接口电路中。然而,本发明的其他实施例可存在于图3的系统内的其他电路、逻辑单元、或设备中。此外,本发明的其他实施例可分布在图3示出的多个电路、逻辑单元或设备中。
尽管已经结合示出的实施例描述了本发明,但是描述并没有限制的含义。各种对于示出的实施例的更改以及对于本领域的技术人员显而易见的合适于本发明的其他实施例都被认为在本发明的精神和范围内。
Claims (30)
1.一种处理器,包括
具有第一时钟信号频率和第一操作电压的第一时钟域;
具有第二时钟信号频率和第二操作电压的第二时钟域;
具有第三时钟信号频率和第三操作电压的第三时钟域。
2.如权利要求1所述的处理器,其特征在于,所述第一时钟域包括指令解码器、重命名单元、定序器、重新排序缓冲器、以及分支预测单元。
3.如权利要求1所述的处理器,其特征在于,所述第二时钟域包括执行单元、寄存器文件、以及发出队列。
4.如权利要求1所述的处理器,其特征在于,所述第三时钟域包括二级高速缓冲存储器。
5.如权利要求1所述的处理器,其特征在于,每个时钟域包括先进先出队列以帮助在时钟域之间的同步操作。
6.如权利要求1所述的处理器,其特征在于,进一步包括具有第四和第五操作电压的第四和第五时钟域,其中所述第二、第四和第五时钟域能通过交叉开关互相发送信息。
7.如权利要求1所述的处理器,其特征在于,所述第一和第二时钟域的时钟信号频率和操作电压根据能量和延迟的平方的乘积的比率被控制,其中所述比率的分子是对于第一时间间隔的能量和延迟的平方的乘积,分母是对于第二时间间隔的能量和延迟的平方的乘积,所述第二时间间隔在所述第一时间间隔之前。
8.如权利要求6所述的处理器,其特征在于,所述第四或第五时钟域包括一级高速缓冲存储器和存储器排序缓冲器。
9.一种方法,包括:
确定用于第一时间间隔的处理器时钟域的能量和延迟;
确定用于第二时间间隔的处理器时钟域的能量和延迟,其中所述第二时间间隔在所述第一时间间隔之后;
调整处理器的第一组逻辑的操作电压和时钟信号,使得第二时间间隔的能量和延迟的乘积与第一时间间隔的能量和延迟的乘积的比率被最小化。
10.如权利要求9所述的方法,其特征在于,所述处理器的第一组逻辑是处理器内多个时钟域中的一个。
11.如权利要求10所述的方法,其特征在于,对于多个时钟域中的每一个单独地执行确定用于第一和第二时间间隔的能量和延迟以及调整操作电压和时钟信号频率。
12.如权利要求11所述的方法,其特征在于,所述多个时钟域依赖于参考时钟信号。
13.如权利要求12所述的方法,其特征在于,所述多个时钟域至少部分地通过对应于多个时钟域的多个先进先出(FIFO)队列被同步。
14.如权利要求13所述的方法,其特征在于,所述多个时钟域包括前端域、后端域、以及二级高速缓冲存储器域。
15.如权利要求14所述的方法,其特征在于,所述前端域包括指令解码器、重命名单元、定序器、重新排序缓冲器、以及分支预测单元。
16.如权利要求14所述的方法,其特征在于,所述后端域包括执行单元、寄存器文件、和发出队列。
17.如权利要求14所述的方法,其特征在于,所述后端域包括存储器排序缓冲器和一级高速缓冲存储器。
18.一种系统,包括:
存储多个指令的存储器;
处理器,所述处理器包括多个时钟域,所述多个时钟域具有取决于被处理器执行的多个指令的多个独立时钟频率和独立操作电压。
19.如权利要求18所述的系统,其特征在于,所述多个独立时钟频率和独立操作电压被调整使得对应于第一时间间隔的能量和延迟平方的乘积与对应于第二时间间隔的能量和延迟平方的乘积的比率对于多个时钟域中的每个时钟域被最小化。
20.如权利要求18所述的系统,其特征在于,所述多个时钟域包括多个功能单元以在多个处理器管线级内执行多个功能。
21.如权利要求20所述的系统,其特征在于,所述多个时钟域包括前端域,所述前端域包括指令解码器。
22.如权利要求21所述的系统,其特征在于,所述多个时钟域包括后端域,所述后端域包括执行单元以执行多个指令。
23.如权利要求22所述的系统,其特征在于,所述多个时钟域包括存储器域,所述存储器域包括二级高速缓冲存储器。
24.如权利要求21所述的系统,其特征在于,所述多个时钟域包括后端域,所述后端域包括存储器排序缓冲器和一级高速缓冲存储器。
25.如权利要求24所述的系统,其特征在于,所述多个时钟域中的每个时钟域包括至少一个先进先出队列,以暂时地存储与多个指令关联的存储数据直到相应的域能操作数据为止。
26.如权利要求25所述的系统,其特征在于,所述后端域包括多个执行单元以执行多个指令,以及多个交叉开关,通过所述多个交叉开关在多个执行单元之间发送信息。
27.一种包括存储在其上的一组指令的机器可读介质,当所述指令被机器执行时,导致机器执行一种方法,包括:
确定对于第一时间间隔的处理器时钟域的能量和延迟;
确定对于第二时间间隔的处理器时钟域的能量和延迟,其中所述第二时间间隔在所述第一时间间隔之后。
调整处理器的第一组逻辑的操作电压和时钟信号频率,使得第二时间间隔的能量和延迟的乘积被最小化。
28.如权利要求27所述的机器可读介质,其特征在于,所述第二时间间隔的能量和延迟的乘积与第一时间间隔的能量和延迟的乘积的比率被最小化。
29.如权利要求28所述的机器可读介质,其特征在于,所述处理器的第一组逻辑是处理器内的多个时钟域中的一个。
30.如权利要求29所述的机器可读介质,其特征在于,对于多个时钟域中的每一个单独地执行确定用于第一和第二时间间隔的能量和延迟以及调整操作电压和时钟信号频率。
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US7434073B2 (en) | 2004-11-29 | 2008-10-07 | Intel Corporation | Frequency and voltage scaling architecture |
US7490254B2 (en) | 2005-08-02 | 2009-02-10 | Advanced Micro Devices, Inc. | Increasing workload performance of one or more cores on multiple core processors |
US7949887B2 (en) | 2006-11-01 | 2011-05-24 | Intel Corporation | Independent power control of processing cores |
US20110106282A1 (en) | 2009-07-23 | 2011-05-05 | Corevalus Systems, Llc | Audio Processing Utilizing a Dedicated CPU Core and a Real Time OS |
US8321705B2 (en) | 2009-10-13 | 2012-11-27 | Advanced Micro Devices, Inc. | Dynamic table look-up based voltage regulator control |
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2004
- 2004-11-29 US US10/999,786 patent/US7434073B2/en not_active Expired - Fee Related
-
2005
- 2005-11-14 GB GB0705111A patent/GB2432939B/en not_active Expired - Fee Related
- 2005-11-14 CN CN200580033614A patent/CN100593155C/zh not_active Expired - Fee Related
- 2005-11-14 JP JP2007533796A patent/JP4860624B2/ja not_active Expired - Fee Related
- 2005-11-14 WO PCT/US2005/041392 patent/WO2006057865A2/en active Application Filing
- 2005-11-14 DE DE112005002416T patent/DE112005002416B4/de not_active Expired - Fee Related
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2007
- 2007-03-26 GB GBGB0705676.5A patent/GB0705676D0/en active Pending
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2008
- 2008-06-20 US US12/214,724 patent/US8407497B2/en active Active
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2011
- 2011-08-31 JP JP2011188311A patent/JP5159931B2/ja not_active Expired - Fee Related
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2013
- 2013-02-28 US US13/780,023 patent/US8689029B2/en not_active Expired - Fee Related
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CN101946219B (zh) * | 2008-02-20 | 2013-03-20 | 惠普开发有限公司 | 具有两个参考时钟的转接驱动器及其操作方法 |
CN102033788A (zh) * | 2009-10-05 | 2011-04-27 | 国际商业机器公司 | 微处理器中的电压和频率的可靠设置 |
CN102033788B (zh) * | 2009-10-05 | 2013-04-17 | 国际商业机器公司 | 微处理器中的电压和频率的可靠设置 |
US8566618B2 (en) | 2009-10-05 | 2013-10-22 | International Business Machines Corporation | Reliable setting of voltage and frequency in a microprocessor |
TWI463296B (zh) * | 2009-10-05 | 2014-12-01 | Ibm | 用於管理與一或多個電壓改變請求及一或多個頻率改變請求相關聯之操作的方法、資料處理系統及電腦程式產品 |
CN102314208A (zh) * | 2010-06-30 | 2012-01-11 | 重庆重邮信科通信技术有限公司 | 一种动态调整嵌入式设备频率电压的方法及装置 |
CN102314208B (zh) * | 2010-06-30 | 2016-08-03 | 重庆重邮信科通信技术有限公司 | 一种动态调整嵌入式设备频率电压的方法及装置 |
CN102445953A (zh) * | 2010-09-30 | 2012-05-09 | 重庆重邮信科通信技术有限公司 | 一种嵌入式设备时钟源的调整方法 |
CN102445953B (zh) * | 2010-09-30 | 2016-08-03 | 重庆重邮信科通信技术有限公司 | 一种嵌入式设备时钟源的调整方法 |
CN102707930A (zh) * | 2012-04-26 | 2012-10-03 | 苏州睿云智芯微电子有限公司 | 寄存器换名系统及方法 |
CN102707930B (zh) * | 2012-04-26 | 2015-04-08 | 苏州睿云智芯微电子有限公司 | 寄存器换名系统及方法 |
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JP2012009061A (ja) | 2012-01-12 |
US8407497B2 (en) | 2013-03-26 |
US7434073B2 (en) | 2008-10-07 |
US20130173948A1 (en) | 2013-07-04 |
JP2008515065A (ja) | 2008-05-08 |
US8689029B2 (en) | 2014-04-01 |
GB2432939A (en) | 2007-06-06 |
US9047014B2 (en) | 2015-06-02 |
US20080263376A1 (en) | 2008-10-23 |
US20060117202A1 (en) | 2006-06-01 |
JP5159931B2 (ja) | 2013-03-13 |
GB0705676D0 (en) | 2007-05-02 |
DE112005002416T5 (de) | 2007-10-18 |
GB0705111D0 (en) | 2007-04-25 |
WO2006057865A2 (en) | 2006-06-01 |
DE112005002416B4 (de) | 2009-04-30 |
US20140164802A1 (en) | 2014-06-12 |
GB2432939B (en) | 2009-01-21 |
WO2006057865A3 (en) | 2006-12-14 |
JP4860624B2 (ja) | 2012-01-25 |
CN100593155C (zh) | 2010-03-03 |
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