CN101034672A - 形成栅极图形的双重曝光双重抗蚀剂层工艺 - Google Patents
形成栅极图形的双重曝光双重抗蚀剂层工艺 Download PDFInfo
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- CN101034672A CN101034672A CNA2007100847361A CN200710084736A CN101034672A CN 101034672 A CN101034672 A CN 101034672A CN A2007100847361 A CNA2007100847361 A CN A2007100847361A CN 200710084736 A CN200710084736 A CN 200710084736A CN 101034672 A CN101034672 A CN 101034672A
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- 238000013461 design Methods 0.000 description 4
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/308,106 US7473648B2 (en) | 2006-03-07 | 2006-03-07 | Double exposure double resist layer process for forming gate patterns |
US11/308,106 | 2006-03-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101034672A true CN101034672A (zh) | 2007-09-12 |
CN100536091C CN100536091C (zh) | 2009-09-02 |
Family
ID=38479480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2007100847361A Expired - Fee Related CN100536091C (zh) | 2006-03-07 | 2007-02-28 | 形成平面场效应晶体管和在集成电路中形成层的方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7473648B2 (zh) |
JP (1) | JP5567248B2 (zh) |
CN (1) | CN100536091C (zh) |
TW (1) | TW200741977A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101859065A (zh) * | 2009-04-07 | 2010-10-13 | 国际商业机器公司 | 减轻双曝光工艺中的抗蚀剂图案关键尺寸变化的方法 |
CN102323716A (zh) * | 2011-07-07 | 2012-01-18 | 西北工业大学 | 一种纳米结构的图形转移制作方法 |
CN105931287A (zh) * | 2015-02-27 | 2016-09-07 | 多佑惠立方株式会社 | 基于半导体工艺的三维虚拟形状建模方法 |
CN106610563A (zh) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | 掩膜版及双重图形化法的方法 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7767570B2 (en) * | 2006-03-22 | 2010-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy vias for damascene process |
US7704680B2 (en) * | 2006-06-08 | 2010-04-27 | Advanced Micro Devices, Inc. | Double exposure technology using high etching selectivity |
TW200810224A (en) * | 2006-08-15 | 2008-02-16 | Univ Yuan Ze | Method for producing fuel cell with micro-sensor and polymer material |
US20090011370A1 (en) * | 2007-06-11 | 2009-01-08 | Hiroko Nakamura | Pattern forming method using two layers of resist patterns stacked one on top of the other |
TW200926261A (en) * | 2007-12-12 | 2009-06-16 | Nanya Technology Corp | Method of forming iso space pattern |
JP5398158B2 (ja) * | 2008-03-27 | 2014-01-29 | 三菱電機株式会社 | パターン形成方法、及び配線構造、並びに電子機器 |
US8001495B2 (en) | 2008-04-17 | 2011-08-16 | International Business Machines Corporation | System and method of predicting problematic areas for lithography in a circuit design |
US8377795B2 (en) * | 2009-02-12 | 2013-02-19 | International Business Machines Corporation | Cut first methodology for double exposure double etch integration |
US8399183B2 (en) * | 2009-05-13 | 2013-03-19 | Synopsys, Inc. | Patterning a single integrated circuit layer using automatically-generated masks and multiple masking layers |
CN102983066B (zh) * | 2011-09-05 | 2015-06-17 | 中国科学院微电子研究所 | 混合线条的制造方法 |
US8875067B2 (en) * | 2013-03-15 | 2014-10-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reusable cut mask for multiple layers |
US11004729B2 (en) | 2018-06-27 | 2021-05-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor devices |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6605541B1 (en) * | 1998-05-07 | 2003-08-12 | Advanced Micro Devices, Inc. | Pitch reduction using a set of offset masks |
JP3669681B2 (ja) * | 2000-03-31 | 2005-07-13 | 株式会社東芝 | 半導体装置の製造方法 |
JP2002055432A (ja) * | 2000-08-10 | 2002-02-20 | Matsushita Electric Ind Co Ltd | フォトマスク装置及びパターン形成方法 |
JP4776813B2 (ja) * | 2001-06-12 | 2011-09-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4040515B2 (ja) * | 2003-03-26 | 2008-01-30 | 株式会社東芝 | マスクのセット、マスクデータ作成方法及びパターン形成方法 |
JP2005197349A (ja) * | 2004-01-05 | 2005-07-21 | Semiconductor Leading Edge Technologies Inc | 微細パターン形成方法及び半導体装置の製造方法 |
-
2006
- 2006-03-07 US US11/308,106 patent/US7473648B2/en not_active Expired - Fee Related
-
2007
- 2007-02-21 JP JP2007040403A patent/JP5567248B2/ja not_active Expired - Fee Related
- 2007-02-28 CN CNB2007100847361A patent/CN100536091C/zh not_active Expired - Fee Related
- 2007-03-01 TW TW096107051A patent/TW200741977A/zh unknown
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101859065A (zh) * | 2009-04-07 | 2010-10-13 | 国际商业机器公司 | 减轻双曝光工艺中的抗蚀剂图案关键尺寸变化的方法 |
CN101859065B (zh) * | 2009-04-07 | 2012-11-28 | 国际商业机器公司 | 减轻双曝光工艺中的抗蚀剂图案关键尺寸变化的方法 |
US9316916B2 (en) | 2009-04-07 | 2016-04-19 | Globalfounries Inc. | Method to mitigate resist pattern critical dimension variation in a double-exposure process |
CN102323716A (zh) * | 2011-07-07 | 2012-01-18 | 西北工业大学 | 一种纳米结构的图形转移制作方法 |
CN105931287A (zh) * | 2015-02-27 | 2016-09-07 | 多佑惠立方株式会社 | 基于半导体工艺的三维虚拟形状建模方法 |
CN106610563A (zh) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | 掩膜版及双重图形化法的方法 |
CN106610563B (zh) * | 2015-10-22 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | 掩膜版及双重图形化法的方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2007243177A (ja) | 2007-09-20 |
CN100536091C (zh) | 2009-09-02 |
JP5567248B2 (ja) | 2014-08-06 |
US20070212863A1 (en) | 2007-09-13 |
TW200741977A (en) | 2007-11-01 |
US7473648B2 (en) | 2009-01-06 |
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Effective date of registration: 20171107 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171107 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
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Granted publication date: 20090902 Termination date: 20190228 |