CN101023717A - 电极基板 - Google Patents

电极基板 Download PDF

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Publication number
CN101023717A
CN101023717A CNA2005800266184A CN200580026618A CN101023717A CN 101023717 A CN101023717 A CN 101023717A CN A2005800266184 A CNA2005800266184 A CN A2005800266184A CN 200580026618 A CN200580026618 A CN 200580026618A CN 101023717 A CN101023717 A CN 101023717A
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China
Prior art keywords
electrode
wiring substrate
circuit board
substrate
electronic
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Granted
Application number
CNA2005800266184A
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English (en)
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CN101023717B (zh
Inventor
森山英二
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Ricoh Microelectronics Co Ltd
Ricoh Co Ltd
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Ricoh Microelectronics Co Ltd
Ricoh Co Ltd
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Publication of CN101023717A publication Critical patent/CN101023717A/zh
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Publication of CN101023717B publication Critical patent/CN101023717B/zh
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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    • H05K3/341—Surface mounted components

Abstract

本发明涉及一种电极基板，在利用铜进行了配线的由玻璃环氧树脂构成的基板(153)表面形成有多个电极的PWB(150)中，形成有未设置由金构成的Au表面层的非Au电极(151)和设有Au表面层的Au电极(152)两者作为所述电极。另外，在非Au电极(151)的表面形成有由与金不同的材料即焊剂构成的氧化抑制膜(154)。通过由该氧化抑制膜(154)抑制非Au电极(151)的氧化，从而可制作PWB(150)。

Description

电极基板
技术领域
本发明涉及在用于安装IC芯片及片状电容等电子部件的由绝缘材料构成的基板表面形成有多个电极的印刷线路板等配线基板。
背景技术
目前，在这种配线基板上安装有电子部件的模块基板等电子电路板在各种电气设备中正被广泛使用。在电气设备的小型化前进的近年来，IC芯片的配线基板上的安装区域也实现相当的省空间化。使用图1、图2及图3说明这样的省空间化的情况。图1是表示作为IC芯片的QFP(Quad Flat Package)的主要部分构成图。图2是表示通过利用引线接合将作为IC芯片的裸片2与配线基板接合的旧式的COB(Chip on Board)工序法制造的电子电路板的主要部分构成图。另外，图3是表示通过将裸片作为倒装片安装的新式的COB工序法制造的电子电路板的主要部分构成图。
图1所示的QFP具有表面形成有多个电极焊盘1的裸片2、多个引线电极3、用于密封裸片2周围的由树脂材料构成的封装件4等。从封装件4的侧面海鸥展翅状突出的多个引线电极3是用于将被封装件4内包的裸片2的电输入输出导出到未图示的配线基板的电极。在封装件4内，形成于裸片2表面上的电极焊盘1和引线电极3的端部通过由金构成的接合线5连接。该连接利用众所周知的引线接合工序法进行。在这种构成的QFP中，在封装件4的外部海鸥展翅状突出或在封装件4的内部朝向裸片2正直延伸的引线电极3占去了未图示的配线基板上的安装区域的一大半。
在图2所示的电子电路基板中，裸片2不是以由树脂材料密封的封装件的状态，而是以不由树脂材料密封的裸的状态安装于配线基板100上。具体而言，装配于配线基板100上的裸片2的多个电极焊盘1通过引线接合工序法与配线基板100上形成的多个电极101的任一个接合线连接。由于进行该接合线连接，从而不需要图1所示的QFP中使用的引线电极，因此，能够实现安装区域的省空间化。另外，也可以设置密封配线基板100上安装的裸片2的由树脂材料构成的封装件4。
在图3所示的电子电路板中，裸片2也以不由树脂材料密封的裸的状态安装于配线基板100上，但与图2所示的电子电路板的不同点是安装的裸片2的姿势。具体而言，在图2所示的电子电路板中，裸片2以使作为其电极焊盘形成面的主面朝向垂直方向上方的正规的姿势安装于配线基板100上。与之相对，在图3所示的电子电路板中，裸片2以其主面朝向垂直方向下方的姿势即面朝下的倒装片的状态安装于配线基板100上。这样的裸片2的安装通过SMT(Sutface Mount Technology)进行。SMT中，首先在配线基板100的电极101上通过掩模印刷法印刷焊锡膏块。其次，将片状部件装配到配线基板100上，使得IC芯片或片状电容等片状部件的下面形成的电极焊盘1与已印刷的焊锡膏块接触。然后，利用软熔工序使焊锡膏块内的焊锡粒熔融固化，由此利用焊锡6将配线基板100的电极101和片状部件的电极焊盘接合。在通过这样的SMT将裸片2作为倒装片安装的图3的电子电路板中，与图2所示的电子电路板不同，不设置采用引线接合的接合线，而在配线基板上安装裸片2。而且，由此接合线5不会飞出裸片2的周围，从而能够实现安装区域的省空间化。
另外，在软熔工序之后，在裸片2的图中下面和配线基板100的表面之间形成间隙，但该间隙由未充满材料7埋没。
再有，作为制造图3所示的电子电路板的方法，已知有专利文献1或专利文献2中记载的方法。
作为配线基板100的电极101，通常在铜等金属母材表面形成设置有通过电解镀金处理得到的Au表面层的结构。设置Au表面层的理由如下。即，作为配线基板100的镀金101的金属母材，通常使用铜及铝等，但由于他们都是容易氧化的金属材料，故其表面容易被氧化膜覆盖。被氧化膜覆盖了的金属母材弹到熔融焊锡上，因此难以进行良好的焊接。为了能够进行良好的焊接，而考虑对露出的金属母材进行氧化膜除去处理，之后直接进行焊接，该方法中能够大量制造配线基板100。当将金属母材在容易氧化的露出的状态下放置时，会产生放置期间的不同而造成的电极101的电特性的偏差，从而不能维持稳定的品质。当不制造配线基板100，而连续实施配线基板100的制造工序和电子部件对制造后的配线基板100进行安装的安装工序时，与制造的情况相比，生产成本不良，导致成本升高。因此，作为电极101，其为形成在金属母材表面设置Au表面层的结构。通过利用非常难以氧化的金属材料即金(Au)对金属母材表面进行涂敷，从而即使大量制造配线基板100，也能够防止电极101表面的氧化，且能够维持容易与焊锡接合的状态。
专利文献1：特开2001-308268号公报
专利文献2：特开2003-282630号公报
在专利文献1或专利文献2中记载的电子电路板制造方法中，将裸片2和配线基板100接合的焊锡6都有可能显著脆弱化。具体而言，如上所述，作为配线基板100的电极101，通常使用形成设有电解镀金处理得到的Au表面层的结构。另一方面，近年来，伴随芯片制造技术发展带来的裸片2的小型化，裸片2的电极焊盘1也变得非常小。而且，与此同时，形成于配线基板100上的电极101也为例如直径250μm以上的大小，而直径250μm以下的大小即为小型化。在这种小型的电极101上印刷焊锡膏块的印刷工序中，为使焊锡膏从构成印刷掩模的印刷图案的微小的贯通孔良好地脱出，而需要使印刷掩模的厚度相当薄。这样，在将膏块的厚度设薄的近些年，介于基板100的电极101和裸片2的电极焊盘1之间的焊锡6的每单位面积的量相当小。当通过软熔使电极101上印刷的焊锡膏块的焊锡粒熔融时，电极101的Au表面层的金析出到熔融焊锡中，如果该析出量过多，则固化后的焊锡6显著变脆。在焊锡6的每单位面积的量相当少的近些年，有金对焊锡6的析出量的比例相当大的倾向，因此，容易使焊锡6显著脆弱化。
本发明者对减小电极101的Au表面层的厚度，减少金对焊锡6的析出量进行了探讨。在电解电镀处理中，使Au表面层的厚度小至2μm程度是一个限度，其不能驻留在能够避免焊锡6脆弱化的程度的金析出量。但是，在无电解电镀处理中，能够将Au表面层的厚度减小到数百nm程度，因此，能够充分避免焊锡6的脆弱化。因此，本发明者尝试形成设有无电解电镀处理得到的Au表面层的结构作为电极101，但焊锡6不能良好地对这样的电极101接合。其理由判断为是由于，在薄度极厚(極めて薄厚)的Au表面层形成不能看到的多个微细孔，通过该微细孔露出Au表面层下的金属材料，由此形成氧化膜。
因此，本发明者下面制造了如下部件，作为配线基板100，通过由不同于金的材料构成的焊接的膜覆盖未设置Au表面层的电极101的表面，在电极101之上形成氧化抑制膜。而且，在将这种配线基板100放置规定期间后，尝试通过SMT对该配线基板100安装裸片2(倒装片)。于是，熔融焊锡不会在电极101上弹起，而能够将裸片2与配线基板100良好地接合。进而还可以对固化后的焊锡6发挥足够的强度。因此，若由作为非金属材料的焊剂的膜覆盖未设置Au表面层的电极101的表面，则能够大量制作配线基板100而实现低成本化，同时能够使焊锡6发挥充分的强度。
但是，在这样的配线基板100中，不能使配线基板100上形成的多个电极101的局部作为接点电极起到良好的作用。具体而言，在目前的电气设备中，有时配线基板100的全部多个电极101不能起到焊接用的电极的作用，而只有其局部起到接点电极的作用。接点电极是作为电子设备主体和与之拆装的电子器件之间的电接点起作用的电极。例如，在家庭用电视游戏机中为对游戏机主体拆装存储游戏软件的ROM盒的构成。在这样的构成中，需要用于将游戏机主体和ROM盒连接的接点电极。因此，使设于ROM盒的电子电路板上的接点电极随着盒的拆装在游戏机主体侧的接点电极上滑动移动，同时将两接点电极连接的家庭用电视游戏机大量上市。另外，在对手机主体拆装作为电子器件的电池组的手机中，通常利用同样的接点电极将电话机主体和电池组连接。在这些接点电极中，其表面未被焊锡覆盖而一直露出。因此，期望设置Au表面层，使得不会引起导通性随氧化进行的降低。另外，在使接点电极之间随着电子器件的拆装而滑动时，Au表面层起到特别有效的作用。由于金是摩擦系数较小的金属材料，故其能够抑制滑动摩擦时的接点电极之间的牵连，从而能够顺畅地拆装。
另一方面，在芯片制造技术的发展带来的裸片2的处理速度的高速化前进的目前，伴随该高度化，期望裸片2和其他电子部件之间的信号传输速度的高速化或噪声混入的降低化。但是，在上述专利文献1或专利文献2中，对能够实现信号传输速度的高速化或噪声混入的降低化的技术没有任何提及。
另外，在上述专利文献1或专利文献2中记载的电子电路板制造方法中，该未充满处理因裸片2的构成而非常困难。这是由于下面说明的理由。即，通常裸片2的电极形成面如图4所示，多个电极焊盘1在周缘部集中形成，且中央部成为没有电极的区域。在这样的裸片2的未充满处理中，如图5的箭头所示，从将裸片2和配线基板100接合的多个焊锡6之间形成的开口流入未充满材料，通过毛细管现象交接到芯片中央部的正下方。但是，当该开口过小时，不能得到充分的毛细管现象，且未充满处理非常困难。
发明内容
本发明是鉴于以上情况而构成的，其第一目的在于，提供如下的配线基板、电子电路板、电子电路板制造方法。即，是避免配线基板的电极表面的金大量析出到焊锡中造成的焊锡脆弱化，同时能够使多个电极的一部分作为接点电极起到良好的作用的配线基板等。
另外，其第二目的在于，在上述第一目的的基础上，提供能够通过制作而实现低成本化的配线基板等。
再有，其第三目的在于，在上述第一或第二目的的基础上，提供能够实现电子部件间的信号传输速度的高速化或噪声混入的降低的电子电路板及制造该电路板的电子电路板制造方法。
其第四目的在于，在上述第三目的的基础上，提供能够容易地进行小型电子部件的未充满处理的电子电路板及制造该电路板的电路板制造方法。
上述本发明的目的如下实现，提供一种配线基板，其在通过导电性物质进行了配线的由绝缘材料构成的基板表面形成多个电极，其特征在于，作为所述电极，形成有未设置由金构成的Au表面层的非Au电极和设有该Au表面层的Au电极两者。
上述本发明的目的如下实现，提供一种电子电路基板，在通过导电性物质进行了配线的由绝缘材料构成的基板表面形成有多个电极的配线基板上将具有用于与该电极接合的接合用电极的多个电子部件进行表面安装，其特征在于，所述配线基板具有作为所述电极的未设置由金构成的Au表面层的非Au电极和设有该Au表面层的Au电极两者，多个所述电子部件中的至少之一作为所述接合用电极具有设有由金构成的Au表面层的结构，该Au电极的该Au表面层具有面积比其侧面大的平坦的接合面，且该接合面与所述配线基板的所述非Au电极进行焊接。
上述本发明的目的如下实现，提供一种电子设备，其具有电子电路板和覆盖该电路板的框体，其中，电子电路板在通过导电性物质进行了配线的由绝缘材料构成的基板表面形成有多个电极的配线基板上将具有用于与该电极接合的接合用电极的多个电子部件进行表面安装，其特征在于，使用所述配线基板作为该配线基板。
上述本发明的目的如下实现，提供一种电子电路板制造方法，其通过实施在由导电性物质配线的由绝缘材料构成的基板表面形成有多个电极的配线基板的该电极上印刷由含有导电性接合材料的膏构成的膏块的印刷工序、经由该膏块在该配线基板上载置多个电子部件的载置工序、为将该膏块中的该导电性接合材料熔融与该电极接合而将设于各多个电子部件上的接合用电极和该配线基板的该电极接合的接合工序，由此制造将多个电子部件表面安装于该配线基板上的电子电路板，其特征在于，使用所述配线基板作为该配线基板。
根据本发明，可提供一种能够避免配线基板的电极表面的金大量析出到焊锡中造成的焊锡的脆弱化，同时能够使多个电极的局部作为接点电极良好地起作用的配线基板等。
另外，可提供能够通过制作来实现低成本化的配线基板等。
再有，可提供能够实现电子部件间的信号传输速度的高速化或噪声混入的降低化的电子电路板及制造该电路板的电子电路板制造方法。
另外，可提供能够容易地进行小型电子部件的未充满处理的电子电路板及制造该电路板的电子电路板制造方法。
附图说明
图1是表示现有的QFP的概略构成图；
图2是表示通过旧式的COB工序法制造的现有的电子电路板的概略构成图；
图3是表示通过新式的COB工序法制造的现有的电子电路板的概略构成图；
图4是表示安装于同一电子电路板上的裸片的电极形成面的平面图；
图5是将同一电子电路板放大表示的立体图；
图6是从第一面侧表示实施例的PWB的平面图；
图7是表示从第二面侧表示同一PWB的平面图；
图8是表示同一PWB的局部放大剖面图；
图9是表示实施例的电子电路板制造方法中使用的塑料掩模的局部放大剖面图；
图10是表示在利用同电子电路板制造方法制造的模块基板上安装的倒装片的电极形成面的平面图；
图11是将同一塑料掩模的半蚀刻部放大表示的平面图；
图12是表示同一电子电路板制造方法的印刷工序中实施的涂膏工序的剖面图；
图13是表示同一印刷工序中实施的掩模剥离工序的剖面图；
图14是表示同一电子电路板制造方法中的载置工序的剖面图；
图15是表示同一电子电路板制造方法中的软熔工序的剖面图；
图16是表示同一电子电路板制造方法中的未充满工序的剖面图；
图17是表示同一未充满工序的立体图；
图18是说明在锂电池上固定由同一电子电路板制造方法制造的模块基板的平面图；
图19是表示使用了同一锂电池、同一模块基板的备用电池和手机的手机主体的立体图；
图20是表示利用同一电子电路板制造方法在同一PWB上安装的倒装片的放大剖面图；
图21是表示利用现有的电子电路板制造方法在同一PWB上安装的倒装片的放大剖面图；
图22是表示安装该现有的倒装片的PWB的放大剖面图；
图23是表示该现有的倒装片的载置工序的放大剖面图；
图24是表示安装于PWB上的该现有的倒装片的放大剖面图。
符号说明
150  PWB(配线基板)
151  非Au电极
152  Au电极
153  基板
203  膏块
301  倒装片(接合用电极的平面面积最小的部件)
301a 电极焊盘(接合用电极)
302  SMD(电子部件)
502  未充满材料
具体实施方式
下面，对作为应用了本发明的配线基板的PWB、作为电子电路板的模块基板及电子电路板制造方法的一实施例进行说明。
首先，对用于电子电路板制造的作为配线基板的PWB(Printed WiringBoard)进行说明。图6是从作为一侧面的第一面侧表示PWB150的平面图。同图中，利用众所周知的技术在PWB150的第一面形成由多个非Au电极151构成的电极图案。在这样的第一面上存在电极组安装区域R1、SMD(SurfaceMount Device)安装区域R2、倒装片安装区域R3。电极组安装区域R1是用于安装后述的电极组的区域，该区域内的电极图案的非Au电极151都形成为矩形状，长度为10mm左右，成为相当大的结构。SMD安装区域R2是用于表面安装与裸片不同的片状电容等这样的电子部件的区域，该区域内的电极图案的非Au电极151为其平面面积都为0.049[mm2]以上的小型的结构。另外，倒装片安装区域R3是用于表面安装作为倒装片的裸片的区域，该区域内的电极图案的非Au电极151为其平面面积都为0.049[mm2]以下的超小型的结构。
图7是从作为其他面的第二面侧表示本实施例的PWB150的平面图。同图中，利用众所周知的技术在PWB150的第二面形成有由多个Au电极152构成的电极图案。在这样的第二面上存在负极用接点电极形成区域R4、正极用接点电极形成区域R5、负极用测试电极形成区域R6、正极用测试电极形成区域R7。在负极用接点电极形成区域R4上形成有一个矩形平面形状的大型的Au电极152，其作为负极用接点电极起作用。在正极用接点电极形成区域R5上形成有一个矩形平面形状的大型的Au电极152，其作为正极用接点电极起作用。另外，在负极用测试电极形成区域R上形成有一个圆形平面形状的中型的Au电极152，其作为负极用测试电极起作用。再有，在正极用测试电极形成区域R7上形成有一个圆形平面形状的中型的Au电极152，其作为正极用测试电极起作用。
图8是表示本实施例的PWB150的局部放大剖面图。同图中，将面向图中上方的面表示为第一面，将面向图中下方的面表示为第二面。PWB150由非Au电极151、Au电极152、利用作为绝缘材料的玻璃环氧树脂构成的基板153、氧化抑制膜154、抗蚀剂层155等构成。PWB150的第一面上形成的多个非Au电极151都为由作为金属母材的铜构成的单层结构。先前所示的图6中，为了说明方便而省略图示，这些非Au电极151的表面由氧化抑制膜154覆盖，其中氧化抑制膜通过由与金不同的材料构成的焊剂构成。另外，非Au电极151的厚度为35[μm]。
在PWB150的第一面，在未形成有非Au电极151的基板区域覆盖有第一抗蚀剂层155a，非Au电极151的表面、第一抗蚀剂层155a的表面为相同的高度。该第一抗蚀剂层155a在利用众所周知的光刻法的非Au电极形成工序中形成于基板153的第一面上。
也可以使用焊剂以外的材料作为形成氧化抑制膜154的材料。但是，与金不同的材料是绝对条件。这是由于当使用金时会引起焊锡的脆弱化。另外，在可能出现焊锡因金以外的金属材料的析出而脆弱化的情况下，用非金属材料形成氧化抑制膜154最佳。焊剂为不同于金的材料，且为非金属材料。
作为焊剂，可使用以松香为主成分的目前公知的材料。该松香为构成焊剂的主成分，其由松香酸等脂肪族炭酸构成。由于这样的松香抑制电极表面的氧化，从而可良好的发挥熔融焊锡对电极表面的润湿性。除松香以外，还可以使用添加了二乙胺盐酸盐、环己胺溴氢酸盐等脂肪族胺卤化氢酸盐、琥珀酸、丙二酸、等脂肪族炭酸等提高除氧化物作用的物质的材料。另外，也可以以各种非金属性有机物或非金属制无机物为焊剂的主成分代替松香。焊剂为在乙醇类等溶剂中溶解了松香等的状态，如果其过多地涂敷于非Au电极151的表面，则溶剂蒸发，成为大致固形的状态的氧化抑制膜154。若在PWB150的整个第一面涂敷焊剂，则第一抗蚀剂层155a上的焊剂会弹起，而汇集在非Au电极1的表面。因此，通过只在整个面上涂敷，可在非Au电极1的大致整个表面形成氧化抑制膜154。
在形成于基板153的第一面上的多个非Au电极151中，在倒装片安装区域R3形成的电极都为其平面截面为100[μm]×100[μm]的矩形。
形成于PWB150的第二面上的Au电极152都具有由作为金属母材的铜构成的母材层152a、由覆盖于其上的镍(Ni)构成的中间层152b、由覆盖于其上的金(Au)构成的Au表面层152c。中间层152b通过众所周知的镀镍处理而覆盖在母材层152a上，其具有在由难以粘合金的铜(Cu)构成的母材层152a上良好地固定Au表面层152c的功能。Au表面层152c通过众所周知的电解镀金处理覆盖在中间层152b上。中间层152b、Au表面层152c都有数[μm]程度的厚度。
在PWB150的第二面上，在未形成Au电极152的基板区域覆盖有第二抗蚀剂层155b，Au电极152的表面和第二抗蚀剂层155b的表面为相同的高度。该第二抗蚀剂层155b是在采用众所周知的光刻法的非Au电极形成工序中形成于基板153的第二面上的层。
在以上构成的PWB150中，形成未设置由金构成的Au表面层的非Au电极151和设置了Au表面层152c的Au电极152两者作为由作为绝缘材料的玻璃环氧树脂构成的基板153上形成的电极，同时在非Au电极151的表面形成由作为非金属材料的焊剂构成的氧化抑制膜154。这样的构成中，通过由焊剂构成的氧化抑制膜154抑制未设置Au表面层的非Au电极151的表面氧化，由此确保非Au电极151的表面长期良好地配合焊锡的状态。而且，由此可大量制作PWB150，实现电子电路板的低成本化。另外，若对非Au电极151焊剂裸片等小型的电子部件，则即使在因例如该小型电子部件的电极焊盘极小而可能使介于电极焊盘和非Au电极151之间的焊锡为微量的情况下，也不会产生从非Au电极151向焊锡析出大量的金的事态。因此，可避免电极表面的金向焊锡中大量析出造成的焊锡的脆弱化。另外，除非Au电极151之外，还形成有设置了Au表面层152c的Au电极152，因此，可防止母材层152a的氧化，使其作为后述的接点电极(例如滑动方式)良好地发挥功能。
另外，在本实施例的PWB150中，在基板153的两面分别形成多个电极，将在作为基板153的一侧面的第一面形成的全部多个电极设为非Au电极151，且将在作为基板153的另一侧面的第二面形成的全部多个电极设为Au电极152。在这样的构成中，与对基板153的同一面混合形成非Au电极及Au电极这种种类相互不同的电极的情况相比，简化了电极形成工序。而且，由此能够降低制造成本。
另外，在本实施例的PWB150中，对于全部的非Au电极151中至少形成于倒装片安装区域R3内的电极而言，平面面积区域低于0.049[mm2]，且全部的Au电极152为0.049[mm2]以上的平面面积。在这样的构成中，通过倒装片安装区域R3内的非Au电极151为低于0.049[mm2]的平面面积，能够将其作为小型倒装片的安装用进行使用。而且，由此即使为正在小型化的近年来的小型裸片，也可以将其作为倒装片安装于基板153的第一面上。由于整个Au电极152为0.049[mm2]以上的平面面积，从而能够通过Au表面层152a抑制基板153的第二面形成的全部电极的氧化。
图9是表示对本实施例的PWB150进行采用STM的表面安装时使用的作为印刷掩模的塑料掩模的局部放大剖面图。同图中，塑料掩模200是对由PET(聚对苯二甲酸乙醇酯)等塑料材料构成的塑料板201形成由准分子激光器加工形成的多个贯通孔202构成的印刷图案的印刷掩模。该印刷图案与本实施例的PWB的第一面形成的电极图案相对应。塑料掩模200面方向的整个区域中的图中8R所示的区域为比其他区域凹陷的半蚀刻部203。该凹陷也通过准分子激光器加工形成。使用厚度75[μm]的材料作为塑料板201，通过由准分子激光器加工进行的20[μm]的深度掘入，半蚀刻部203的厚度达到50[μm]。
形成这种半蚀刻部203的图中R8的区域与先前图4所示的PWB150的第一面的倒装片安装区域R3相对应。利用塑料掩模200的半蚀刻部203上形成的多个贯通孔202，在形成于PWB150的倒装片安装区域R3的多个倒装片安装用非Au电极151上分别印刷微小的焊锡膏块。如图9所示，形成于半蚀刻部203内的多个贯通孔202的直径都比形成于半蚀刻部203的外部的多个贯通孔202的直径小很多。这是由于倒装片的电极焊盘的大小极小。即使是这种小径的贯通孔202，也可以通过形成半蚀刻部203来减小其长度而防止焊锡膏从孔内顺畅地脱出。另外，通过准分子激光器加工而形成的贯通孔202通过利用消融(ァブレ一ション)现象掘入而达到优良的内壁平滑性，因此，与金属掩模上形成的贯通孔相比，能够提高焊锡脱离性。
图10是表示倒装片301的电极形成面的平面图。如图所示，在该电极形成面上，在周缘部集中形成有六个电极焊盘301a。更详细地说，在与四角形电极形成面的四边对应的四个缘部中相对向的两个缘部分别形成有由作为接合用电极的三个电极焊盘301a构成的电极列。着眼于剩下的两个缘部，电极列一端的电极焊盘301a分别位于缘部的两端附近。位于该两端附近的两个电极焊盘301a之间的距离L1为500[μm]以上。与之相对，形成有电极列的两个缘部的电极焊盘之间的距离L2为低于500[μm]。另外，各电极焊盘301a的平面面积为100[μm]×100[μm]＝0.01[mm2]以上，这在上述PWB(150)上安装的多个电子部件的电极焊盘中成为最小的值。另外，如先前的图5所示，在周缘部存在多个电极列的情况下，对于至少一个缘部来说，在与之相连的其他两个缘部相互对向的最靠中央的电极列间的距离需要为500[μm]以上。
图11是将塑料掩模200的区域R8放大表示的平面图。对于印刷掩模的贯通孔来说，通常其开口形成为圆形。但是，如图10所示的倒装片301的电极焊盘301a，在对应非常小的电极的极小径的贯通孔中，当开口为圆形时，难以将印刷工序中压装的焊锡膏良好地充填到贯通孔内。本发明者发现，对于这种极小径的贯通孔而言，如图11所示，其开口为菱形，且该菱形的尖的边缘朝向焊锡的压装方向(图中箭头方向)而形成，由此，能够将焊锡膏良好地充填到贯通孔内。因此，在本实施例的电子电路板制造方法中，使用这样形成区域R8内(半蚀刻部内)的贯通孔的结构作为塑料掩模200。另外，在同图中，菱形开口的长度方向的长度L3为130[μm]。纵向方向的长度L4为100[μm]。
图12、图13、图14、图15及图16是分别表示在本实施例的PWB150上安装电子部件而构成作为电子电路板的模块基板的电子电路板制造方法的各工序的说明图。另外，图中符号302表示作为电子部件的SMD。符号301表示倒装片。在本电子电路板制造方法中，首先如图12及图13所示，使用塑料掩模200在PWB150的第一面的各非Au电极151上分别印刷焊锡膏块203(印刷工序)。其次，如图14所示，使用众所周知的芯片架将各种电子部件(301、302)及未图示的镍块装配在完成焊锡膏印刷的PWB150上(载置工序)。然后，如图15所示，通过在软熔炉内将PWB150升温，将各焊锡膏块203内的未图示的焊锡粒熔融，由此将各种电子部件的电极焊盘(391a、302a)及电极组焊接在PWB150的第一面的非Au电极151上(接合工序)。
图20是将上述载置工序中的PWB150上的倒装片301放大表示放大剖面图。倒装片301被装配在PWB150的形成有非Au电极151的第一面和形成有Au电极152的第二面中的第一面上。在第一面上形成有非Au电极151，在其表面如上述那样覆盖了氧化抑制膜154。在上述印刷的凹低处，在该氧化抑制膜154上印刷焊锡膏块203，倒装片301以使作为其接合用电极的电极焊盘301a与该焊锡膏块203重合的方式装配的第一面上。倒装片301的作为接合用电极的电极焊盘301a由平坦的金属母材焊盘301b和Au表面层301c构成，其中金属母材焊盘由镍及铝等非Au材料构成，Au表面层由覆盖于其表面的金构成。该Au表面层301c未形成有在目前通常使用的倒装片的接合用电极的表面使用的金补片(バンプ)(参照图21)这样的突起，而为图示的扁平形状。由于Au表面层301c为扁平的形状，故与基板电极接合的接合面(面向图中上方的面)的面积远比其侧面(厚度方向的面)的面积大。若将形成有这种Au表面层301c的倒装片301装配到PWB150的第一面上，则如图所示，会成为Au表面层301只与焊锡膏块203的表面接触的状态。若在这种状态下进行软熔工序，则与在将图24所示的金补片301f插入焊锡膏块203内的状态下进行软熔工序的情况相比，能够降低金向熔融焊锡中析出的量。由此，能够抑制用于倒装片接合用电极的金向熔融焊锡中析出造成的焊接的脆弱化。
另外，本发明者通过进行试验确认了：在Au表面层301c如图20那样构成为扁平的情况下，在将倒装片301通过支架装配在PWB150上时，焊锡膏块203被压碎，从而可能不能确保芯片下面和基板面之间所需要的间隙。但是，着重进行支架的控制，在使倒装片301与焊锡膏块203接触之前，使支架的臂(在其前端保持芯片)的速度低于目前速度，由此可避免焊锡膏块203被压碎。
在实施了软熔的接合工序之后，最后如图16所示，使未充满材料502流入倒装片301的电极形成面和配线基板150的部件安装面的空隙，进行未充满处理(未充满工序)。另外，本发明者实际上进行了以上的工序，结果是，软熔工序后的该空隙的高度大致为50～60[μm]，为低于70[μm]的相当小的值。另外，在目前进行的未充满工序之前的清洗工序中未进行。不进行清洗工序的理由已说明。通过以上的工序，制造对PWB150安装了各种电子部件的作为电子电路板的模块基板210。
作为焊锡膏，优选使用不含铅的无Pb的材料，焊锡粒的粒径为10～30[μm]的材料。越是焊锡粒的平均粒径小的焊锡膏，越能够发挥良好的接合性。
在未充满工序中，如图17所示，从倒装片301的四个侧面中电极焊盘301a间的距离L1为500[μm]以上的侧面流入未充满材料502。此时，使沿喷嘴501的倾斜切下的前端的倾斜部与形成于倒装片301和模块基板210的第一面之间的空隙对面，同时使从该倾斜部喷出的含有树脂的未充满材料502与倒装片301和模块基板210两者接触最佳。由此，通过毛细管现象，未充满材料502不会到达间隙的很深各处而遍布。另外，充填的未充满材料502几乎使溶剂蒸发并固化。
就这样制造的作为电子电路板的模块基板210而言，通过利用SMT来表面安装倒装片，从而与通过引线接合将倒装片和基板电极连接的情况相比，能够大幅降低倒装片和基板电极之间的阻抗。例如，引线接合的结构的阻抗为30[mΩ]，与之相对，可将其降到其一半的15[mΩ]程度。而且，由此可得到噪声强且适用于高速处理的模块基板210。
另外，由于将倒装片301的电极焊盘301a和配线基板150的非金电极151接合的焊锡的厚度为70[μm]以下，因此，与100[μm]以上的现有的情况相比，能够实现信号传输速度的高速化，同时能够降低噪声的混入。另外，能够从电极焊盘301a间的距离L1即焊锡间的距离为500[μm]以上的大的开口良好地流入未充满材料502，从而能够容易地进行倒装片301的未充满处理。
也可以将倒装片301的周围用树脂密封而构成封装件。在PWB150上安装有多个倒装片301的壳体上，在密封树脂流入形成有与多个倒装片301分别对应的形成有多个凹部的型材的各凹部内后，使该型材与PWB的第一面接触分离，由此能够同时对多个倒装片进行密封处理。作为密封树脂，可使用丙烯类、环氧类、硅类各种树脂，但特别优选环氧类树脂。
如上那样制造的模块基板210作为例如电子设备即手机的电池保护模块使用。具体来说，在手机的备用锂电池充电时，模块基板210可成为用于防止过电流进入锂电池内的模块。该情况下，如图18所示，安装于第一面上的两个电极组303中的一个焊接在从锂电池400的内部延伸出来的正极用的金属带401上。另外，另一个焊接在从锂电池400的内部延伸出来的正极用金属带402上。由此，先前图7所示的基板第二面上的负极用接点电极形成区域R4上形成的矩形状的Au电极152与锂电池400内的负极导通，起到负极用接点电极的作用。形成于正极用电极形成区域R5的矩形的Au电极152与锂电池400内的正极导通，起到正极用测试电极的作用。另外，形成于负极用电极形成区域R6的圆形的Au电极152与锂电池400内的负极导通，起到负极用测试电极的作用。再有，形成于正极用电极形成区域R7的圆形的Au电极152与锂电池400内的正极导通，起到正极用测试电极的作用。另外，负极用测试电极或正极用测试电极分别在进行锂电池包(リチゥムバッテリ一パック)的检查时使用。
上述的锂电池400或其上具有模块基板210等的锂电池410如图19所示，与手机的手机主体411拆装。在进行该拆装时，负极用接点电极152Y及正极用接点电极152Y在手机主体411的负极电极412或正极电极413上滑动移动，同时与负极电极412或正极电极413连接。
以上对使用实施例的PWB制造使倒装片作为模拟方式的集成电路起作用的电池保护模块的例子进行了说明，但也可以利用同一PWB制造模拟方式的RFID(Radio Frequency Identification)、DC/DC换频器、游戏机等各种电气设备中的电源保护电路等。也可以制造数字方式的RAM模块、CPU模块、图像形成装置中的图像处理模块等。有关这些模拟方式及数字方式的模块，可用于个人电脑的主板、HDD(硬盘驱动器)、汽车导航系统、DVD驱动器、DVD唱机、数码相机、复印机、打印机、IC标签、IC卡、信息处理装置、图像处理装置、控制装置、通信装置等。
另外，对使用了作为绝缘材料的玻璃环氧树脂的PWB作为基板153的例子进行了说明，但本发明也可以应用于使用了由硅(Si)等其他绝缘材料构成的配线基板。在使用由硅构成的基板153时，也可以采用代替铜的铝构成的结构作为各电极的金属母材。该情况下，由Au电极152的铝构成的母材层152a的厚度可为与由铜构成的母材层152a的情况相同的35[μm]程度。另外，镀镍处理得到的中间层152a或电解镀金处理得到的Au表面层152c的厚度也可为与由铜构成的母材层152c的情况相同的数[μm]程度的薄厚。
这样，在本发明的实施例中，在通过导电性物质配线的由绝缘材料构成的基板的表面形成有多个电极的配线基板上，作为上述电极形成有未设置由金构成的Au表面层的Au电极和设有该Au表面层的Au电极两者。
在这些配线基板上，若对未设有Au表面层的非Au电极焊接裸片等小型电子部件，则即使在因例如该小型电子部件的电极焊盘极小而可能使介于电极焊盘和非Au电极之间的焊锡为微量的情况下，也不会产生从非Au电极151向焊锡析出大量的金的事态。因此，可避免电极表面的金向焊锡中大量析出造成的焊锡的脆弱化。
另外，除未设有Au表面层的非Au电极之外，还形成有设置了Au表面层的Au电极，因此，即使将其作为直接出来的接点电极使用，也能够良好地发挥功能。
另外，在上述配线基板中，也可以在上述非Au电极的表面形成由与金不同的材料构成的氧化抑制膜。
通过利用由焊剂等非金属材料构成的氧化抑制膜抑制未设有Au表面层的非Au电极表面的氧化，从而将非Au电极表面长期保持与焊锡良好接合的状态。而且，由此可大量制造配线基板，实现电子电路板的低成本化。
另外，在上述配线基板上，在上述基板的两面分别形成多个电极，将该基板的一侧面形成的全部多个电极设为上述非Au电极，且也可以将该基板的另一侧面上形成的全部多个电极设为上述Au电极。
通过将基板的一侧面的全部多个电极作为非Au电极形成，且将另一侧面的全部多个电极作为Au电极形成，从而与相对于同一面混合形成非Au电极及Au电极这种种类相互不同的电极的情况相比，简化了电极形成工序。而且，由此可降低制造成本。
再有，在上述配线基板上，多个上述非Au电极的全部或其一部分的平面面积为0.049[mm2]以下，且全部多个上述Au电极的平面面积为0.049[mm2]以上。
通过将多个非Au电极的至少一部分的平面面积设为0.049[mm2]以下，可将该非Au电极作为小型倒装片的安装用使用。而且，由此即使为正在小型化的近年来的小型裸片，也可以将其作为倒装片表面安装于基板的一侧面上。另外，通过将整个Au电极的平面面积设为0.049[mm2]以上，能够通过Au表面层抑制基板的另一侧面形成的全部电极的氧化。
再有，在通过导电性物质配线的由绝缘材料构成的基板的表面形成有多个电极的配线基板上将具有用于与该电极接合的接合用电极的多个电子部件进行表面安装的电子电路板中，可以使用上述的配线基板作为配线基板。
上述电子电路板即多个上述电子部件中的至少之一作为上述接合用电极，具有设有由金构成的Au表面层的结构，该Au表面层具有面积比其侧面大的平坦接合面，该接合面也可以与上述配线基板的上述非Au电极焊接。
另外，在通过导电性物质配线的由绝缘材料构成的基板的表面形成有多个电极的配线基板上将具有用于与该电极接合的接合用电极的多个电子部件进行表面安装的电子电路板，即上述配线基板作为上述电极具有未设有由金构成的Au表面层的非Au电极和设有该Au表面层的Au电极两者，多个上述电子部件中的至少之一作为上述接合用电极，具有设有由金构成的Au表面层的Au电极，该Au电极的该Au表面层具有面积比其侧面大的平坦的接合面，且该接合面也可以与上述配线基板的上述非Au电极焊接。
不仅能够避免配线基板电极表面的金大量析出到焊锡中造成的焊锡脆弱化，通过下面说明的理由，还能够抑制电子部件的接合用电极的金析出到焊锡中造成的焊锡的脆弱化。即，在现有的倒装片中，为防止用于与配线基板的电极接合的接合用电极的氧化造成的接合不良，而通常在接合用电极表面形成由金构成的金补片。图21表示这种现有的补片的放大剖面图。同图中，在倒装片301的表面形成有多个接合用电极301d。这些接合用电极301d在由镍及铝等非Au金属材料构成的平坦的金属母材焊盘301e的表面覆盖有金补片301f。该金补片301f是通过用于上述旧式的COB法的引线接合装置而突设，使得金材料在平坦的金属母材焊盘301e的表面上形成线状突起的补片。在将这种补片301进行表面安装时，首先如图22所示，在作为配线基板的PWB150的非Au电极151上印刷焊锡膏块203。然后，如图23所示，以将该焊锡膏块203和接合用电极301d接合的方式将倒装片301装配到PWB150上。于是，如图24所示，构成在膏状焊锡膏块203中插入接合用电极301d的金补片301f的状态。当在这样的状态下施行软熔工序时，插入焊锡膏块203中的金补片301f的金大量析出到熔融焊锡中，使固化后的焊锡脆弱。因此，作为倒装片301等电子部件，不使用在接合用电极的表面设置金补片这样的金突起，而使用Au表面层的面积比其侧面大的平坦的接合面的结构。在这种电子部件中，如图21所示，在由非金材料构成的平坦的金属母材焊盘301b的表面形成的由金构成的平坦的Au表面层301c进入到焊锡膏块203中，成为只与焊锡膏块203的表面接触的状态。即使在这种状态下进行软熔工序，从Au表面层301c向熔融焊锡的金析出也只是在膏块203的表面部分产生，因此，与设有金补片301f的电子部件相比，金向熔融焊锡中的析出量降低。由此，能够抑制电子部件的接合用电极的金析出到焊锡中造成的焊锡脆弱化。
另外，多个上述电子部件中，上述接合用电极的平面面积最小的电子部件中的电极形成面和上述配线基板的部件安装面的距离也可以为70[μm]以下。
电子电路基板的多个电子部件中，接合用电极的平面面积最小的电子部件、即实现小型化的倒装片这样的信号传输速度的高速化及噪声混入的降低化的电子部件，以极少的量通过薄度厚的导电性接合材料与配线基板接合。该电极形成面和配线基板的部件安装面的距离为软熔后的70[μm]以下这样的量和厚度，与100[μm]以上的现有的情况相比，为非常少的量且薄度厚。由于这样极少量且薄度厚的导电性接合材料的电阻比目前小，因此，能够实现信号传输速度的高速化，同时能够降低噪声的混入。
作为上述接合用电极的平面面积最小的电子部件，使用上述电极形成面的周缘部的局部区域的该接合用电极间的距离为500[μm]以上的部件，且也可以在该电极形成面和上述部件安装面之间施行未充满处理。
通过在小型电子部件的电极形成面和配线基板的部件安装面之间产生的间隙充填未充满材料，避免电子部件和配线基板的热膨胀系数不同而造成的向电子部件的间隙的挠曲。而且可防止该挠曲造成的固化后的导电性接合材料的破断。另外，即使电子部件的电极形成面和配线基板的部件安装面的空隙为70[μm]以下这样非常小的部件，也可以在电子部件周缘部的局部区域形成基板面方向的长度为500[μm]以上的大小的开口。因此，未充满材料从该大的开口良好地流入，从而能够容易地进行小型电子部件的未充满处理。
上述电子电路板即多个上述电子部件中的至少之一也可以是在使集成电路形成面朝向上述配线基板吻合的状态下安装的倒装片。
另外，在本发明实施例中，在具有由导电性物质进行配线的由绝缘材料构成的基板的表面形成有多个电极的配线基板上将具有用于与该电极接合的接合用电极的多个电子部件进行表面安装的电子电路板、和覆盖该电路板的框体的电子设备中，使用上述配线基板作为该配线基板。
另外，在本实施例中，在通过实施在由导电性物质配线的由绝缘材料构成的基板表面形成有多个电极的配线基板的该电极上印刷由含有导电性接合材料的膏构成的膏块的印刷工序、经由该膏块在该配线基板上载置多个电子部件的载置工序、为将该膏块中的该导电性接合材料熔融，与该电极接合而将设于各多个电子部件上的接合用电极和该配线基板的该电极接合的接合工序，由此制造将多个电子部件表面安装于该配线基板上的电子电路板的电子电路板制造方法中，使用上述配线基板作为该配线基板。
另外，在上述电子电路板制造方法中，也可以通过上述印刷工序将多个上述电子部件中上述接合用电极的平面面积最小的电子部件的电极形成面和上述配线基板的部件安装面的距离在实施上述接合工序后为70[μm]以下的厚度的上述膏块印刷在上述配线基板的上述电极上。
还有，在上述电子电路板制造方法中，使用上述电极形成面的周缘部的局部区域的该接合用电极间的距离为500[μm]以上的部件作为上述接合用电极的平面面积最小的电子部件，在进行了上述接合工序后，也可以实施使未充满材料从该局部区域和上述部件安装面之间流入该电极形成面之下的未充满工序。
再有，在上述电子电路板制造方法中，不清洗上述部件安装面的上述电极形成面的对向区域，也可以实施上述未充满工序。
由于省去了目前进行的与部件安装面的电极形成面对向的区域的清洗工序，从而能够降低电子电路板的制造成本。另外，虽然目前不能省去这样的清洗工序进行未充满处理，但在本发明中可通过下面说明的理由省去清洗工序。即，目前由于介于电子部件的电极形成面和配线基板的部件安装面之间的膏块的量大，故在进行软熔时大量的焊剂从该膏块中向部件安装面飞散。而且，在未充满处理时，附着在部件安装面上的大量的焊剂弹在未充满材料上，阻碍其流入。另一方面，在本发明中，由于介于电子部件的电极形成面和配线基板的部件安装面之间的膏块量非常少，故软熔时飞散到部件安装面的焊剂的量也为少量。因此，即使不实施清洗焊剂的清洗工序，也可以使未充满材料流入。
以上说明了本发明优选的实施例，但本发明不限于此，在本发明主旨的范围内可进行各种变形及变更。
产业上的可利用性
本发明适用于例如在用于安装IC芯片及片状电容等电子部件的由绝缘材料构成的基板表面形成有多个电极的印刷线路板等配线基板。

Claims (16)

1、一种配线基板，在通过导电性物质进行了配线的由绝缘材料构成的基板表面形成有多个电极，其特征在于，作为所述电极，形成有未设置由金构成的Au表面层的非Au电极和设有该Au表面层的Au电极两者。
2、如权利要求1所述的配线基板，其特征在于，在所述非Au电极表面形成有由与金不同的材料构成的氧化抑制膜。
3、如权利要求1或2所述的配线基板，其特征在于，在所述基板的两面分别形成多个电极，将该基板的一面形成的全部多个电极设为所述非Au电极，且将该基板的另一面形成的全部多个电极设为所述Au电极。
4、如权利要求3所述的配线基板，其特征在于，全部多个所述非Au电极或其一部分的平面面积为0.049[mm2]以下，且全部多个上述Au电极的平面面积为0.049[mm2]以上。
5、一种电子电路板，在通过导电性物质进行了配线的由绝缘材料构成的基板表面上形成有多个电极的配线基板上，将具有用于与该电极接合的接合用电极的多个电子部件进行表面安装，其特征在于，使用权利要求1～4中任一项所述的配线基板作为所述配线基板。
6、如权利要求5所述的电子电路板，其特征在于，多个所述电子部件中的至少之一作为所述接合用电极具有设有由金构成的Au表面层的Au电极，该Au表面层具有面积比其侧面大的平坦的接合面，该接合面与所述配线基板的所述非Au电极焊接。
7、一种电子电路板，在通过导电性物质进行了配线的由绝缘材料构成的基板表面上形成有多个电极的配线基板上，将具有用于与该电极接合的接合用电极的多个电子部件进行表面安装，其特征在于，所述配线基板具有作为所述电极的未设置由金构成的Au表面层的非Au电极和设有该Au表面层的Au电极两者，多个所述电子部件中的至少之一作为所述接合用电极具有设有由金构成的Au表面层的结构，该Au电极的该Au表面层具有面积比其侧面大的平坦的接合面，且该接合面与上述配线基板的上述非Au电极进行焊接。
8、如权利要求5、6或7所述的电子电路板，其特征在于，多个所述电子部件中，所述接合用电极的平面面积最小的电子部件的电极形成面和所述配线基板的部件安装面的距离为70[μm]以下。
9、如权利要求8所述的电子电路板，其特征在于，作为所述接合用电极的平面面积最小的电子部件，使用所述电极形成面周缘部的局部区域的该接合用电极间的距离为500[μm]以上的部件，在该电极形成面和所述部件安装面之间实施未充满处理。
10、如权利要求5～9中任一项所述的电子电路板，其特征在于，多个所述电子部件中的至少之一是以使集成电路形成面朝向所述配线基板吻合的状态安装的倒装片。
11、一种电子设备，其具有电子电路板和覆盖该电路板的框体，其中，电子电路板在通过导电性物质进行了配线的由绝缘材料构成的基板表面形成有多个电极的配线基板上，将具有用于与该电极接合的接合用电极的多个电子部件进行表面安装，其特征在于，使用权利要求1～4中任一项所述的配线基板作为该配线基板。
12、一种电子设备，其具有电子电路板和覆盖该电路板的框体，其中，电子电路板在通过导电性物质进行了配线的由绝缘材料构成的基板表面形成有多个电极的配线基板上，将具有用于与该电极接合的接合用电极的多个电子部件进行表面安装，其特征在于，使用权利要求5～10中任一项所述的配线基板作为该配线基板。
13、一种电子电路板制造方法，其通过实施在由导电性物质配线的由绝缘材料构成的基板表面形成有多个电极的配线基板的该电极上，印刷由含有导电性接合材料的膏构成的膏块的印刷工序、经由该膏块在该配线基板上载置多个电子部件的载置工序、为将该膏块中的该导电性接合材料熔融与该电极接合而将设于各多个电子部件上的接合用电极和该配线基板的该电极接合的接合工序，由此制造将多个电子部件表面安装于该配线基板上的电子电路板，其特征在于，使用权利要求1～4的配线基板作为所述配线基板。
14、如权利要求13所述的电子电路板制造方法，其特征在于，通过所述印刷工序将在实施所述接合工序后多个所述电子部件中所述接合用电极的平面面积最小的电子部件的电极形成面和所述配线基板的部件安装面的距离为70[μm]以下的厚度的所述膏块印刷在所述配线基板的所述电极上。
15、如权利要求14所述的电子电路板制造方法，其特征在于，作为所述接合用电极的平面面积最小的电子部件，使用所述电极形成面周缘部的局部区域的该接合用电极间的距离为500[μm]以上的部件，在进行所述接合工序后，实施使未充满材料从该局部区域和所述部件安装面之间流入该电极形成面之下的未充满工序。
16、如权利要求15所述的电子电路板制造方法，其特征在于，不对与所述部件安装面的所述电极形成面对向的区域进行清洗，而实施所述未充满工序。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646606A (zh) * 2011-02-16 2012-08-22 中电智能卡有限责任公司 Ic卡模块的封装方法
CN104134649A (zh) * 2013-05-02 2014-11-05 瑞萨电子株式会社 电子装置
CN104308314A (zh) * 2014-10-11 2015-01-28 昆山圆裕电子科技有限公司 Dip通孔零件的回流焊接工艺

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100874588B1 (ko) * 2007-09-05 2008-12-16 성균관대학교산학협력단 전기적 특성 평가가 가능한 플립칩 및 이것의 제조 방법
USRE48422E1 (en) * 2007-09-05 2021-02-02 Research & Business Foundation Sungkyunkwan Univ. Method of making flip chip
US9425157B2 (en) 2014-02-26 2016-08-23 Taiwan Semiconductor Manufacturing Company Limited Substrate and package structure
JP6889399B2 (ja) * 2017-08-08 2021-06-18 大日本印刷株式会社 貫通電極基板

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3394527A (en) * 1967-07-24 1968-07-30 American Cyanamid Co Reinforcing anisotropic non-homogeneous engineering structures
JPS58192351A (ja) 1982-05-06 1983-11-09 Sharp Corp 半導体装置の製造方法
JPH02296336A (ja) 1989-05-10 1990-12-06 Seiko Epson Corp 半導体回路バンプの製造方法
JPH05167236A (ja) * 1991-12-19 1993-07-02 Sumitomo Bakelite Co Ltd 回路等への半田付け方法
JPH07193166A (ja) * 1993-11-19 1995-07-28 Citizen Watch Co Ltd 半田バンプ付き半導体装置及びその製造方法
FI940953A (fi) * 1994-02-28 1995-08-29 Neste Oy Polymeerikalvot ja menetelmä niiden valmistamiseksi
US6524644B1 (en) * 1999-08-26 2003-02-25 Enthone Inc. Process for selective deposition of OSP coating on copper, excluding deposition on gold
US6534192B1 (en) * 1999-09-24 2003-03-18 Lucent Technologies Inc. Multi-purpose finish for printed wiring boards and method of manufacture of such boards
JP3952434B2 (ja) * 2000-03-29 2007-08-01 ローム株式会社 電池パックおよびその製造方法
DE10018025A1 (de) * 2000-04-04 2001-10-18 Atotech Deutschland Gmbh Verfahren zum Erzeugen von lötfähigen Oberflächen und funktionellen Oberflächen auf Schaltungsträgern
JP3855592B2 (ja) 2000-04-19 2006-12-13 松下電器産業株式会社 小型モジュールの製造方法
JP3477656B2 (ja) * 2000-06-21 2003-12-10 三洋ジ−エスソフトエナジー株式会社 電池の外部端子とそれを用いた電池パック
TW511257B (en) * 2000-12-11 2002-11-21 Chino Excel Technology Corp Flip-chip mounting method for decreasing conducting resistance in power transistor of charging battery protection circuit
US6494361B1 (en) * 2001-01-26 2002-12-17 Amkor Technology, Inc. Semiconductor module package substrate fabrication method
US6515744B2 (en) * 2001-02-08 2003-02-04 Therma-Wave, Inc. Small spot ellipsometer
JP3792129B2 (ja) * 2001-03-01 2006-07-05 新光電気工業株式会社 キャパシタ、キャパシタ内蔵回路基板及びそれらの製造方法
US6744135B2 (en) * 2001-05-22 2004-06-01 Hitachi, Ltd. Electronic apparatus
JP2002368038A (ja) * 2001-06-07 2002-12-20 Fuji Electric Co Ltd フリップチップ実装方法
JP3866591B2 (ja) * 2001-10-29 2007-01-10 富士通株式会社 電極間接続構造体の形成方法および電極間接続構造体
US7130198B2 (en) * 2001-12-06 2006-10-31 Rohm Co., Ltd. Resin-packaged protection circuit module for rechargeable batteries and method of making the same
JP3872995B2 (ja) 2002-03-20 2007-01-24 Ｔｄｋ株式会社 ベアチップ実装方法
JP2003318308A (ja) * 2002-04-18 2003-11-07 Nippon Mektron Ltd 可撓性回路基板のフリップチップｉｃ接続用回路パターン
JP2004165637A (ja) * 2002-10-21 2004-06-10 Matsushita Electric Ind Co Ltd 半導体装置
JP2004171964A (ja) * 2002-11-20 2004-06-17 Sony Corp 回路基板、電池の接続方法、並びに電源装置
TWI263704B (en) * 2003-03-18 2006-10-11 Ngk Spark Plug Co Wiring board
US7141874B2 (en) * 2003-05-14 2006-11-28 Matsushita Electric Industrial Co., Ltd. Electronic component packaging structure and method for producing the same
JP4033811B2 (ja) 2003-06-19 2008-01-16 株式会社リコー フリップチップ実装体
US7186645B2 (en) * 2003-10-13 2007-03-06 Intel Corporation Selective plating of package terminals
EP1635459B1 (en) * 2004-01-19 2017-10-25 Murata Manufacturing Co., Ltd. Acoustic boundary wave device
JP4736451B2 (ja) * 2005-02-03 2011-07-27 パナソニック株式会社 多層配線基板とその製造方法、および多層配線基板を用いた半導体パッケージと電子機器

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646606A (zh) * 2011-02-16 2012-08-22 中电智能卡有限责任公司 Ic卡模块的封装方法
CN102646606B (zh) * 2011-02-16 2014-12-24 中电智能卡有限责任公司 Ic卡模块的封装方法
CN104134649A (zh) * 2013-05-02 2014-11-05 瑞萨电子株式会社 电子装置
CN104308314A (zh) * 2014-10-11 2015-01-28 昆山圆裕电子科技有限公司 Dip通孔零件的回流焊接工艺

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