CN100541738C - 用于形成具有硅化物层的半导体器件的方法 - Google Patents

用于形成具有硅化物层的半导体器件的方法 Download PDF

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Publication number
CN100541738C
CN100541738C CNB2005800171377A CN200580017137A CN100541738C CN 100541738 C CN100541738 C CN 100541738C CN B2005800171377 A CNB2005800171377 A CN B2005800171377A CN 200580017137 A CN200580017137 A CN 200580017137A CN 100541738 C CN100541738 C CN 100541738C
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CN
China
Prior art keywords
layer
metal silicide
metal
silicide layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005800171377A
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English (en)
Chinese (zh)
Other versions
CN1961411A (zh
Inventor
达尔迈什·贾瓦拉尼
塔伯·A·斯蒂芬斯
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1961411A publication Critical patent/CN1961411A/zh
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Publication of CN100541738C publication Critical patent/CN100541738C/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30—Diffusion for doping of conductive or resistive layers
    • H10P32/302—Doping polycrystalline silicon or amorphous silicon layers

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CNB2005800171377A 2004-05-26 2005-04-26 用于形成具有硅化物层的半导体器件的方法 Expired - Fee Related CN100541738C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/854,389 US7235471B2 (en) 2004-05-26 2004-05-26 Method for forming a semiconductor device having a silicide layer
US10/854,389 2004-05-26

Publications (2)

Publication Number Publication Date
CN1961411A CN1961411A (zh) 2007-05-09
CN100541738C true CN100541738C (zh) 2009-09-16

Family

ID=35461084

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005800171377A Expired - Fee Related CN100541738C (zh) 2004-05-26 2005-04-26 用于形成具有硅化物层的半导体器件的方法

Country Status (5)

Country Link
US (1) US7235471B2 (https=)
JP (1) JP5103174B2 (https=)
CN (1) CN100541738C (https=)
TW (1) TWI391993B (https=)
WO (1) WO2005119752A1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100587686B1 (ko) * 2004-07-15 2006-06-08 삼성전자주식회사 질화 티타늄막 형성방법 및 이를 이용한 커패시터 제조방법
US7538026B1 (en) * 2005-04-04 2009-05-26 Advanced Micro Devices, Inc. Multilayer low reflectivity hard mask and process therefor
JP2007048893A (ja) * 2005-08-09 2007-02-22 Fujifilm Corp 固体撮像素子およびその製造方法
JP2010003742A (ja) * 2008-06-18 2010-01-07 Fujitsu Microelectronics Ltd 半導体装置、及び薄膜キャパシタの製造方法
KR101037495B1 (ko) * 2008-07-31 2011-05-26 주식회사 하이닉스반도체 고집적 반도체 장치의 제조 방법 및 반도체 장치
US8158254B2 (en) * 2008-08-25 2012-04-17 The Trustees Of Boston College Methods of fabricating complex two-dimensional conductive silicides
US8216436B2 (en) * 2008-08-25 2012-07-10 The Trustees Of Boston College Hetero-nanostructures for solar energy conversions and methods of fabricating same
US20170170016A1 (en) * 2015-12-14 2017-06-15 Globalfoundries Inc. Multiple patterning method for substrate
US11424338B2 (en) 2020-03-31 2022-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Metal source/drain features

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1335648A (zh) * 2000-07-22 2002-02-13 三星电子株式会社 用于降低源漏极间电阻的mos场效应管及其制造方法
US6657244B1 (en) * 2002-06-28 2003-12-02 International Business Machines Corporation Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation
CN1490853A (zh) * 2002-10-16 2004-04-21 上海宏力半导体制造有限公司 可改善接面电性特性的自行对准金属硅化物的制造方法
WO2004038807A1 (en) * 2002-09-30 2004-05-06 Advanced Micro Devices, Inc. Mosfets incorporating nickel germanosilicided gate and methods of their formation

Family Cites Families (15)

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Publication number Priority date Publication date Assignee Title
JPS6266679A (ja) * 1985-09-19 1987-03-26 Fujitsu Ltd 半導体装置の製造方法
JPS63306665A (ja) * 1987-06-08 1988-12-14 Nippon Telegr & Teleph Corp <Ntt> 絶縁ゲ−ト型電界効果トランジスタおよびその製造方法
JPH088317B2 (ja) * 1990-04-24 1996-01-29 株式会社東芝 半導体記憶装置及びその製造方法
JP3770954B2 (ja) * 1995-11-13 2006-04-26 エイ・ティ・アンド・ティ・コーポレーション 装置の製造方法
US6156632A (en) * 1997-08-15 2000-12-05 Micron Technology, Inc. Method of forming polycide structures
JP4538693B2 (ja) * 1998-01-26 2010-09-08 ソニー株式会社 メモリ素子およびその製造方法
US6107211A (en) * 1999-04-26 2000-08-22 Vanguard International Semiconductor Corporation Split polysilicon process in CMOS image integrated circuit
US20020132478A1 (en) * 1999-06-29 2002-09-19 Tinghao Frank Wang Method for selectively etching silicon and/or metal silicides
US6391767B1 (en) * 2000-02-11 2002-05-21 Advanced Micro Devices, Inc. Dual silicide process to reduce gate resistance
US6306698B1 (en) * 2000-04-25 2001-10-23 Advanced Micro Devices, Inc. Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same
JP3676276B2 (ja) * 2000-10-02 2005-07-27 松下電器産業株式会社 半導体装置及びその製造方法
JP2003077900A (ja) * 2001-09-06 2003-03-14 Hitachi Ltd 半導体装置の製造方法
US7449385B2 (en) * 2002-07-26 2008-11-11 Texas Instruments Incorporated Gate dielectric and method
US6867130B1 (en) * 2003-05-28 2005-03-15 Advanced Micro Devices, Inc. Enhanced silicidation of polysilicon gate electrodes
US20040238876A1 (en) * 2003-05-29 2004-12-02 Sunpil Youn Semiconductor structure having low resistance and method of manufacturing same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1335648A (zh) * 2000-07-22 2002-02-13 三星电子株式会社 用于降低源漏极间电阻的mos场效应管及其制造方法
US6657244B1 (en) * 2002-06-28 2003-12-02 International Business Machines Corporation Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation
WO2004038807A1 (en) * 2002-09-30 2004-05-06 Advanced Micro Devices, Inc. Mosfets incorporating nickel germanosilicided gate and methods of their formation
CN1490853A (zh) * 2002-10-16 2004-04-21 上海宏力半导体制造有限公司 可改善接面电性特性的自行对准金属硅化物的制造方法

Also Published As

Publication number Publication date
TW200618067A (en) 2006-06-01
WO2005119752A1 (en) 2005-12-15
US20050277275A1 (en) 2005-12-15
TWI391993B (zh) 2013-04-01
CN1961411A (zh) 2007-05-09
JP2008500728A (ja) 2008-01-10
JP5103174B2 (ja) 2012-12-19
US7235471B2 (en) 2007-06-26

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Address after: Texas in the United States

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Patentee before: Fisical Semiconductor Inc.

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Granted publication date: 20090916

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CF01 Termination of patent right due to non-payment of annual fee