CN100511650C - 制造非易失性存储器件的方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
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- 238000000137 annealing Methods 0.000 claims abstract description 27
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- 241001269238 Data Species 0.000 description 1
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- 239000012299 nitrogen atmosphere Substances 0.000 description 1
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Abstract
一种制造非易失性存储器件的方法包括以下步骤:形成栅极,所述栅极各自具有其中在半导体衬底上沉积栅极绝缘层、第一导电层、介电层、第二导电层和金属硅化物层的结构,在与所述介电层的退火温度相同或低于所述介电层的退火温度的温度下退火所述金属硅化物层;在整个表面上形成缓冲氧化物层,和在所述缓冲氧化物层上形成氮化物层。
Description
本发明要求2006年5月26日提交的韩国专利申请10-2006-47684和2006年12月20日提交的韩国专利申请10-2006-131118的优先权,这些韩国专利申请经引用整体并入本文。
技术领域
本发明涉及一种制造非易失性存储器件的方法。
背景技术
一般来说,随着快闪存储器件尺寸减小,非易失性存储器件的编程干扰特性变得与其他过程关系密切。编程干扰现象的最可能的原因在于由于过程中的热应力而产生的衬底上的失效。通过在采用自对准接触(SAC)的NAND快闪存储器制造工艺的后续热处理过程中较高温度下的修复可以改善差错。
然而,如果使用传统方法而没有变化,随着器件的小型化可能发生编程干扰问题。
发明内容
因此,本发明解决上述问题,并且提供了一种制造非易失性存储器件的方法,其中,通过在形成非易失性存储器件时给出用于形成产生物理应力的SAC过程中所用的氮化物层的条件,并优化硅化钨层(即栅极工艺的核)的热处理过程,可以抑制在半导体衬底中发生的差错并改善编程干扰特性。
根据本发明的一个方面,一种制造非易失性存储器件的方法包括以下步骤:形成栅极,所述栅极分别具有其中在半导体衬底上层叠栅极绝缘层、第一导电层、介电层、第二导电层和金属硅化物层的结构;在与介电层的退火温度相同或低于介电层退火温度的温度下退火金属硅化物层;在整个表面上形成缓冲氧化物层,以及在缓冲氧化物层上形成氮化物层。
附图说明
图1A至1E是说明根据本发明的一个实施方案的制造非易失性存储器件的方法的截面图。
图2是说明图1B中所示的硅化钨层的退火过程的图。
图3是说明基于元件形成步骤的应力的图。
图4是说明图1D中所示的SAC氮化物层的形成过程的图。
图5是说明取决于SAC氮化物层的沉积方法的失效位的图。
具体实施方式
现参考附图描述根据本发明的具体实施方案。
图1A至1E是说明根据本发明的一个实施方案的制造非易失性存储器件的方法的截面图。
参见图1A,栅极200和300形成在半导体衬底100上。栅极200和300包括用于外围电路(未示出)的高压和低压的栅极,以及用于单元的栅极200,用于选择晶体管的栅极300。
在栅极200和300形成之前,进行阱形成过程、沟槽型分隔结构形成过程等。分隔结构可以通过浅沟槽分隔(STI)方案或SA-STI方案形成。
栅极200的每一个包括栅极绝缘层101、第一导电层102、介电层103、第二导电层104、金属硅化物层105和栅极硬掩模层106,所有这些层层叠在半导体衬底100上。
在用于单元的栅极200中,第一导电层102作为浮置栅极,第二导电层104和金属硅化物层105作为控制栅极。在用于选择晶体管的栅极300中,第一导电层103、第二导电层104和金属硅化物层105连接并作为各栅极。
介电层103具有氧化物-氮化物-氧化物(ONO)结构。为了改善介电层103的薄膜质量,介电层103可以在800-850摄氏度的温度范围内退火。金属硅化物层105可以由硅化钨层形成。
参见图1B,为了解决由于栅极的高电阻产生的字线负载(word lineloading)问题,进行金属硅化物层105的退火。金属硅化物层105的退火过程可以在与ONO介电层103的退火温度相同或者低于ONO介电层的退火温度的温度下进行。原因在后面参考图3进行描述。下面参考图2描述当金属硅化物层105是硅化钨层时的退火过程。
图2是说明图1B所示的硅化钨层的退火过程的图。
硅化钨层105的退火过程在N2气氛下进行,并且包括装载步骤A、升温步骤B、退火保温步骤C、降温步骤D和卸载步骤E。
装载步骤A在750摄氏度的温度下进行25分钟。升温步骤B在将温度从750摄氏度升高到800摄氏度的同时进行10分钟。退火保温步骤C是保持主退火温度的步骤,其在800摄氏度的温度下进行18.5分钟。降温步骤D在将温度从800摄氏度降低到750摄氏度的同时进行17分钟,同时。卸载步骤E在750摄氏度进行30分钟。
应当注意,在硅化钨层的退火过程中所用的温度和时间仅仅是举例说明性的实验数据。因此,本发明不限于在上述实验数据中设定的上述温度和时间,而是可以包括各种不同的温度和时间。
图3是说明基于元件形成步骤的应力的图。一般来说,ONO介电层103的退火温度范围为800至850摄氏度。如果硅化钨层105的退火温度高于850摄氏度,在沟槽型分隔结构的顶角处应力增大。然而,如果在本发明给出的条件下进行退火过程,则应力保持非常稳定的值,如图3所示。
参见图1C,在金属硅化物层105退火后,在半导体衬底100上形成杂质离子注入区107、栅极隔离物绝缘层108和SAC缓冲氧化物层109。
通过在650至700摄氏度的温度范围内的沉积过程可以形成SAC缓冲氧化物层109。
参见图1D,在SAC缓冲氧化物层109上形成SAC氮化物层110。通过等离子体增强化学气相沉积(PE-CVD)法或低压CVD(LP-CVD)法可以形成SAC氮化物层110。但是,当SAC氮化物层110通过LP-CVD法形成时的应力大于当SAC氮化物层110通过PE-CVD法形成时的应力。因此,当SAC氮化物层110通过LP-CVD法形成时的失效位的数量比在SAC氮化物层110通过PE-CVD法形成时高三倍。这将在后面参考附图5进行描述。下面参考图4描述SAC氮化物层110的形成工艺。
图4是说明图1D所示的SAC氮化物层110的形成工艺的图。
SAC氮化物层110通过PE-CVD法形成,并且包括装载步骤F、升温步骤G、沉积步骤H、降温步骤I和卸载步骤J。
装载步骤F在N2气氛下保持在大气压下,并且在400摄氏度的温度下进行70分钟。
在升温步骤G中,在N2气氛下保持压力为5Torr,并且温度每分钟升高5摄氏度,并在66分钟内升高到730摄氏度。
沉积步骤H在N2、NH3和DCS(SiH2Cl2)混合的气氛下保持在0.35Torr,并在730摄氏度的温度下进行57分钟。
在降温步骤I中,在N2气氛下将压力保持在0.35Torr,温度每分钟降低3摄氏度,并降低到400摄氏度。
卸载步骤J在400摄氏度的温度下进行120分钟,同时在N2气氛下缓慢升高压力使其变成大气压。
应当注意,在SAC氮化物层110的形成过程中所用的温度、时间和压力仅是举例说明性的实验数据。因此,本发明不限于在所述实验数据中设定的上述温度、时间和压力,而是包括各种不同的温度、时间和压力。
图5是说明失效位随SAC氮化物层110的沉积方法变化的图。
在图5中,A和B表示当SAC氮化物层110通过LP-CVD法形成时的失效位数量,C、D和E表示当SAC氮化物层通过PE-CVD法形成时的失效位数量。可以看出,当SAC氮化物层110通过PE-CVD法形成时的失效位数量小于当SAC氮化物层110通过LP-CVD法形成时的失效位数量。因此,在本发明中,SAC氮化物层110通过PE-CVD法形成。
此外,图E表示参考图4描述的SAC氮化物层110的形成工艺条件。可以看出,在曲线E中的失效位数量比在曲线A、B、C和D中小。
参见图1E,为了抛光表面,在SAC氮化物层110上形成绝缘层111。通过SAC法形成接触孔112,通过该接触孔112暴露杂质离子注入区107。
如上所述,根据本发明,给出了在SAC过程中所用的形成氮化物层的条件,在形成非易失性存储器件时,该过程产生物理应力,并且优化了硅化钨层(即栅极过程的核)的热处理过程。因此,可以抑制半导体衬底中产生的差错并且可以改善编程干扰特性。
尽管参考各种实施方案进行了以上描述,应当理解,本领域技术人员可以进行本发明的变化和改进而不脱离本发明及所附权利要求的实质和范围。
Claims (11)
1.一种制造非易失性存储器件的方法,其包括以下步骤:
形成栅极,所述栅极各自具有其中在半导体衬底上层叠栅极绝缘层、第一导电层、介电层、第二导电层和金属硅化物层的结构;
在与所述介电层的退火温度相同或低于所述介电层的退火温度的温度下退火所述金属硅化物层;
在整个表面上形成缓冲氧化物层;和
在所述缓冲氧化物层上形成氮化物层。
2.权利要求1的方法,其中所述介电层具有氧化物层、氮化物层和氧化物层的ONO层叠结构,并且在800至850摄氏度的温度范围内退火。
3.权利要求1的方法,其中所述金属硅化物层的退火温度在750至800摄氏度范围内。
4.权利要求1的方法,其中所述金属硅化物层包括硅化钨层。
5.权利要求4的方法,其中所述硅化钨层的退火过程包括:
在750摄氏度进行的装载步骤,
温度从750摄氏度升高到800摄氏度的升温步骤,
在800摄氏度进行的退火保温步骤,
温度从800摄氏度降低到750摄氏度的降温步骤,
在750摄氏度进行的卸载步骤。
6.权利要求5的方法,其中所述硅化钨层的退火过程在N2气氛下进行。
7.权利要求1的方法,其在所述金属硅化物层的退火过程以后还包括以下步骤:
在半导体衬底中形成杂质离子注入区;和
形成栅极隔离绝缘层。
8.权利要求1的方法,其中所述氮化物层通过等离子体增强化学气相沉积法形成。
9.权利要求1的方法,其中所述氮化物层在400至730摄氏度的温度范围内形成。
10.权利要求1的方法,其中形成所述氮化物的步骤包括:
在N2气氛下,压力保持在大气压,在400摄氏度的温度下进行的装载步骤,
在N2气氛下,压力保持在5Torr,将温度升高到730摄氏度的升温步骤,
在N2、NH3和SiH2Cl2的混合气氛下,压力保持在0.35Torr,在730摄氏度的温度下进行的沉积步骤,
在N2气氛下,压力保持在0.35Torr,将温度降低到400摄氏度的降温步骤,和
在N2气氛下,在将压力缓慢升高到大气压的同时在400摄氏度的温度下进行的卸载步骤。
11.权利要求10的方法,其中:
在所述升温步骤中,所述温度每分钟升高5摄氏度,和
在所述降温步骤中,所述温度每分钟降低3摄氏度。
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