CN100490062C - 半导体装置的制造方法 - Google Patents
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Abstract
本发明涉及一种具有半导体电阻层的半导体装置的制造方法,其能够降低理论电阻值与实测电阻值间的偏差。在半导体基板(1)的整个面上形成层间绝缘膜(9),之后有选择地蚀刻该层间绝缘膜(9),形成分别使多晶硅电阻层(4)、源极区域(7)及漏极区域(8)局部露出的接触孔(10、11)。在多晶硅电阻层(4)上,将相邻的接触孔间距定义为电阻元件的长L1、L2,进而设定多晶硅电阻层(4)的构图尺寸。接着,经由接触孔(10)进行离子注入,在多晶硅电阻层(4)上形成低电阻区域(15a~15c)(高浓度杂质注入区域)。接着,以比形成源极区域、漏极区域时的热处理温度更低的温度进行该离子注入后的热处理(退火)。
Description
技术领域
本发明涉及半导体装置的制造方法,特别涉及具有电阻元件的半导体装置。
背景技术
以往,作为用于构成搭载模拟电路的LSI电路的电阻元件,众所周知有由多晶硅层构成的电阻值比较高的元件(以下称为多晶硅电阻层)。该多晶硅电阻层若形成于元件分离区域,则能够将元件形成区域的面积缩小而实现高集成化,且也能够降低寄生电容,因而得到广泛应用。
另外,在一般的LSI电路中,除多晶硅电阻层以外,像MOS晶体管或双极晶体管等那样的有源元件也形成在同一的半导体基板上。下面,参照图6至图8,对在同一半导体基板上具有多晶硅电阻层及MOS晶体管的现有的半导体装置的制造工序的一例,进行说明。
如图6所示,通过LOCOS法等在半导体基板100上形成用于元件分离的场绝缘膜101。另外,通过热氧化法等在场绝缘膜101包围的区域的半导体基板100的表面上,形成MOS晶体管用的栅极绝缘膜102。接着,在半导体基板100的整个面上形成多晶硅层,进行使电阻元件具有所希望的电阻值的离子注入,之后,通过干蚀刻等进行构图,而在场绝缘膜101上形成多晶硅电阻层103,在栅极绝缘膜102上形成栅极电极104。
接着,如图7所示,为了使多晶硅电阻层103的接触形成区域有良好的电连接,将抗蚀剂膜105作为掩模进行离子注入,在多晶硅电阻层103上形成低电阻区域106a~106c(高浓度杂质注入区域)。
另外,在MOS晶体管形成区域,也在形成低电阻区域106a~106c的同时进行离子注入,且形成源极区域107及漏极区域108。之后,为使注入的杂质活化,在高温(例如950℃)下进行约1小时的热处理(退火)。
接着,如图8所示,在半导体基板100的整个面上形成层间绝缘膜109,之后在多晶硅电阻层103、源极区域107及漏极区域108上所希望的位置上开口形成接触孔110。接着,通过在各接触孔110内形成金属配线116,多晶硅电阻层103及MOS晶体管与其它元件电连接。图9为从上方看的通过以上的工序而形成的半导体装置的平面概略图。
专利文献1(日本)特开平5-129294号公报
但是,电阻元件的电阻值R通过R=Rs×L/W而定。在此,Rs为薄层电阻(Ω/sp),L为电阻元件的长,W为其宽。所示多晶硅电阻层103中,其构图尺寸(薄层电阻Rs、长L、宽W)为得到所希望的电阻值R而预先设计,且在制造过程中不变。
以往,如图7所示,将使用抗蚀剂膜105进行离子注入的间距X、Y定义为电阻元件的长L而设计电阻元件。在此,X为相邻的低电阻区域106a、106b之间的长,Y为低电阻区域106b、106c之间的长,例如X=1200μm、Y=70μm。
但是,在上述以往的制造工序中,低电阻区域形成后,为使其它的有源元件的杂质区域活化,需要进行高温热处理(退火),因此,如图8、图9所示,低电阻区域106a~106c在横向上扩散规定的距离Z,成为低电阻区域115a~115c。因此,预先设计的电阻元件的长X、Y变短为X′、Y′,产生理论电阻值与实测电阻值出现偏差的问题。电阻元件越微小,此偏差越显著,特别是在分割电阻仅取出微小电压的情况下等,成为大问题。
通过预先更长地设定低电阻区域X、Y的距离来回避将出现的偏差,但这样多晶硅电阻层103所占面积增大,从而使芯片面积增大。
发明内容
本发明的目的在于,在减小电阻元件的理论电阻值与实测电阻值的偏差的同时,实现电阻元件的小型化。
本发明的主要特征如下:及,本发明的半导体装置的制造方法,其特征在于,具有:在半导体基板的表面形成绝缘膜的工序;在所述绝缘膜上形成半导体电阻层的工序;形成覆盖所述半导体电阻层的层间绝缘膜的工序;在所述层间绝缘膜上形成使所述半导体电阻层局部露出的接触孔的工序;经由所述接触孔在所述半导体电阻层进行离子注入、在所述半导体电阻层上形成低电阻区域的工序。
本发明的半导体装置的制造方法,该半导体装置在同一半导体基板上具有半导体电阻层及MOS晶体管,其特征在于,具有:在半导体基板的表面上形成元件分离绝缘膜及所述MOS晶体管的栅极绝缘膜的工序;在所述元件分离绝缘膜上形成所述半导体电阻层的工序;在所述栅极绝缘膜上形成所述MOS晶体管的栅极电极的工序;用于形成所述MOS晶体管的源极区域及漏极区域而进行第一离子注入的工序;形成层间绝缘膜的工序,该层间绝缘膜具有使所述半导体电阻层、所述源极区域及所述漏极区域局部露出的接触孔;经由所述接触孔进行第二离子注入、且在所述半导体电阻层上形成用于降低接触电阻的低电阻区域的工序。
半导体装置的制造方法,其特征在于,具有:将通过所述第一离子注入而注入的离子活化的第一热处理工序;在低于所述第一热处理的温度的条件下,使通过所述第二离子注入而注入的离子活化的第二热处理工序。
根据本发明,能够提供一种可减小电阻元件的理论电阻值与实测电阻值的偏差、使电阻值稳定的半导体装置。
附图说明
图1是说明本发明的半导体装置的制造方法的剖面图;
图2是说明本发明的半导体装置的制造方法的剖面图;
图3是说明本发明的半导体装置的制造方法的剖面图;
图4是说明本发明的半导体装置的制造方法的剖面图;
图5是说明本发明的半导体装置的制造方法的平面图;
图6是说明以往的半导体装置的制造方法的剖面图;
图7是说明以往的半导体装置的制造方法的剖面图;
图8是说明以往的半导体装置的制造方法的剖面图;
图9是说明以往的半导体装置的制造方法的平面图。
附图标记
1 半导体基板
2 场绝缘膜
3 栅极绝缘膜
4 多晶硅电阻层
5 栅极电极
6 抗蚀剂膜
7 源极区域
8 漏极区域
9 层间绝缘膜
10 接触孔
11 接触孔
15a~15c 低电阻区域
16 金属配线
100 半导体基板
101 场绝缘膜
102 栅极绝缘膜
103 多晶硅电阻层
104 栅极电极
105 抗蚀剂膜
106a~106c 低电阻区域
107 源极区域
108 漏极区域
109 层间绝缘膜
115a~115c 低电阻区域
X、Y、X′、Y′、L1、L2 电阻元件的长
Z 扩散距离
具体实施方式
下面,参照附图对本发明的实施方式进行说明。图1至图4为分别按顺序表示的制造工序的剖面图,图5为图4的平面概略图。另外,以下的工序是对在同一半导体基板上具有多晶硅电阻层及MOS晶体管的半导体装置的制造工序进行说明,将双极晶体管等有源元件形成于同一半导体基板上,当然也是可能的。
首先如图1所示,在半导体基板1的表面通过选择氧化法(SelectiveOxidation Method)形成场绝缘膜2,将MOS晶体管形成区域进行元件分离。这也称为硅的局部氧化(LOCOS)。
接着,在场绝缘膜2包围的区域的半导体基板1的表面上,例如通过热氧化法等,形成MOS晶体管的栅极绝缘膜3。
接着,在半导体基板1的整个面上例如以CVD法形成例如400nm膜厚的多晶硅层,其后对该多晶硅层注入杂质(例如磷离子或砷离子),使其后形成的多晶硅电阻层4具有所希望的薄层电阻(例如5KΩ/sp)。该离子注入例如在磷离子以加速电压70KeV,注入量5×1014/cm2的条件下进行。
接着,在整个面上形成氧化膜(未图示),将抗蚀剂膜(未图示)作为掩模,将MOS晶体管的形成区域的氧化膜蚀刻而除去。进而,除去抗蚀剂膜,将多晶硅电阻层4的形成区域上的氧化膜作为掩模,其后,在栅极电极5形成的多晶硅层上,实施将POCl3作为扩散源的磷掺杂,以实现低于多晶硅电阻层4的低电阻化。另外,在本实施方式中,在形成栅极电极5的多晶硅层上实施磷掺杂,也可以通过使用磷离子等的离子注入法来实现低电阻化。
接着,通过将未图示的抗蚀剂膜作为掩模,对该多晶硅层进行干蚀刻等,进行构图,而在场绝缘膜2上形成多晶硅电阻层4,在栅极绝缘膜3形成MOS晶体管用的栅极电极5。在此,如上所述栅极电极5比多晶硅电阻层4更低电阻化。另外,所述离子注入也可以在构图多晶硅层之后进行。
接着,如图2所示,以抗蚀剂膜6覆盖多晶硅电阻层4,在半导体基板1的表面上,注入杂质(例如磷离子或砷离子),形成MOS晶体管的源极区域7及漏极区域8。该离子注入例如在磷离子以加速电压70KeV,注入量1×1014/cm2、砷离子以加速电压80KeV,注入量6×1015/cm2的条件下进行。之后,在高温(例如950℃)下进行约1小时的热处理(退火),使注入的载流子活化。
接着,如图3所示,在半导体基板1的整个面上形成层间绝缘膜9(例如,用CVD法形成的氮化硅膜及BPSG膜)。接着,通过进行例如950℃左右的热处理,使所述层间绝缘膜9(BPSG膜)的表面形状变得平缓,以实现平坦化。其后有选择地蚀刻该层间绝缘膜9,形成分别使多晶硅电阻层4、源极区域7及漏极区域8局部露出的接触孔10、11。接触孔10、11的直径例如为1.6μm左右。
接着,经由接触孔10注入杂质(例如磷离子、砷离子),在多晶硅电阻层4上形成低电阻区域15a~15c(高浓度杂质注入区域)。这样形成低电阻区域15a~15c正如前面所述,是为了减小与金属配线的接触电阻,使接触区域的电连接良好。该离子注入例如在磷离子以加速电压80KeV,注入量2×1015/cm2的条件下进行。另外,进行该离子注入工序时,也可以在MOS晶体管等有源元件的形成区域中由抗蚀剂膜等覆盖接触孔11,在该被覆盖的区域不进行该离子注入。
在此,形成接触孔10、11之后的处理中,从防止器件特性的恶化的观点看,不进行高温热处理。因此,包括使被注入的载流子活化的热处理在内,本实施方式的低电阻区域15a~15c形成后的热处理(退火)能够以比所述源极、漏极区域形成时更低的温度(例如,700~900℃)进行。另外,用于使注入到低电阻区域15a~15c的载流子活化的热处理的时间为例如30分钟至60分钟左右。因此,与以往的半导体装置的制造方法相比较,注入到低电阻区域15a~15c的杂质离子在水平方向几乎不扩散。因此,将相邻接触孔间距定义为电阻元件的长L1、L2,然后再设定电阻元件的构图尺寸,能够将理论电阻值与实测电阻值的偏差控制在较低水平。例如,L1=1200μm,L2=70μm。
在该活化处理时,通过对所述层间绝缘膜9(BPSG膜)进行热处理,在层间绝缘膜9上形成的接触孔10、11的形状变得平缓。因此,由于接触孔10、11的开口端部带有圆角,能够较好地形成后述的金属配线16。
并且,在如上所述使注入的载流子活化的同时,用于使接触孔10、11的开口端部带有圆角的热处理在同一工序中进行的情况下,为了使层间绝缘膜9(BPSG膜)流动,优选在比700℃更高的温度(例如800℃~900℃)下进行热处理。另外,如果仅进行所述活化处理,则只要是高于700℃的温度即可。
接着,如图4所示,通过在各接触孔内以溅射法等形成由铝或钛等构成的金属配线16,多晶硅电阻层4及MOS晶体管与其它元件电连接。
如上所述,在本实施方式中,多晶硅电阻层4的低电阻区域15a~15c的离子注入及其热处理(退火),在各接触孔10、11形成后进行。根据本制造方法,如前所述,由于接触孔形成后不进行使LSI操作特性恶化的高温热处理,因此低电阻区域15a~15c几乎不扩散,若将相邻接触孔间距定义为电阻元件区域的长L,则能够得到几乎不偏离于理论电阻值的电阻值。根据本发明的发明人的验证,相对于在以往的制造方法中,将多晶硅电阻层进行电阻分割而使用的情况下,其与理论值的输出电压的偏差约为10%,而本实施方式的制造方法中,其偏差能够被抑制为不足1%。
因此,根据本发明,能够制造不增加半导体电阻层的面积而使理论电阻值与实测电阻值几乎无偏差、且具有稳定的电阻值的半导体装置。特别适宜于如本实施方式的进行输出电压的电阻分割的情况下,提高其精度。
另外,由于将形成有接触孔10、11的层间绝缘膜9作为用于形成低电阻区域15a~15c的掩模来使用,不会增加掩模的数目,也不会增加制造成本。
另外,上述实施方式中,对多晶硅电阻层4上形成三个接触孔、将输出电压进行电阻分割的情况进行了说明,但也可以形成多个接触孔,另外,还可以作为形成两个接触孔的简单的电阻元件来使用。
另外,毋庸置疑,本发明并不局限于上述实施方式,只要在不脱离其主旨的范围内,还可以进行变更,为能够广泛应用于具有电阻元件的半导体装置的制造方法。
Claims (2)
1.一种半导体装置的制造方法,该半导体装置在同一半导体基板上具有半导体电阻层及MOS晶体管,其特征在于,具有:
在半导体基板的表面上形成元件分离绝缘膜及所述MOS晶体管的栅极绝缘膜的工序;
在所述元件分离绝缘膜上形成所述半导体电阻层的工序;
在所述栅极绝缘膜上形成所述MOS晶体管的栅极电极的工序;
为形成所述MOS晶体管的源极区域及漏极区域而进行第一离子注入后,使通过所述第一离子注入而注入的离子活化的第一热处理工序;
形成层间绝缘膜的工序,该层间绝缘膜具有使所述半导体电阻层、所述源极区域及所述漏极区域局部露出的接触孔;
经由所述接触孔进行第二离子注入、在所述半导体电阻层上形成用于降低接触电阻的低电阻区域后,在低于所述第一热处理的温度的条件下,使通过所述第二离子注入而注入的离子活化的第二热处理工序。
2.如权利要求1所述的半导体装置的制造方法,其特征在于,所述半导体电阻层由多晶硅层构成。
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CN102890195B (zh) * | 2011-07-20 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | 测试与衬底同型的有源区上接触孔电阻的方法 |
CN106033710B (zh) * | 2015-03-13 | 2019-10-15 | 北大方正集团有限公司 | 一种多晶电阻的制作方法 |
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