CN100481406C - 改进的蚀刻方法 - Google Patents

改进的蚀刻方法 Download PDF

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CN100481406C
CN100481406C CNB2005800181167A CN200580018116A CN100481406C CN 100481406 C CN100481406 C CN 100481406C CN B2005800181167 A CNB2005800181167 A CN B2005800181167A CN 200580018116 A CN200580018116 A CN 200580018116A CN 100481406 C CN100481406 C CN 100481406C
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substrate
sub
etching
area
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CN1977376A (zh
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J·克卢斯特曼
P·迪克斯特拉
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Koninklijke Philips NV
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Abstract

公开一种蚀刻结构的改进方法以及由该方法蚀刻的结构。结构的实例为IC封装的引线框的底侧，有利地可以通过所公开的方法对其进行蚀刻。该方法包括给要被蚀刻的衬底设置蚀刻掩模的步骤。该蚀刻掩模包括至少两个子掩模：覆盖在蚀刻工艺之后基本上保留下来的区域的第一子掩模，以及覆盖在蚀刻工艺中要被除去的区域的第二子掩模。第二子掩模为格栅形式的牺牲掩模。第二子掩模的存在增大了其所覆盖的区域的蚀刻速度。

Description

改进的蚀刻方法
技术领域
本发明涉及一种蚀刻结构的方法以及由该方法蚀刻的结构，特别涉及结构的回蚀刻(back-etching)，例如用于IC封装的引线框。
背景技术
半导体器件的制造和封装包括多个步骤。作为第一个步骤，就是对整个半导体器件或管芯的晶片进行加工。各个管芯分开并且安装在引线框上。引线框通过支持管芯上结合垫之间的电连接以及在管芯被封装并且密封之后可以被接通的电连接来提供至半导体器件本身的电通路(electrical access)。
已有许多类型的封装并且正在研发新类型，例如用于生产更小的封装。更小的封装支持更小的引线，这是所希望的，尤其是对于高频应用来说，因为大管脚使高频信号退化。
在典型的封装中环氧树脂层覆盖半导体器件并且引线为从封装的一侧突出的小金属管脚。然而，在更新更小的封装类型中，从封装的表面中蚀刻出引线框，典型地从封装的背面中蚀刻，使得引线框成为封装的组成部分。
在PCT申请WO/03/085728中描述了这种封装的一种实例。在那里管芯附着在预先蚀刻的层状衬底上。将该管芯封装在环氧树脂中并且进一步对中间封装的背面进行蚀刻，以制作具有从封装的背面突出的引线的封装。
为了以所希望的方式对衬底进行构图，例如用于制造引线以所希望的方式突出的封装，可以通过蚀刻掩模以及随后的蚀刻对封装的表面进行构图。然而，在蚀刻工艺中，在蚀刻过程中也除去了被掩模覆盖的部分衬底，也就是所谓的底部蚀刻(under-etching)。因而，在蚀刻工艺中在蚀刻掩模下越来越多的材料被除去。通常一些底部蚀刻是不可避免的并且是可以容忍的，但是应当避免关键性的底部蚀刻。对于要被除去的衬底的给定厚度，给定蚀刻时间是必要的，因而在其他参数中，所需图案的最小分辨率是衬底厚度的函数。为了增加图案的分辨率，一种解决方案是降低衬底的厚度。然而，得到的结构也需要一定的厚度，使得在一定厚度下将衬底变薄是不可能的。
发明内容
本发明的发明者已经意识到所需蚀刻掩模的底部蚀刻可能是不希望有的，并由此作出本发明。
本发明的第一个目的是提供一种用于在衬底中蚀刻出结构如图案的改进的蚀刻方法。
本发明的另一个目的是提供一种改进的蚀刻方法，用于对电子器件的侧或表面进行构图。
本发明的再一个目的是在部分制造的电子器件的侧或表面上设置蚀刻掩模，其允许在制造过程中的稍后阶段在不使用光刻的情况下进一步对所述侧或表面进行构图的可能性。
因此提供一种蚀刻结构的方法，该方法包括下述步骤：
-设置第一材料的衬底，
-在该衬底的顶部上按照所需图案设置第二材料的蚀刻掩模，该蚀刻掩模包括至少两个子掩模：
-以第一子图案覆盖衬底的第一区域的第一子掩模，该第一子掩模在蚀刻工艺之后基本上保留下来，以及
-以第二子图案覆盖衬底的第二区域的第二子掩模，该第二子掩模是牺牲掩模，该牺牲掩模增大了该至少第二区域中的蚀刻速度，
-对衬底蚀刻预定时间。
衬底可以是电子器件的底侧或者在其上希望蚀刻出图案的侧。例如，衬底可以是层状结构中的外层，例如引线框的底侧。通常衬底可以是覆盖任意类型的结构的外层，包括包含集成电路的衬底，基于半导体的传感器、MEMS器件、滤波器如大消声器、无源部件网络等等。衬底还可以是支撑一个以上的半导体器件的装置的一侧，那么该衬底也可以用作用于该装置的互连的附加互连层。
作为实例，引线框可以用一系列的加工步骤制造，这些步骤通常包括在引线框的顶侧上进行光刻。引线框的底侧可以设置有包括第一和第二子掩模的蚀刻掩模。接着，可以将半导体部件即管芯设置到引线框并且以一种方式进行封装，使得引线框可以机械地锚定在该封装中，从而管芯和引线框形成半个单元。经常将这称作封装。在稍后的加工步骤中，可以进一步对引线框进行蚀刻，从而可以提供根据第一子掩模的图案。有利的是，可以在封装工艺之后蚀刻引线框而不使用光刻，例如因为在装配工厂中可以避免光刻加工。
通常地，该衬底是将要以所需方式进行构图的衬底。将衬底分成至少两个区域，在蚀刻加工之后将保留的区域和在蚀刻工艺之后将被除去的区域。蚀刻工艺之后保留的所需图案可以包括多个岛状结构。每个岛状结构可以具有基本上相同的形状，一些岛状结构可以具有基本相同的形状，而其他的具有不同的形状，可以存在多种不同形状的岛状结构等等。
为了蚀刻出图案，在衬底的表面上设置蚀刻掩模。该蚀刻掩模包括两个子掩模。用于限定所需图案或者所需结构以在蚀刻工艺之后保留的第一子掩模以及第二子掩模。第二子掩模是牺牲掩模，其具有的目的是增大其所覆盖的区域中的蚀刻速度。因而在将要通过蚀刻工艺被除去的区域中设置第二子掩模，该第二子掩模也通过蚀刻工艺被除去。第一和第二子掩模可以设置在单个步骤中，或者第一和第二子掩模可以设置在两个步骤中或者一系列步骤中。可以根据设置蚀刻掩模的任何适当方式设置蚀刻掩模。例如，可以通过电镀图案来设置蚀刻掩模。作为另一个实例，可以使用聚合物蚀刻掩模即抗蚀剂来设置蚀刻掩模。蚀刻掩模可以是正或负蚀刻掩模。
沿衬底的垂直方向或z-方向与衬底的水平方向，即衬底的(x，y)-平面内的任何方向的蚀刻速度之间的比率在由第二子掩模覆盖的区域中可以被增大。
根据本发明的方法的优点在于，能够在无需降低衬底的厚度的情况下增大衬底中将要被蚀刻出的所需图案的分辨率。可替换地，优点可以在于可以决定衬底的厚度，而无需考虑图案的预期分辨率。另一个优点在于，对于具有与图案的分辨率相比相当大的厚度的衬底来说，可以实现衬底的基本上均匀的蚀刻。
蚀刻工艺之后保留的所需图案可以由一个或多个岛状结构构成。这些结构可以是蚀刻前衬底中的一个或多个区域，这些区域被第一子掩模覆盖在表面上并且称作第一区域。同样地，第二子掩模限定了在蚀刻工艺期间衬底的将要被除去的一个或多个区域，这些区域称作第二区域。还可以存在没有被蚀刻掩模覆盖的区域，这些区域也可以在蚀刻工艺中被除去。当第二区域的尺寸比第一区域的尺寸大时，第二子掩模可以设置在一个区域中并且由此限定衬底的第二区域。在一个或多个第二区域比至少一个第一区域大的情况下根据本发明设置蚀刻掩模可以是有利的。
衬底的材料，即第一材料，可以是金属或具有金属的导电性的材料。材料的例子包括Al、Cu、Ni或其混合物的任何合金。衬底可以形成材料叠层的一部分，其中叠层中的各材料是金属或具有金属的导电性的材料。例如，衬底可以是一部分的Cu/Al/Cu叠层、Cu/Al叠层、Cu/Ni/Cu叠层等。作为一般性例子，衬底可以是金属叠层的一部分，从该金属叠层可以单独地蚀刻掉各个金属。该材料可以是导电的，例如如果衬底形成引线框的一部分，其中所得到的结构构成引线。然而衬底也可以是半导体材料或绝缘材料。衬底的厚度可以在10和100微米之间，例如在25和75微米之间，例如50微米。
蚀刻掩模的材料，即第二材料，可以是具有可焊接精整(solderablefinish)的材料。因而，该材料可以是支持焊接的材料，即该材料可以借助焊料粘接到另一个物体的表面上。例如在利用倒装芯片安装的连接中，其中两个物体借助焊料凸起彼此附着。材料的例子包括Ag、Pd、Au、Ni或其混合物的任何合金，例如NiPdAu。作为一般性实例，蚀刻掩模的材料可以是不受用于蚀刻掉衬底的蚀刻剂侵蚀或者以低得多的速率被其侵蚀的材料。使用具有可焊接精整的材料作为蚀刻掩模可以是有利的。
牺牲掩模的图案，即第二子掩模的图案可以是格栅的形式，如正方形格栅、矩形格栅、六边形格栅等。此外，与栅栏的简单交叉相比，格栅中的交叉点可以在尺寸上被扩大或者减小。第二子掩模可以是格栅的分支形式，或者第二子掩模可以是格栅中的开口形式。
格栅可以由牺牲掩模的子单元构成。这些子单元可以设有特定尺寸，其中这些子单元的特征尺寸与衬底的厚度以及工艺的蚀刻因子相关。子单元的特征尺寸例如在这些子单元的形状为方形的情况下是这些子单元的宽度，以及在这些子单元为圆形的情况下是子单元的直径。然而，这些子单元也可以拥有更复杂的形状，在这种情况下特征尺寸为这些子单元的特征宽度或长度。
衬底的厚度可以取决于许多因素，并且蚀刻因子可以取决于衬底的材料、要蚀刻的图案等。因此这些子单元的尺寸和形状可以取决于衬底的厚度以及蚀刻因子。这些子单元的特征尺寸和衬底厚度之间的比率可以在特征尺寸和蚀刻因子之间的比率的0.75和1.25之间，例如在0.85和1.15之间，例如在0.95和1.05之间，例如近似相等。因而可以提供大约1:1:1的比率。
根据本发明的另一个方面，根据蚀刻掩模设置衬底表面上的图案，其中蚀刻之前的衬底由蚀刻掩模覆盖，该蚀刻掩模包括至少两个子掩模：
-以第一子图案覆盖第一区域的第一子掩模，该第一子掩模在蚀刻工艺之后基本上保留，以及
-以第二子图案覆盖第二区域的第二子掩模，该第二子掩模是牺牲掩模，该牺牲掩模增大了该至少第二区域中的蚀刻速度，
其中在蚀刻工艺之后衬底与第一子图案接触的面积为第一子图案的面积的至少30％，例如为至少40％，例如为至少50％，例如为至少60％，例如为至少70％，例如为至少80％，例如为至少90％，例如为几乎100％。
由于蚀刻掩模的底部蚀刻，蚀刻工艺之后衬底与蚀刻掩模接触的面积小于蚀刻掩模的面积。根据要被蚀刻的图案，跨越衬底可以存在蚀刻速度的变化，引起跨越衬底的底部蚀刻的程度的变化。通常本发明的优点在于，可以使用本发明获得的图案与没有使用本发明蚀刻出或者试图蚀刻出的相同图案相比，可以被提供有更小程度的底部蚀刻。
作为本发明的结果，可以在IC封装中使用较厚的引线框。使用具有一定厚度的引线框可以是有利的，因为可以获得更坚固的引线框，更坚固的引线框可能是所需要的，因为对引线框或IC封装的处理的关注很少。然而，由于较厚的引线框会导致较大程度的底部蚀刻，所以在不使用本发明的情况下厚引线框受限于所需图案的可获得的分辨率。本发明的结果是在设置有第二子掩模的区域中增大了蚀刻因子。蚀刻因子取决于不同的方面，例如衬底的材料、第二子掩模的形状和尺寸等。然而，可以获得的蚀刻因子越高，可以使用的衬底就越厚。
本发明的再一优点在于通过本发明的方法可以提供用于IC封装制造中的引线框的非标准底部布局。
附图说明
参考下文描述的实施例，本发明的这些和其他方面、特征和/或优点将变得明显并将被阐明。
现在参考附图对本发明的优选实施例进行详细描述，其中：
图1示出了在附着半导体器件之前的引线框，
图2示出了IC封装，
图3示出了IC封装底侧上的引线构造的实施例，
图4示出了没有使用本发明时衬底的蚀刻，
图5示出了没有使用本发明时衬底的另一种蚀刻，
图6示出了蚀刻掩模的底部蚀刻，
图7示出了根据本发明的蚀刻掩模的第一实施例，
图8示出了使用根据本发明的蚀刻方法时衬底的蚀刻，
图9示出了使用根据本发明的蚀刻方法时蚀刻掩模的底部蚀刻，
图10示出了根据本发明的蚀刻掩模的第二实施例。
这些图是示意性的并且没有按比例绘制。不同图中类似的参考数字表示相同或相似的部分。这些图和说明仅仅是实例而且不应当看作是设定本发明的范围。
具体实施方式
半导体器件的制造和封装包括多个步骤。在这部分中结合引线框的回蚀刻对本发明进行描述，该引线框是通过利用电镀在衬底表面上的NiPd-Au蚀刻掩模由Cu/Al/Cu叠层制造的。参考图1，引线框的材料为Cu7、Al8和Cu6。因此在本实施例中，衬底为Cu层6。
在图1中已经进行了多个步骤。该图示出了在附着半导体器件之前的引线框。如图1所示的引线框1的制作在本领域中是已知的(参见例如PCT申请WO/03/085728)。引线框通过衬底6端接于底侧。
在图2中，示出了最终的IC封装20。在该图中，半导体器件或管芯3线接合到引线框的上侧。该管芯和部分引线框被封装在封装材料如环氧树脂4中。引线框借助小凹进5锚定在环氧树脂中。结合随后的图对根据本发明包括于在最终IC封装时发生的步骤进行讨论。在图2中根据蚀刻掩模2的图案将部分衬底6蚀刻掉，从而形成岛状引线(21-23)，由此提供从封装外部到管芯的电连接。在引线之间设置保护绝缘层24。该保护层可以是所谓的转换层，是从CrO2、TiO2、ZrO2、CeO2等的组中选择的材料的层。可以在其上施加具有良好选择的热膨胀系数的有机层。
图3中示出了从IC封装底侧突出的引线的所希望的构造30的实例(下文也将这些引线称作占位空间(footprint))。
在图4-6和8，9中，在封装的底侧上形成NiPd-Au图案。该NiPd-Au图案用作用于对封装底侧上的铜进行蚀刻的蚀刻掩模，或者蚀刻抗蚀剂。该Cu层的厚度范围为30到90微米。这些图示出了利用普通显微镜得到的图像。
在如图3中所示的图案中，在封装中央的区域33比各个占位空间31下面的区域大很多倍。因而，衬底中央的面积/区域限定了本文中其他地方所称的第二面积/区域，而由占位空间限定的面积/区域限定了本文中其他地方所指的第一面积/区域。如果使用标准蚀刻方法的话，其中只有蚀刻工艺之后保留下来的区域被蚀刻掩模覆盖，那么由于尺寸不同，NiPd-Au占位空间下面的Cu区域比封装中央的Cu更快地被蚀刻掉。占位空间的尺寸可以根据所需要的IC封装而改变。然而典型的占位空间尺寸通常在150微米×250微米和250微米×350微米之间。
在图4和5中，示出了在不使用本发明的情况下的蚀刻能力，典型地可以获得0.2到0.75的蚀刻因子。该蚀刻因子为z方向上的蚀刻速度和x方向(或者(x，y)平面内的任何其他方向)上的蚀刻速度之间的比率。
在图4中，在占位空间之间的材料被除去使得占位空间彼此隔离时停止蚀刻。然而，封装中央的Cu 33因蚀刻因子低而仍然保留在表面上。
在图5中，当中央的Cu 53几乎被去除时停止蚀刻。然而，在这种情况下，占位空间51也被除去了。
由于封装底部上的Cu层的厚度，NiPd-Au图案的底部蚀刻致使封装底侧的高分辨率图案的蚀刻变得困难。图6中示出了蚀刻掩模的底部蚀刻，其示出了衬底的截面。在这种情况下NiPd-Au占位空间61几乎从引线框中被去除，因为与Al 63接触的Cu 62因底部蚀刻几乎被去除。
在图7中示出了根据本发明的蚀刻掩模80。该蚀刻掩模分为第一子掩模和第二子掩模。第一子掩模包括所需要的图案，即根据所需要的占位空间31设置第一子掩模70，71，72，73，即在衬底的四个区域70-73中设置NiPd-Au掩模，该NiPd-Au掩模覆盖所需占位空间31的区域。第二子掩模74设置在要被除去的区域中。在所示实施例中，第二子掩模由小矩形区域的图案构成。第二子掩模由覆盖Cu的区域76即格栅上的分支和没有覆盖Cu的区域75即格栅中的开口构成。通过使用如图7中所示的蚀刻掩模，蚀刻速度可以增大到这样的程度使得可以获得1到1.5的最终蚀刻因子。第二子掩模为牺牲掩模并且其在蚀刻工艺期间被除去。第二子掩模因该掩模下面的材料被蚀刻掉而被除去。
在图8中示出了与图4和5中的那些相似的引线框的底侧，然而根据本发明对衬底进行蚀刻，即利用图7中所示的蚀刻掩模。可以看到封装中央的Cu被完全除去，而占位空间31没有。
在图9中示出了用于图8中所示的引线框的占位空间的底部蚀刻。该图示出了与图8中标记为90的区域相对应的部分，但是以略微倾斜的角度观察的。在该图中看到黑暗区域93和多个亮点91，92。黑暗区域93是已经除去了Cu的地方，而亮点是占位空间。每个占位空间分开成两个，并且上部91为NiPd-Au掩模且下部92为掩模下面的铜。因而，该图与图6对应，除了图6为占位空间的特写侧视图之外，而图9示出了以略微倾斜的角度观察的多个占位空间。观察到NiPd-Au下面的Cu94的宽度几乎与NiPd-Au占位空间95的宽度一样大，因而通过使用图7中所示的蚀刻掩模抑制了底部蚀刻。
在封装的底侧上形成牺牲掩模导致了可以蚀刻高分辨率图案的事实。划分封装中央的大Cu区域导致了Cu与蚀刻剂直接接触的区域减小的事实，然而这导致由第二子掩模所覆盖的区域，即封装中央的蚀刻速度增大。在图7所示的蚀刻掩模中，小矩形为60微米×60微米大。矩形区域的尺寸将尤其取决于衬底的厚度以及该工艺的蚀刻因子。开口区域的形状也可以改变。在图10中示出了可替换的实施例。在图案中，在开口空间100的边缘处设置小突起。这将四个垫之间的开口空间的尺寸最小化，并且使得该空间的对角线是与侧面相同的长度。
虽然结合优选实施例对本发明进行了描述，但是不是要局限于此处阐述的具体形式。更确切地说，本发明的范围仅由所附权利要求限定。
在该部分中，对所公开实施例的特定具体细节例如引线框的回蚀刻、材料的选择、引线的数量和形式等的阐述是出于解释而不是限制的目的，从而提供对本发明的清楚和完整的理解。然而，本领域技术人员应当容易理解，在不明显脱离该公开的精神和范围的情况下，本发明可以以与这里阐述的细节并不完全一致的其他实施例实现。而且，在该上下文中，出于简明和清楚的目的，已经省略了公知装置、电路和方法的详细描述以避免不必要的细节和可能的混乱。
应当理解，对单数的引用也旨在包含复数，而且反之亦然，并且对具体数量的特征或装置的引用不应被解释为将本发明限制为该具体数量的特征或装置。而且，诸如“包括”、“包含”、“具有”、“拥有”、“并入”、“含有”的表述应被解释为非专门性的，也就是说这种表述应被解释为不排除存在其他项。
权利要求中包括参考标记，然而包括这些参考标记仅仅是为了清楚起见，并且不应当解释为对权利要求的范围的限制。

Claims (16)

1、蚀刻结构的方法，该方法包括下述步骤：
-设置第一材料的衬底(6，32)，
-在该衬底的顶部上按照所需图案设置第二材料的蚀刻掩模(80)，该蚀刻掩模包括至少两个子掩模：以第一子图案覆盖所述衬底的第一区域的第一子掩模(70-73)，该第一子掩模在蚀刻工艺之后保留下来，以及
以第二子图案覆盖所述衬底的第二区域的第二子掩模(74)，该第二子掩模是牺牲掩模，该牺牲掩模增大了该至少第二区域中的蚀刻速度，
-对衬底蚀刻预定时间。
2、根据权利要求1的方法，其中在衬底的垂直方向上与衬底的水平方向上的蚀刻速度之间的比率在该至少第二区域中增大。
3、根据权利要求1的方法，其中该第一区域在衬底的蚀刻之后保留下来，并且其中该第二区域通过蚀刻衬底被除去，其中第二区域的尺寸比第一区域的尺寸大，并且其中在第二区域中设置牺牲掩模。
4、根据权利要求1的方法，其中第一材料为导电材料。
5、根据权利要求1的方法，其中第二材料支持焊接。
6、根据权利要求1的方法，其中牺牲掩模的图案为格栅。
7、根据权利要求6的方法，其中该格栅由牺牲掩模的子单元(75，100)构成，其中子单元的特征尺寸、衬底的厚度以及该工艺的蚀刻因子是相关的，使得这些子单元的特征尺寸和衬底的厚度之间的比率在该特征尺寸和蚀刻因子之间的比率的0.75和1.25之间。
8、根据权利要求7的方法，所述子单元的特征尺寸和衬底的厚度之间的比率在该特征尺寸和蚀刻因子之间的比率的0.85和1.15之间。
9、根据权利要求8的方法，所述子单元的特征尺寸和衬底的厚度之间的比率在该特征尺寸和蚀刻因子之间的比率的0.95和1.05之间。
10、根据权利要求9的方法，所述子单元的特征尺寸和衬底的厚度之间的比率在该特征尺寸和蚀刻因子之间的比率相等。
11、根据权利要求1的方法，其中衬底形成引线框的一部分。
12、根据权利要求1的方法，其中衬底是层状结构的外层。
13、根据权利要求12的方法，其中衬底是引线框的底侧。
14、根据蚀刻掩模设置在衬底上的图案，其中蚀刻之前的衬底由蚀刻掩模覆盖，该蚀刻掩模包括至少两个子掩模：
-以第一子图案覆盖第一区域的第一子掩模(70-73)，该第一子掩模在蚀刻工艺之后保留下来，以及
-以第二子图案覆盖第二区域的第二子掩模(74)，该第二子掩模是牺牲掩模，由于与蚀刻剂直接接触的至少一部分第二区域减少，该牺牲掩模增大了该至少第二区域中的蚀刻速度。
15、根据权利要求14的衬底上的图案，其中第二子掩模的图案为格栅。
16、根据权利要求15的衬底上的图案，其中第二子掩模的图案为正方形格栅、矩形格栅、六边形格栅。
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