TW200625563A - Improved etch method - Google Patents

Improved etch method

Info

Publication number
TW200625563A
TW200625563A TW094118047A TW94118047A TW200625563A TW 200625563 A TW200625563 A TW 200625563A TW 094118047 A TW094118047 A TW 094118047A TW 94118047 A TW94118047 A TW 94118047A TW 200625563 A TW200625563 A TW 200625563A
Authority
TW
Taiwan
Prior art keywords
mask
sub
etched
area
etching
Prior art date
Application number
TW094118047A
Other languages
English (en)
Inventor
Jan Kloosterman
Paul Dijkstra
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of TW200625563A publication Critical patent/TW200625563A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
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    • H01L2224/0554External layer
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • ing And Chemical Polishing (AREA)
TW094118047A 2004-06-04 2005-06-01 Improved etch method TW200625563A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04102537 2004-06-04

Publications (1)

Publication Number Publication Date
TW200625563A true TW200625563A (en) 2006-07-16

Family

ID=34970003

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094118047A TW200625563A (en) 2004-06-04 2005-06-01 Improved etch method

Country Status (6)

Country Link
US (1) US8070971B2 (zh)
EP (1) EP1756866A1 (zh)
JP (1) JP2008501858A (zh)
CN (1) CN100481406C (zh)
TW (1) TW200625563A (zh)
WO (1) WO2005119768A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110707005B (zh) * 2018-08-03 2022-02-18 联华电子股份有限公司 半导体装置及其形成方法
US11002063B2 (en) * 2018-10-26 2021-05-11 Graffiti Shield, Inc. Anti-graffiti laminate with visual indicia
CN112490131A (zh) * 2020-11-27 2021-03-12 西安交通大学 一种基于刻蚀工艺的引线框架制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3225206C1 (de) * 1982-07-06 1983-10-27 Dr. Johannes Heidenhain Gmbh, 8225 Traunreut Verfahren zum einseitigen Ätzen von Platten
CH682528A5 (fr) * 1990-03-16 1993-09-30 Westonbridge Int Ltd Procédé de réalisation par attaque chimique d'au moins une cavité dans un substrat et substrat obtenu par ce procédé.
US5695658A (en) * 1996-03-07 1997-12-09 Micron Display Technology, Inc. Non-photolithographic etch mask for submicron features
KR100224730B1 (ko) * 1996-12-17 1999-10-15 윤종용 반도체장치의 패턴 형성방법 및 이를 이용한 커패시터 제조방법
CN1295563C (zh) * 2001-05-18 2007-01-17 皇家菲利浦电子有限公司 制造器件的光刻法
AU2003219354A1 (en) * 2002-04-11 2003-10-20 Koninklijke Philips Electronics N.V. Carrier, method of manufacturing a carrier and an electronic device

Also Published As

Publication number Publication date
CN100481406C (zh) 2009-04-22
EP1756866A1 (en) 2007-02-28
US8070971B2 (en) 2011-12-06
JP2008501858A (ja) 2008-01-24
CN1977376A (zh) 2007-06-06
WO2005119768A1 (en) 2005-12-15
US20080280105A1 (en) 2008-11-13

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