CN100441074C - 多层集成电路封装 - Google Patents

多层集成电路封装 Download PDF

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Publication number
CN100441074C
CN100441074C CNB03811318XA CN03811318A CN100441074C CN 100441074 C CN100441074 C CN 100441074C CN B03811318X A CNB03811318X A CN B03811318XA CN 03811318 A CN03811318 A CN 03811318A CN 100441074 C CN100441074 C CN 100441074C
Authority
CN
China
Prior art keywords
layer
core layer
conductive region
built
metal core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB03811318XA
Other languages
English (en)
Chinese (zh)
Other versions
CN1653874A (zh
Inventor
博伊德·库马
迈克尔·沃克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1653874A publication Critical patent/CN1653874A/zh
Application granted granted Critical
Publication of CN100441074C publication Critical patent/CN100441074C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09554—Via connected to metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1142—Conversion of conductive material into insulating material or into dissolvable compound
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
CNB03811318XA 2002-03-29 2003-03-21 多层集成电路封装 Expired - Fee Related CN100441074C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/109,792 2002-03-29
US10/109,792 US6899815B2 (en) 2002-03-29 2002-03-29 Multi-layer integrated circuit package

Publications (2)

Publication Number Publication Date
CN1653874A CN1653874A (zh) 2005-08-10
CN100441074C true CN100441074C (zh) 2008-12-03

Family

ID=28453172

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB03811318XA Expired - Fee Related CN100441074C (zh) 2002-03-29 2003-03-21 多层集成电路封装

Country Status (8)

Country Link
US (2) US6899815B2 (https=)
EP (1) EP1491078B1 (https=)
CN (1) CN100441074C (https=)
AT (1) ATE472242T1 (https=)
AU (1) AU2003225932A1 (https=)
DE (1) DE60333084D1 (https=)
MY (1) MY132766A (https=)
WO (1) WO2003086038A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7368045B2 (en) * 2005-01-27 2008-05-06 International Business Machines Corporation Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow
JP5072283B2 (ja) * 2006-07-31 2012-11-14 三洋電機株式会社 回路基板
KR100815361B1 (ko) 2007-01-31 2008-03-19 삼성전기주식회사 인쇄회로기판의 제조방법
JP2009200338A (ja) * 2008-02-22 2009-09-03 Renesas Technology Corp 半導体装置の製造方法
JP2011014612A (ja) * 2009-06-30 2011-01-20 Ibiden Co Ltd 配線基板及び配線基板の製造方法
US8304863B2 (en) * 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
US8867219B2 (en) * 2011-01-14 2014-10-21 Harris Corporation Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices
KR102103375B1 (ko) 2013-06-18 2020-04-22 삼성전자주식회사 반도체 패키지
DE102014220650A1 (de) * 2014-10-13 2016-04-14 Heraeus Deutschland GmbH & Co. KG Optimiertes Leiterbahndesign von metallischen Materialien auf keramischen Substanzen
US9865527B1 (en) 2016-12-22 2018-01-09 Texas Instruments Incorporated Packaged semiconductor device having nanoparticle adhesion layer patterned into zones of electrical conductance and insulation
US9941194B1 (en) 2017-02-21 2018-04-10 Texas Instruments Incorporated Packaged semiconductor device having patterned conductance dual-material nanoparticle adhesion layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001015877A (ja) * 1999-06-30 2001-01-19 Mitsubishi Plastics Ind Ltd 金属ベースプリント配線板および金属ベース多層プリント配線板並びにその製造方法
JP2001320171A (ja) * 2000-05-08 2001-11-16 Shinko Electric Ind Co Ltd 多層配線基板及び半導体装置
US6328201B1 (en) * 1997-09-25 2001-12-11 Nitto Denko Corporation Multilayer wiring substrate and method for producing the same
US6335076B1 (en) * 1999-07-14 2002-01-01 Nitto Denko Corporation Multi-layer wiring board and method for manufacturing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4146440A (en) * 1978-04-03 1979-03-27 Burroughs Corporation Method for forming an aluminum interconnect structure on an integrated circuit chip
US5917157A (en) * 1994-12-12 1999-06-29 Remsburg; Ralph Multilayer wiring board laminate with enhanced thermal dissipation to dielectric substrate laminate
US6395582B1 (en) * 1997-07-14 2002-05-28 Signetics Methods for forming ground vias in semiconductor packages
US6326555B1 (en) * 1999-02-26 2001-12-04 Fujitsu Limited Method and structure of z-connected laminated substrate for high density electronic packaging
US6204089B1 (en) * 1999-05-14 2001-03-20 Industrial Technology Research Institute Method for forming flip chip package utilizing cone shaped bumps
EP1100295B1 (en) * 1999-11-12 2012-03-28 Panasonic Corporation Capacitor-mounted metal foil and a method for producing the same, and a circuit board and a method for producing the same
TWI226814B (en) * 1999-12-16 2005-01-11 Matsushita Electric Industrial Co Ltd A removable film, a substrate with film, a process for forming the removable film and a process for the manufacturing of the circuit board
US6585903B1 (en) * 2000-09-06 2003-07-01 Visteon Global Tech. Inc. Electrical circuit board and a method for making the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6328201B1 (en) * 1997-09-25 2001-12-11 Nitto Denko Corporation Multilayer wiring substrate and method for producing the same
JP2001015877A (ja) * 1999-06-30 2001-01-19 Mitsubishi Plastics Ind Ltd 金属ベースプリント配線板および金属ベース多層プリント配線板並びにその製造方法
US6335076B1 (en) * 1999-07-14 2002-01-01 Nitto Denko Corporation Multi-layer wiring board and method for manufacturing the same
JP2001320171A (ja) * 2000-05-08 2001-11-16 Shinko Electric Ind Co Ltd 多層配線基板及び半導体装置

Also Published As

Publication number Publication date
CN1653874A (zh) 2005-08-10
EP1491078B1 (en) 2010-06-23
MY132766A (en) 2007-10-31
US20050009353A1 (en) 2005-01-13
US20030184987A1 (en) 2003-10-02
DE60333084D1 (https=) 2010-08-05
ATE472242T1 (de) 2010-07-15
WO2003086038A1 (en) 2003-10-16
US6899815B2 (en) 2005-05-31
AU2003225932A1 (en) 2003-10-20
US7245001B2 (en) 2007-07-17
EP1491078A1 (en) 2004-12-29

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C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081203

Termination date: 20170321

CF01 Termination of patent right due to non-payment of annual fee