CN100390988C - 电子电路封装件中的互连 - Google Patents
电子电路封装件中的互连 Download PDFInfo
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Abstract
公开了一种RF微电路封装和互连线路设备,能够将电路元件之间的阻抗不匹配最小化。还公开了多条信号通路和邻近接地通路以及经调节的引线接合。
Description
本申请按照美国公司HEI,Inc.于2000年12月20递交的PCT国际专利申请(指定了除美国以外的所有国家)提出。
技术领域
本申请涉及组装微电子电路的“封装”技术,更具体而言,涉及在封装内的离散组件和基板之间传送和耦合RF信号的方法、技术和设备。
技术背景
微型电路电子产品一般是将单个组件组装进一个封装而组装成的。实际上,单个组件被挑选出来并放在基板上。基板可以是柔韧的聚合体膜层,也可以是坚硬的陶瓷片。基板可以有多层电路轨迹,各层之间通过通路在Z方向具有互连线路。有些组件可以用焊料或粘合剂等直接电子连接到基板上的焊盘。其它组件的焊盘不在基板表面的平面上。为了容纳这些焊盘的“高度”,使用了引线连接这种方法来传输位于不同平面的焊盘之间的信号。
例如,通常的做法一贯是将集成电路粘接或焊接到陶瓷基板上,然后用“引线接合”的方法在集成电路(IC)上的焊盘和基板上的焊盘之间做成电路互连线路。“引线接合”是一个小的电路回路,电流从IC上的焊盘流出,流过IC的边缘,然后回到基板的表面。在加工过程中,引线接合会迅速熔合在IC上,通常的产出量是每秒5个引线接合。通路和引线接合共同形成封装的可接受信号路径,只要有关的信号是“低频”信号。
但是,引线接合在低GHz范围内会衰减和辐射信号。导线本身有一个寄生电感,因此成为GHz范围内的一个重要电路元件。减少衰减的传统解决方法包括“楔形”接合和“带接合”。这两项技术着力减少导线的长度,从而减少“导线”的阻抗。
在楔形技术方法中,导线在焊盘外面形成锐角连接以使连接的总长度最小。可以每秒2-3个接合的速度加工这种连接。带接合用扁平带导线替代了引线接合中传统的圆形截面。带具有一个寄生电容,相对而言,该值大于电感,能够减少衰减。但是,成功的带引线接合严重依赖组件的布设。这一处理过程极其缓慢。
在基板本身上也存在类似的信号路线问题。在一个多层基板上,线性信号轨迹通常靠近零电位平面布置。因此,对于RF信号,使用公知的“带状线”技术,可以将信号路径设计为具有恒定的额定阻抗。但是,如果信号路径偏离带状线路径,并沿Z方向传送,则这种不对称性将由于相关的衰减和反射而产生阻抗的不匹配。陶瓷基板易碎,为了保证机械强度,需要在Z方向增加厚度,因而特别容易产生阻抗不匹配的问题。
因此,需要改进的互连线路设备和方法,以加工出高性能的高频电路“封装”。
发明内容
与现有技术相比,本发明提出了解决基板上阻抗不匹配问题的方法。根据本发明的原理,在基板接合片附近形成了一个电容。该电容与引线接合“导线”形成了一个谐振电路。该电路布局的功能类似具有额定特性阻抗的传输线,耦合信号时减少了反射能量和辐射能量的衰减和抑制。
在本发明的第二方面,提供了两个或多个通路以在Z方向传输RF信号。工作时,平行通路的耦合阻抗形成信号的传输线。在另一种形式中,在信号通路旁设置接地通路,以形成类似传输线的连接。这些不同的原理可以单独使用或组合使用以制成高性能的封装。
使用这些技术构造的封装有如下优点。低损耗连接允许重新划分RF信号处理元件以实现低成本或高性能。例如,缺少“理想”的互连线路技术会迫使人们使用集成电路元件,这种情况下,如果利用本发明,就可以使用离散的电路元件,而不使用集成电路元件。该连接方法还允许进行组件布设,从而降低加工成本。这些技术还允许使用低成本的常规加工设备来加工高性能的RF封装,这一点也意味着成本的降低。
附图说明
结合如下附图,在几个说明性的实施例中,对本发明的各个方面和功能进行描述,其中:
图1是使用本发明各个方面的封装的截面图;
图2是使用本发明某些方面的封装的平面图;
图3显示对原型封装进行回波损耗测试的结果;
图4显示对原型封装进行介入损耗测试的结果;
图5显示了使用分层基板的封装的性能。
优选实施例的详细说明
本申请公开的内容基于性能测试,为了阐述公开的内容,对测试方法进行简短的说明。一般而言,进行测试的装置带有一个RF输入端口和一个RF输出端口。进入电路的射频功率作为一个整体,并将输出功率与输入功率进行比较以测量“介入损耗”。“介入损耗”低对应于性能好。由于阻抗不匹配而导致的反射能量也会使性能降低。这一参数用回波损耗来度量。回波损耗的测量结果一般为负数,因此,回波损耗越高,性能越好。
回波损耗和介入损耗的测量结果是频率的函数,通常都是对应频率进行绘制。对于提供宽带的新的数字电话技术而言,尤其需要宽带上的性能。
图1所示为封装30的截面。箭头9表示本图的Z轴。该封装包括基板16,可以是陶瓷的,也可以是聚合体膜,并且一般都分为几层电路。为清楚起见,图中所示的基板16为只有一层的结构。对于微波的常见情况,基板的下表面是由基板16上的铜层形成的零电位平面18。由轨迹20和零电位平面18所形成的传输线在此基板16上形成一条信号轨迹。在现有技术中,对于任何给定的基板材料和介电常数,可以方便地计算出轨迹20的精确宽度。轨迹20从基板24下表面上的轨迹28下面穿过并与轨迹28接合。在一个一般构造中,陶瓷基板24可以带有几个集成电路,也可以带有其他与陶瓷或聚合体膜分层基板16连接的离散组件,从而做成一个产品。
在图1所示的构造中,基板24由有多条通路将零电位平面引到集成电路22的下面。第一信号通路14和第二通路15(见图2)一起形成了一个Z方向的信号路径,用来将信号从传输线20传到基板24上表面上的键合区12。与现有技术结构相比,RF信号被分成图1和图2中的通路14和通路15。第一信号通路14和第二信号通路的位置靠近接地通路17。这两条信号通路和附带的接地通路一起,在传输线20和键合焊盘12之间的Z方向上形成恒定阻抗连接。显然可以用一个以上的其他接地通路或信号通路来获得阻抗匹配特性。
在图1中,导线10的接合形成键合焊盘12到端口2连接的电信号路径连接,以完整地描述测试封装30。
图2所示为图1布局的平面图。箭头11表示该构造的X-Y轴。信号从端口1,经过轨迹20和零电位平面18(未示出)形成的传输线连接进入测试封装30。该传输线20与轨迹28连接。连接轨迹28在图中以部分剖面图示出。该连接轨迹28与第一信号通路14和第二信号通路15连接。每个通路用一个圆圈表示,通路14和通路15之间的距离表示为间距32。该间距的大小可用来“调节”信号通路14和15的传输线特征。
在图2中,在基板24的上表面,键合焊盘12的宽度用标记为36的夸大的宽度来表示。该扩展的键合焊盘相对于基板22和基板24的零电位平面具有电容。正是焊盘的电容在“调节”导线10的电感以产生特性设计阻抗。尽管图中将该焊盘表示为在Y方向展开形成了一个T形连接,应该理解也可以形成其他形状,而且在某些特定情况下,可能更需要其他形状。许多RF集成电路都有这样一个特点,即互连线路的密度低,因而可以将通路的外边用做这种结构。还应注意的是,T形状利用了大多数集成电路的基板或下端靠近零电位平面的优点。对应的电路是一个电感导线和接地端间的电容,在信号路径中形成了一个带通滤波器。
对于信号通路15和信号通路14之间的间距32,应该理解,建立所需要的特性阻抗的准确间距取决于基板24和16的介电常数,以及其他接地特征的邻近性。因此,在给出特定封装设计时,可能需要多个信号通路。第一信号通路14和第二信号通路15的形状和位置是说明性的,不起限定作用。与此类似,作为补充信号通路14和15的接地通路17,其位置可用来“调节”连接。由于与其他杂散电容邻近以及与其他接地结构邻近,不存在精确的对应关系。
在各种测试中,RF信号从端口1进入,从端口2流出。在端口2的可用功率取决于端口1和端口2之间各种连接的质量,并且测试过程测得两个端口之间的“回波损耗”和“介入损耗”。一般来讲,在复合测试封装上对图1和图2中所示的两种布局进行了检测,并求出这些检测的平均值。优选情况下,使用填加有聚四氟乙烯的陶瓷作为基板,因为这种材料的介电常数高,能改进本发明技术方法的性能。
图3将所测得的封装回波损耗显示为曲线26。将这一性能与该图中标号为27的未使用本发明的相似的封装进行比较。为进行比较,用-15dB曲线29划分性能范围。一般而言,如果回波损耗高于-15dB,信号将退化从而使封装无法使用。本发明中,封装在36GHz附近才会达到-15dB。相比之下,常规技术在13GHz就会达到-15dB。因此,本发明的封装能够在高频范围工作。还应该注意的重要一点是,高频率范围是宽带的使用要求。
图4所示为封装的介入损耗特性。曲线33代表使用本发明的测试封装,曲线31代表常规技术的结果。曲线33在40GHz左右之前,一直在曲线31上方,表明该封装的介入损耗较低。一定要注意,该图表示本发明的毫米波长封装对带外噪声的衰减要大于常规封装。通带中的介入损耗低,同时对通带外能量的衰减提高,这一点在诸如蜂窝电话等的高性能通信产品中特别有用。
图5所示为使用分层基板,并且基板材料为填加有聚四氟乙烯的陶瓷的测试封装的测试结果。该图中,用曲线35表示的封装在50GHz的毫米波长范围内具有更高级的性能。
本文所讲述的本发明的各种实施例一起形成一个高性能的RF封装。但是,在不背离本发明范围的前提下,每个方案都可以单独使用,也可以与其他技术组合使用。在不背离本发明范围的前提下,显然可以对本发明进行其他修改。
Claims (10)
1.一种电子电路封装件中的互连,用在电子电路封装件的第一层上的第一焊盘和电子电路封装件的第二层上的第二焊盘之间,包括:
从所述第一焊盘伸向所述第二焊盘的导线,所述导线具有一定的电感值,并形成信号路径的至少一部分;
一个电容,其与所述信号路径电气通信,并被布置得并联所述信号路径,所述电容具有一定的电容值,所述电容值和电感值给由所述导线组成的所述信号路径提供了一个设计带宽上的设计的特性阻抗,其中,在所述设计带宽内的一些频率上,所述设计的特性阻抗值与所述信号路径的至少另一个部分的阻抗值相匹配。
2.根据权利要求1的电子电路封装件中的互连,其特征在于,使用从主要由楔连接和带连接组成的组中所选择的接合,将所述导线与第一或第二焊盘中的至少一个接合。
3.根据权利要求1的电子电路封装件中的互连,其特征在于,所述导线的截面是圆形的。
4.根据权利要求1的电子电路封装件中的互连,其特征在于,所述电容是一个扩展面积的焊盘。
5.根据权利要求4的电子电路封装件中的互连,其特征在于,所述扩展面积的焊盘在X-Y平面上具有扩展的宽度。
6.根据权利要求1的电子电路封装件中的互连,其特征在于,所述导线的截面是矩形的。
7.根据权利要求1的电子电路封装件中的互连,进一步包括:
一个基板,具有一个介电常数、一个由所述第一层形成的第一面和一个第二面,所述第一面与所述第二面相对布置,所述第一焊盘在所述基板的所述第一面上形成;以及
一个零电位平面,在所述基板的第二面上形成,其中,由所述第一焊盘和所述零电位平面形成所述电容器。
8.根据权利要求7的电子电路封装件中的互连,其特征在于,所述基板材料是填加有聚四氟乙烯的陶瓷。
9.根据权利要求7的电子电路封装件中的互连,其特征在于,
所述设计带宽至少包括不小于30GHz的频率;以及
对于所述设计带宽内的频率,所述信号路径的所述第一部分和第二部分之间的回波损耗小于-15dB。
10.根据权利要求1的电子电路封装件中的互连,其特征在于,所述导线是一条带。
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US09/477,048 US6294966B1 (en) | 1999-12-31 | 1999-12-31 | Interconnection device |
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Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6294966B1 (en) * | 1999-12-31 | 2001-09-25 | Hei, Inc. | Interconnection device |
US6646521B1 (en) * | 2000-09-15 | 2003-11-11 | Hei, Inc. | Connection for conducting high frequency signal between a circuit and a discrete electric component |
CA2390627C (en) * | 2001-06-18 | 2007-01-30 | Research In Motion Limited | Ic chip packaging for reducing bond wire length |
US6737931B2 (en) * | 2002-07-19 | 2004-05-18 | Agilent Technologies, Inc. | Device interconnects and methods of making the same |
WO2004075336A1 (ja) * | 2003-02-21 | 2004-09-02 | Matsushita Electric Industrial Co., Ltd. | 高周波回路 |
US7239207B2 (en) * | 2003-08-20 | 2007-07-03 | Intel Corporation | Transimpedance amplifier |
US7187256B2 (en) * | 2004-02-19 | 2007-03-06 | Hittite Microwave Corporation | RF package |
US7105918B2 (en) * | 2004-07-29 | 2006-09-12 | Micron Technology, Inc. | Interposer with flexible solder pad elements and methods of manufacturing the same |
US7187249B2 (en) * | 2004-09-24 | 2007-03-06 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Interconnecting a port of a microwave circuit package and a microwave component mounted in the microwave circuit package |
US20070035019A1 (en) * | 2005-08-15 | 2007-02-15 | Semiconductor Components Industries, Llc. | Semiconductor component and method of manufacture |
WO2007032966A1 (en) * | 2005-09-12 | 2007-03-22 | Sealed Air Corporation (Us) | Flexible valves |
US7295084B2 (en) * | 2005-09-28 | 2007-11-13 | Agilent Technologies, Inc. | Electrical interconnection for coaxial line to slab line structure including a bead ring |
CN100411400C (zh) * | 2006-04-06 | 2008-08-13 | 华为技术有限公司 | 一种阻抗调节装置和包含该装置的通信系统 |
US9713258B2 (en) * | 2006-04-27 | 2017-07-18 | International Business Machines Corporation | Integrated circuit chip packaging |
US20080218979A1 (en) * | 2007-03-08 | 2008-09-11 | Jong-Ho Park | Printed circuit (PC) board module with improved heat radiation efficiency |
DE102007046728B4 (de) * | 2007-09-28 | 2013-08-22 | Epcos Ag | Elektrisches Bauelement |
KR101463074B1 (ko) * | 2008-01-10 | 2014-11-21 | 페어차일드코리아반도체 주식회사 | 리드리스 패키지 |
US9069418B2 (en) * | 2008-06-06 | 2015-06-30 | Apple Inc. | High resistivity metal fan out |
US8107177B2 (en) * | 2008-12-23 | 2012-01-31 | Hitachi Global Storage Technologies Netherlands B.V. | Electrical interconnect system with integrated transmission- line compensation components |
JP2011077841A (ja) * | 2009-09-30 | 2011-04-14 | Renesas Electronics Corp | 電子装置 |
US8791767B2 (en) | 2010-10-29 | 2014-07-29 | Qualcomm Incorporated | Package inductance compensating tunable capacitor circuit |
CN102623777B (zh) * | 2011-01-27 | 2014-06-18 | 鸿富锦精密工业(深圳)有限公司 | 低通滤波器 |
CN103503133B (zh) * | 2011-03-03 | 2016-09-28 | 天工方案公司 | 与线焊盘有关且降低高rf损耗镀覆影响的设备和方法 |
US20150282299A1 (en) * | 2014-04-01 | 2015-10-01 | Xilinx, Inc. | Thin profile metal trace to suppress skin effect and extend package interconnect bandwidth |
TWI557752B (zh) * | 2015-02-25 | 2016-11-11 | 緯創資通股份有限公司 | 排線結構 |
CN106129029A (zh) * | 2016-07-14 | 2016-11-16 | 中国电子科技集团公司第五十五研究所 | 应用于Ku波段的陶瓷四边扁平无引脚型外壳 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0718905A1 (en) * | 1994-12-21 | 1996-06-26 | Industrial Technology Research Institute | Surface mountable microwave IC package |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0793392B2 (ja) | 1986-10-25 | 1995-10-09 | 新光電気工業株式会社 | 超高周波素子用パツケ−ジ |
JPS63124102A (ja) | 1986-11-14 | 1988-05-27 | Hitachi Ltd | 冗長化システムの縮退運転方法 |
FR2684804B1 (fr) | 1991-12-06 | 1994-01-28 | Thomson Csf | Dispositif de montage de circuits integres monolithiques hyperfrequences a tres large bande. |
JPH07221223A (ja) * | 1994-02-03 | 1995-08-18 | Mitsubishi Electric Corp | 半導体装置,及び混成集積回路装置 |
JPH0897611A (ja) * | 1994-09-22 | 1996-04-12 | Nippon Telegr & Teleph Corp <Ntt> | 高周波伝送線路およびマイクロ波回路 |
US5583468A (en) * | 1995-04-03 | 1996-12-10 | Motorola, Inc. | High frequency transition from a microstrip transmission line to an MMIC coplanar waveguide |
US6175287B1 (en) * | 1997-05-28 | 2001-01-16 | Raytheon Company | Direct backside interconnect for multiple chip assemblies |
WO1999027646A1 (en) | 1997-11-21 | 1999-06-03 | Hitachi, Ltd. | High-frequency amplifier circuit device and high-frequency transmission system using the same |
US5982250A (en) * | 1997-11-26 | 1999-11-09 | Twr Inc. | Millimeter-wave LTCC package |
US6118357A (en) * | 1999-02-15 | 2000-09-12 | Trw Inc. | Wireless MMIC chip packaging for microwave and millimeterwave frequencies |
US6201454B1 (en) | 1999-03-30 | 2001-03-13 | The Whitaker Corporation | Compensation structure for a bond wire at high frequency operation |
US6294966B1 (en) * | 1999-12-31 | 2001-09-25 | Hei, Inc. | Interconnection device |
-
1999
- 1999-12-31 US US09/477,048 patent/US6294966B1/en not_active Expired - Lifetime
-
2000
- 2000-12-20 AU AU22854/01A patent/AU2285401A/en not_active Abandoned
- 2000-12-20 JP JP2001550811A patent/JP2003519925A/ja active Pending
- 2000-12-20 WO PCT/US2000/034805 patent/WO2001050531A1/en active Application Filing
- 2000-12-20 CN CNB008186499A patent/CN100390988C/zh not_active Expired - Fee Related
- 2000-12-20 EP EP00986661A patent/EP1245046A1/en not_active Withdrawn
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-
2001
- 2001-09-24 US US09/961,627 patent/US6469592B2/en not_active Expired - Fee Related
-
2002
- 2002-08-26 US US10/228,587 patent/US6838953B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0718905A1 (en) * | 1994-12-21 | 1996-06-26 | Industrial Technology Research Institute | Surface mountable microwave IC package |
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