CN100381834C - 用于安全扫描测试的方法和装置 - Google Patents

用于安全扫描测试的方法和装置 Download PDF

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Publication number
CN100381834C
CN100381834C CNB038099357A CN03809935A CN100381834C CN 100381834 C CN100381834 C CN 100381834C CN B038099357 A CNB038099357 A CN B038099357A CN 03809935 A CN03809935 A CN 03809935A CN 100381834 C CN100381834 C CN 100381834C
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China
Prior art keywords
scan
scanning
signal
information
processor
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Expired - Fee Related
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CNB038099357A
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English (en)
Chinese (zh)
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CN1650183A (zh
Inventor
托马斯·特卡奇克
约翰·E·小斯皮塔尔
乔纳森·卢茨
劳伦斯·卡塞
道格拉斯·哈迪
马克·雷德曼
格雷戈里·施密特
斯蒂芬·图格博格
迈克尔·D·菲茨西蒙斯
达雷尔·L·卡德尔
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN1650183A publication Critical patent/CN1650183A/zh
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Publication of CN100381834C publication Critical patent/CN100381834C/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Storage Device Security (AREA)
CNB038099357A 2002-04-30 2003-04-14 用于安全扫描测试的方法和装置 Expired - Fee Related CN100381834C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/135,877 US7185249B2 (en) 2002-04-30 2002-04-30 Method and apparatus for secure scan testing
US10/135,877 2002-04-30

Publications (2)

Publication Number Publication Date
CN1650183A CN1650183A (zh) 2005-08-03
CN100381834C true CN100381834C (zh) 2008-04-16

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CNB038099357A Expired - Fee Related CN100381834C (zh) 2002-04-30 2003-04-14 用于安全扫描测试的方法和装置

Country Status (9)

Country Link
US (2) US7185249B2 (cg-RX-API-DMAC7.html)
EP (1) EP1499906B1 (cg-RX-API-DMAC7.html)
JP (1) JP2006505798A (cg-RX-API-DMAC7.html)
KR (1) KR100966661B1 (cg-RX-API-DMAC7.html)
CN (1) CN100381834C (cg-RX-API-DMAC7.html)
AU (1) AU2003224959A1 (cg-RX-API-DMAC7.html)
DE (1) DE60303126T2 (cg-RX-API-DMAC7.html)
TW (1) TWI270768B (cg-RX-API-DMAC7.html)
WO (1) WO2004051294A1 (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108351380A (zh) * 2015-10-29 2018-07-31 北欧半导体公司 微处理器接口

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7228440B1 (en) * 2002-02-13 2007-06-05 Lsi Corporation Scan and boundary scan disable mechanism on secure device
US7672452B2 (en) * 2002-05-03 2010-03-02 General Instrument Corporation Secure scan
CN100559203C (zh) * 2003-09-19 2009-11-11 Nxp股份有限公司 包括秘密的子模块的电子电路
TWI229741B (en) * 2004-01-16 2005-03-21 Sunplus Technology Co Ltd Device and method for accessing hidden data in boundary scan test interface
TWI235599B (en) * 2004-01-16 2005-07-01 Sunplus Technology Co Ltd Device and method for transmitting hidden signal in boundary scan testing interface
FR2865827A1 (fr) * 2004-01-29 2005-08-05 St Microelectronics Sa Securisation du mode de test d'un circuit integre
EP1560033A1 (fr) * 2004-01-29 2005-08-03 STMicroelectronics S.A. Circuit intégré comportant un mode de test sécurisé par initialisation du dit mode de test
FR2865828A1 (fr) * 2004-01-29 2005-08-05 St Microelectronics Sa Procede de securisation du mode de test d'un circuit integre par detection d'intrusion
US7490231B2 (en) * 2004-07-23 2009-02-10 Broadcom Corporation Method and system for blocking data in scan registers from being shifted out of a device
US7290191B2 (en) * 2004-08-20 2007-10-30 International Business Machines Corporation Functional frequency testing of integrated circuits
US8379861B2 (en) * 2004-11-22 2013-02-19 Freescale Semiconductor, Inc. Integrated circuit and a method for secure testing
FR2883998A1 (fr) * 2005-04-05 2006-10-06 St Microelectronics Sa Coprocesseur securise comprenant un circuit de detection d'un evenement
US7519883B1 (en) * 2005-04-05 2009-04-14 Advanced Micro Devices, Inc. Method of configuring a system and system therefor
FR2884000A1 (fr) * 2005-04-05 2006-10-06 St Microelectronics Sa Coprocesseur securise comprenant des moyens pour empecher l'acces a un organe du coprocesseur
FR2885417A1 (fr) * 2005-05-04 2006-11-10 St Microelectronics Sa Circuit integre comportant un mode de test securise par detection de l'etat chaine des cellules configurables du circuit integre
US7600166B1 (en) * 2005-06-28 2009-10-06 David Dunn Method and system for providing trusted access to a JTAG scan interface in a microprocessor
US7334173B2 (en) * 2005-06-28 2008-02-19 Transmeta Corporation Method and system for protecting processors from unauthorized debug access
US7694197B2 (en) * 2005-07-08 2010-04-06 Stmicroelectronics, Sa Integrated circuit comprising a test mode secured by detection of the state of a control signal
FR2888330B1 (fr) * 2005-07-08 2007-10-05 St Microelectronics Sa Circuit integre comportant un mode de test securise par detection de l'etat d'un signal de commande
US7363564B2 (en) * 2005-07-15 2008-04-22 Seagate Technology Llc Method and apparatus for securing communications ports in an electronic device
DE602006014417D1 (de) * 2005-08-10 2010-07-01 Nxp Bv Prüfen einer integrierten schaltung, die geheiminformationen enthält
US7328384B1 (en) * 2005-09-29 2008-02-05 Xilinx, Inc. Method and apparatus using device defects as an identifier
JP2007171060A (ja) * 2005-12-23 2007-07-05 Toshiba Corp 動作モード設定回路、動作モード設定回路を有するｌｓｉ、及び動作モード設定方法
FR2897440A1 (fr) * 2006-02-10 2007-08-17 St Microelectronics Sa Circuit electronique comprenant un mode de test securise par rupture d'une chaine de test, et procede associe.
US7779252B2 (en) * 2006-03-21 2010-08-17 Harris Corporation Computer architecture for a handheld electronic device with a shared human-machine interface
US8127145B2 (en) * 2006-03-23 2012-02-28 Harris Corporation Computer architecture for an electronic device providing a secure file system
US8041947B2 (en) * 2006-03-23 2011-10-18 Harris Corporation Computer architecture for an electronic device providing SLS access to MLS file system with trusted loading and protection of program execution memory
US8060744B2 (en) * 2006-03-23 2011-11-15 Harris Corporation Computer architecture for an electronic device providing single-level secure access to multi-level secure file system
US7979714B2 (en) * 2006-06-02 2011-07-12 Harris Corporation Authentication and access control device
JP4262265B2 (ja) * 2006-06-20 2009-05-13 キヤノン株式会社 半導体集積回路
FR2903497A1 (fr) * 2006-07-07 2008-01-11 St Microelectronics Sa Circuit electronique comprenant un mode de test securise par insertion de donnees leurres dans la chaine de test,procede associe.
CN100495989C (zh) * 2006-07-07 2009-06-03 中国科学院计算技术研究所 一种测试外壳电路及其设计方法
US8528102B2 (en) * 2006-10-06 2013-09-03 Broadcom Corporation Method and system for protection of customer secrets in a secure reprogrammable system
US7869915B2 (en) * 2007-04-12 2011-01-11 GM Global Technology Operations LLC Method and apparatus for validating processors using seed and key tests
US9111122B2 (en) * 2007-07-02 2015-08-18 Freescale Semiconductor, Inc. Asymmetric cryptographic device with local private key generation and method therefor
US7975307B2 (en) * 2007-09-07 2011-07-05 Freescale Semiconductor, Inc. Securing proprietary functions from scan access
US7987331B2 (en) * 2007-11-15 2011-07-26 Infineon Technologies Ag Method and circuit for protection of sensitive data in scan mode
US8051345B2 (en) * 2008-06-04 2011-11-01 Ati Technologies Ulc Method and apparatus for securing digital information on an integrated circuit during test operating modes
US8397079B2 (en) * 2008-06-04 2013-03-12 Ati Technologies Ulc Method and apparatus for securing digital information on an integrated circuit read only memory during test operating modes
EP2146213B1 (en) * 2008-07-14 2011-08-17 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Integrated circuit, method and electronic apparatus
CN102112889A (zh) * 2008-08-08 2011-06-29 Nxp股份有限公司 具有耦接至特权信息提供电路的可测试电路的电路
US8074132B2 (en) * 2008-10-28 2011-12-06 Broadcom Corporation Protecting data on integrated circuit
JP2010252305A (ja) * 2009-03-25 2010-11-04 Renesas Electronics Corp 半導体集積回路及びその制御方法
JP2010261768A (ja) * 2009-05-01 2010-11-18 Sony Corp 半導体集積回路、情報処理装置、および出力データ拡散方法、並びにプログラム
JP2010266417A (ja) * 2009-05-18 2010-11-25 Sony Corp 半導体集積回路、情報処理装置、および情報処理方法、並びにプログラム
US9009552B2 (en) * 2010-09-09 2015-04-14 Advanced Micro Devices, Inc. Scan-based reset
CN102565684A (zh) * 2010-12-13 2012-07-11 上海华虹集成电路有限责任公司 基于安全的扫描链控制电路、扫描链测试电路及使用方法
US9746519B2 (en) * 2011-03-25 2017-08-29 Nxp B.V. Circuit for securing scan chain data
US8495443B1 (en) 2011-05-31 2013-07-23 Apple Inc. Secure register scan bypass
JP5793978B2 (ja) * 2011-06-13 2015-10-14 富士通セミコンダクター株式会社 半導体装置
US9465755B2 (en) 2011-07-18 2016-10-11 Hewlett Packard Enterprise Development Lp Security parameter zeroization
US9373377B2 (en) 2011-11-15 2016-06-21 Micron Technology, Inc. Apparatuses, integrated circuits, and methods for testmode security systems
US9224012B2 (en) * 2013-05-20 2015-12-29 Advanced Micro Devices, Inc. Debug functionality in a secure computing environment
US9310436B2 (en) * 2014-01-28 2016-04-12 Omnivision Technologies, Inc. System and method for scan-testing of idle functional units in operating systems
CN106556792B (zh) * 2015-09-28 2021-03-19 恩智浦美国有限公司 能够进行安全扫描的集成电路
US10185633B2 (en) * 2015-12-15 2019-01-22 Intel Corporation Processor state integrity protection using hash verification
EP3430627B1 (en) * 2016-03-16 2022-01-12 Hewlett-Packard Development Company, L.P. Controlling a transition between a functional mode and a test mode
CN107783030B (zh) * 2016-08-29 2021-04-23 恩智浦美国有限公司 具有低功率扫描系统的集成电路
CN108073832B (zh) * 2016-11-15 2021-06-29 华为技术有限公司 一种数据安全保护方法及设备
US10222417B1 (en) * 2016-11-28 2019-03-05 Cadence Design Systems, Inc. Securing access to integrated circuit scan mode and data
US10223531B2 (en) 2016-12-30 2019-03-05 Google Llc Secure device state apparatus and method and lifecycle management
CN106707139B (zh) * 2017-01-03 2019-06-04 大唐微电子技术有限公司 一种扫描链测试装置及实现方法
KR102220662B1 (ko) * 2018-01-05 2021-03-17 주식회사 아이씨티케이 홀딩스 테스트 모드에서 데이터 보호 장치 및 방법
US11222098B2 (en) * 2018-08-23 2022-01-11 University Of Florida Research Foundation, Incorporated Protecting obfuscated circuits against attacks that utilize test infrastructures
US10984108B2 (en) 2018-10-05 2021-04-20 International Business Machines Corporation Trusted computing attestation of system validation state
US10976366B2 (en) * 2018-10-19 2021-04-13 Silicon Laboratories Inc. Two pin scan interface for low pin count devices
CN110020558A (zh) * 2019-04-09 2019-07-16 长沙理工大学 边界扫描设计环境下一种安全的密码芯片可测试性设计结构
TWI727308B (zh) * 2019-04-17 2021-05-11 國立成功大學 測試電路之動態密鑰防禦架構與方法
US11144677B2 (en) * 2019-08-08 2021-10-12 Nxp Usa, Inc. Method and apparatus for digital only secure test mode entry
KR20220062501A (ko) * 2019-09-12 2022-05-17 핑거프린트 카드즈 아나카툼 아이피 에이비 암호화 회로가 있는 생체 인식 장치
US10955473B1 (en) 2019-11-01 2021-03-23 Nxp B.V. System and method of scan reset upon entering scan mode
US11320482B2 (en) 2020-02-26 2022-05-03 Silicon Laboratories Inc. Secure scan entry
EP3893008A1 (en) * 2020-04-07 2021-10-13 Commsolid GmbH Method and apparatus for performing a secure test mode of a soc
WO2022235747A1 (en) * 2021-05-04 2022-11-10 Texas Instruments Incorporated Methods and apparatus for using scan operations to protect secure assets
US20220358230A1 (en) * 2021-05-04 2022-11-10 Texas Instruments Incorporated Methods and apparatus for using scan operations to protect secure assets
US11454671B1 (en) * 2021-06-30 2022-09-27 Apple Inc. Data gating using scan enable pin
US11953548B2 (en) * 2022-01-14 2024-04-09 University Of Florida Research Foundation, Incorporated Invisible scan architecture for secure testing of digital designs
KR20240130440A (ko) 2023-02-22 2024-08-29 연세대학교 산학협력단 스캔 체인 보안 회로 및 그 구동 방법
CN117521168A (zh) * 2023-11-20 2024-02-06 海光云芯集成电路设计(上海)有限公司 芯片、芯片的信息安全保护方法及电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347523A (en) * 1992-03-02 1994-09-13 Motorola, Inc. Data processing system having serial self address decoding and method of operation
US5530749A (en) * 1994-08-15 1996-06-25 International Business Machines Corporation Methods and apparatus for secure hardware configuration
US5898776A (en) * 1996-11-21 1999-04-27 Quicklogic Corporation Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0827730B2 (ja) * 1986-11-07 1996-03-21 沖電気工業株式会社 シングルチップマイクロコンピュータ及びそのテスト方法
US4925353A (en) 1987-05-28 1990-05-15 Litton Systems, Inc. Drive fastening system
JPH01118933A (ja) * 1987-10-31 1989-05-11 Nec Corp シングルチップマイクロコンピュータ
US4947357A (en) * 1988-02-24 1990-08-07 Stellar Computer, Inc. Scan testing a digital system using scan chains in integrated circuits
JPH01307815A (ja) * 1988-06-07 1989-12-12 Mitsubishi Electric Corp 情報処理装置のリセット方式
JPH0325688A (ja) * 1989-06-23 1991-02-04 Nec Corp マイクロコンピュータ
JPH04256145A (ja) * 1991-02-08 1992-09-10 Sharp Corp 集積回路装置
JPH0512459A (ja) * 1991-07-05 1993-01-22 Nec Corp シングルチツプマイクロコンピユータ
US5627842A (en) * 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
GB2290877B (en) * 1994-07-01 1997-08-20 Advanced Risc Mach Ltd Integrated circuit test controller
GB9414266D0 (en) * 1994-07-14 1994-08-31 Jonhig Ltd Testing of memory content
KR0147619B1 (ko) * 1995-01-27 1998-12-01 김광호 플립플롭 제어기
JP3670449B2 (ja) * 1997-07-09 2005-07-13 株式会社東芝 半導体装置
US6049901A (en) 1997-09-16 2000-04-11 Stock; Mary C. Test system for integrated circuits using a single memory for both the parallel and scan modes of testing
US6061010A (en) * 1997-09-25 2000-05-09 Analog Devices, Inc. Dual return-to-zero pulse encoding in a DAC output stage
JP3638770B2 (ja) * 1997-12-05 2005-04-13 東京エレクトロンデバイス株式会社 テスト機能を備える記憶装置
JPH11282671A (ja) 1998-03-31 1999-10-15 Texas Instr Japan Ltd コンピュータシステム
US6425100B1 (en) * 1998-04-24 2002-07-23 Texas Instruments Incorporated Snoopy test access port architecture for electronic circuits including embedded core with built-in test access port
US6304099B1 (en) * 1998-05-21 2001-10-16 Lattice Semiconductor Corporation Method and structure for dynamic in-system programming
US6216251B1 (en) * 1999-04-30 2001-04-10 Motorola Inc On-chip error detection and correction system for an embedded non-volatile memory array and method of operation
US6499124B1 (en) * 1999-05-06 2002-12-24 Xilinx, Inc. Intest security circuit for boundary-scan architecture
JP4294159B2 (ja) * 1999-05-06 2009-07-08 株式会社ルネサステクノロジ 半導体集積回路装置
EP1087233A1 (de) * 1999-09-23 2001-03-28 Infineon Technologies AG Verfahren und Anordnung zum datenschützenden Selbsttest für Microcontroller
US6754862B1 (en) * 2000-03-09 2004-06-22 Altera Corporation Gaining access to internal nodes in a PLD
KR100381959B1 (ko) * 2000-08-31 2003-05-01 삼성전자주식회사 테스트 포인트가 삽입된 반도체 집적회로 장치
FR2822971A1 (fr) * 2001-04-03 2002-10-04 St Microelectronics Sa Systeme et procede de controle d'acces a des donnees protegees stockees dans une memoire
EP1248200A1 (de) * 2001-04-06 2002-10-09 Micronas GmbH Verriegelungsschaltung zur Verhinderung eines unzulässigen Zugriffs auf die Speichereinrichtung eines Prozessors
US6954886B2 (en) * 2001-12-31 2005-10-11 Intel Corporation Deterministic hardware reset for FRC machine
US7386774B1 (en) * 2004-02-26 2008-06-10 Integrated Device Technology, Inc. Memory unit with controller managing memory access through JTAG and CPU interfaces
US7328384B1 (en) * 2005-09-29 2008-02-05 Xilinx, Inc. Method and apparatus using device defects as an identifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347523A (en) * 1992-03-02 1994-09-13 Motorola, Inc. Data processing system having serial self address decoding and method of operation
US5530749A (en) * 1994-08-15 1996-06-25 International Business Machines Corporation Methods and apparatus for secure hardware configuration
US5898776A (en) * 1996-11-21 1999-04-27 Quicklogic Corporation Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108351380A (zh) * 2015-10-29 2018-07-31 北欧半导体公司 微处理器接口

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AU2003224959A1 (en) 2004-06-23
JP2006505798A (ja) 2006-02-16
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US20030204801A1 (en) 2003-10-30
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US7725788B2 (en) 2010-05-25
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US7185249B2 (en) 2007-02-27
US20070226562A1 (en) 2007-09-27
CN1650183A (zh) 2005-08-03
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