CN100380603C - 制造纳米线的方法、纳米线和电子装置 - Google Patents

制造纳米线的方法、纳米线和电子装置 Download PDF

Info

Publication number
CN100380603C
CN100380603C CNB038071436A CN03807143A CN100380603C CN 100380603 C CN100380603 C CN 100380603C CN B038071436 A CNB038071436 A CN B038071436A CN 03807143 A CN03807143 A CN 03807143A CN 100380603 C CN100380603 C CN 100380603C
Authority
CN
China
Prior art keywords
nano wire
layer
district
semiconductor substrate
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB038071436A
Other languages
English (en)
Other versions
CN1643661A (zh
Inventor
E·P·A·M·巴克斯
F·鲁泽布姆
J·F·C·M·维霍文
P·范德斯鲁伊斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of CN1643661A publication Critical patent/CN1643661A/zh
Application granted granted Critical
Publication of CN100380603C publication Critical patent/CN100380603C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122—Single quantum well structures
    • H01L29/125—Quantum wire structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Plasma & Fusion (AREA)
  • Thin Film Transistor (AREA)
  • Led Devices (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)

Abstract

本发明公开一种纳米线制造方法，包括以下步骤：在半导体衬底的表面提供构图的刻蚀掩模，以及沿垂直于该半导体衬底表面的方向刻蚀该半导体衬底以形成纳米线，其中该半导体衬底包括第一材料的第一层、第二材料的第二层和第三材料的第三层，这些层相互邻接；第二层夹在第一层和第三层之间，并具有至多100nm的厚度，以及刻蚀穿过第一层、第二层和第三层以用于形成纳米线，使得该纳米线包括第一材料的第一区、第二材料的第二区和包含第三材料的第三区。在所得纳米线中，界面是非常地明显。因此在第一和第二电极之间具有纳米线的电子装置具有很好的电致发光和光电特性。

Description

制造纳米线的方法、纳米线和电子装置
技术领域
本发明通常涉及的是纳米线领域，具体涉及的是纳米线的制造方法、使用所述方法制造的纳米线以及具有这种纳米线的电子装置。
背景技术
纳米线为通常由半导电的材料制成的直径小于100nm的线。这些线被认为是未来的电子和光电元件的构建模块。纳米线具有光刻构图造成的尺寸限制变得不太相关的优点。此外，因为量子效应，例如非欧姆电阻，纳米线与具有更大尺寸的相同材料的单元在性质上不同。
从Liu等人J.Vac.Sci.Technol.B，11(1993)，2532-2537中可以了解开始段落中介绍的方法。在已知的方法中，借助电子束光刻在刻蚀的掩模中定义出图形。借助反应离子刻蚀将该图形转移到半导体衬底。由于该图形定义了被保护的不受刻蚀掩模刻蚀影响的隔离区，因此在半导体衬底中形成了纳米线。这些纳米线具有60nm的直径和10μm的长度。随后通过加热到800℃来氧化纳米线的外壳。然后通过在HF的槽中腐蚀而除去外壳，留下6到15nm直径的纳米线。
该方法的一个缺点是如此形成的纳米线不包括内在功能元件。
发明内容
本发明提供一种制造纳米线的方法，包括以下步骤：
-在半导体衬底的表面提供构图的刻蚀掩模，以及
-沿垂直于该半导体衬底表面的方向刻蚀该半导体衬底以形成纳米线，
其特征在于：
-该半导体衬底包括第一材料的第一层、第二材料的第二层和第三材料的第三层，这些层相互邻接；
-第二层夹在第一层和第三层之间，并具有至多100nm的厚度，以及
-刻蚀穿过第一层、第二层和第三层以用于形成纳米线，使得该纳米线包括第一材料的第一区、第二材料的第二区和包含第三材料的第三区。
本发明还提供一种装备有第一材料的第一区、第二材料的第二区和第三材料的第三区的纳米线，其中第一和第二材料不同，同时所述第二区夹在所述第一区和所述第三区之间，并具有至多100nm的厚度，其中根据上述方法可得到所述纳米线。
本发明进一步提供一种装备有通过一根或多根纳米线互连的第一和第二电极的电子装置，其特征在于，权利要求7所述的纳米线存在于第一和第二电极之间。
本发明的第一个目的是提供一种方法，通过该方法可以得到这种纳米线。
获得所述第一目的的原因在于，该半导体衬底包括第一材料的第一层和第二材料的第二层，这些层相互邻接；而且刻蚀穿过第一和第二层以形成纳米线，以致该纳米线包括第一材料的第一区和第二材料的第二区。
通过根据本发明的方法可以在沿纳米线的轴向方向形成具有一种或几种内部跃迁的纳米线。适当地引入这种内部跃迁产生了不仅适合于作为晶体管沟道的纳米线。此外，这种纳米线可发射光，用作高频整流器，或形成量子点存储器。从Gud1iksen等人Nature，415(2002)，617-620中可以了解这些。
根据本发明方法的第一个优点是，该方法很简单并且适合于大规模制造。在通过刻蚀制成纳米线之前，可以将材料中所期望的变化引入或提供在半导体衬底上。随后在150mm的单个半导体衬底中可以得到几十亿根纳米线。
根据本发明方法的第二个优点是，在所得到的纳米线中从第一到第二区的跃迁很明显。例如如果跃迁为p-n结和/或如果需要电致发光的话，那么这一点就很重要。
第一材料与第二材料在很多方面不同。在第一实施例中，第一和第二材料包括相同的半导体但是具有不同的掺杂。这导致内部的pn结，或者pnp结(如果需要)。在第二实施例中，第二材料的带隙与第一材料的带隙不同。这些实例有从Si跃迁到SiGe、SiC、或三元或四元化合物、InP和InAs的结、GaAs和GaN或GaP的结、以及其他的III-V、II-VI材料。在第三实施例中，第一材料为金属，第二材料为半导体。
可以以多种方式形成衬底的第一层，并且特别是以多种方式形成衬底的第二层。如果第一材料在掺杂方面不同于第二材料，那么可以提供所谓的德耳塔(delta)掺杂。备选地，第一和第二层可独立形成并随后结合在一起。这种结合技术对于SOI型衬底的制造是公知的。
在另一实施例中，通过在第一层上外延生长第二材料形成第二层。这种外延生长产生很均匀的具有强烈跃迁的层，例如从W.B.deBoer，Adv.In Rapid Thermal and Integrated Processing(KluwerPress，1996)，443-463中可以明显看出，其公开内容在此引入作为参考。此外，在单晶材料的外延生长期间形成与第一层的结合。结果纳米线中第一和第二区之间的粘附性极好。本实施例的另一优点在于外延生长是工业上很常用的技术。
可以通过多种技术刻蚀半导体衬底。在第一变型中，采用干法刻蚀或反应离子刻蚀。在这种情况下，在构图的掩模中定义小尺寸的隔离图形；然后除了位于隔离图形下面的那些将形成纳米线的部分之外，在刻蚀期间将除去整个衬底。本实施例的优点是所述刻蚀技术基本上不受第一和第二层之间的差异影响。
在第二变型中，使用了阳极浸蚀法。在这种情况下，在构图的掩模中定义开口。在刻蚀期间，在开口的下面形成微孔，由于适当地设置了电流密度，微孔变得更宽，直到在微孔之间仅保留纳米线。阳极浸蚀法适合于其中第一和第二材料的差异程度较低，例如仅在掺杂方面不同的半导体衬底。
在另一实施例中，第三材料的第三层存在于半导体衬底中，第二层夹在第一层和第三层之间，并具有至多100nm的厚度。为了形成纳米线，刻蚀穿过第一、第二和第三层，由此纳米线包括第一区、第二区以及第三材料的第三区。可以用本发明的该实施例制成具有局部定义功能的功能线。一个例子是其中局部存在SiGe区的Si的纳米线。与Si相比SiGe的带隙较小，引起SiGe吸引电子。这里第二区基本上为点的形状。它可以起量子点的作用，其中由于存在量子化可以以有效的方式高密度地存储信息。而且这种点形源特别适合于用做光电复合中心和用做发出辐射的激光。在本实施例的另一变型中，可以在线中定义所期望的结构。实例是交替掺杂或带隙的结构，诸如p-n-p-n-p...和S i-Ge-Si-Ge-Si...和InP-InAs-InP-InAs-...
在优选实施例中，从衬底中除去纳米线。然后将它们分散并提供在衬底上。例如可以用超声振动来除去。
备选地，不除去纳米线，但是在硅衬底上进一步构建装置。然后优选地以适合于应用的图形来刻蚀衬底。此后将纳米线密封在例如玻璃的绝缘基质中，诸如未预先公开的申请EP 02078262.9(PHNL 020716)中所介绍的。这特别适合于显示应用。
可以从Gudliksen等人Nature，415(2002)，617-620了解具有内部功能的纳米线。该公知纳米线的一个缺点是，第一材料的第一区和第二材料的第二区之间的跃迁是在15到20nm的范围内渐进的。对于高频应用或某一波长的发光来讲，这种跃迁不够强烈。
因此本发明的第二目的是提供一种纳米线，该纳米线具有第一材料的第一区和第二材料的第二区，在第一区和第二区之间存在跃迁，该跃迁基本上在原子标度上是强烈的。
本发明的第三目的是，提供一种在第三段落中提到的具有根据本发明纳米线的类型的电子装置。
获得第二目的的原因在于，通过根据本发明的方法得到纳米线。
获得第三目的的原因在于，本发明的纳米线存在于第一和第二电极之间。
附图说明
参考实施例和附图，下面更详细地介绍根据本发明的方法、纳米线以及装置的这些和其它方面，其中：
图1A到C示出了本方法的第一实施例；
图2A到C示出了本方法的第二实施例；以及
图3为本电子装置的示意性剖视图。
具体实施方式
实施例1
图1示出了根据本发明方法的第一实施例，通过该方法经干法刻蚀在半导体衬底5中形成纳米线10。图1A示出具有n型掺杂的第一层13、具有p型掺杂的第二层14以及具有n型掺杂的第三层16的半导体衬底5。图1B示出了在其表面1处具有刻蚀掩模20的半导体衬底5。图1C示出在从衬底5分离这些纳米线10之前，干法刻蚀之后形成的纳米线10。下面将更详细地介绍：
具有p型掺杂的Si的第二层14被外延地生长在具有n型掺杂(掺杂级别1019atom/cm3)的第一层13上。第二层14的厚度约10到30nm。具有n型掺杂的Si的第三层16被外延地生长在第二层14上。第三层16的厚度约200nm。
包括400nm厚的硬烘焙的Shipley AZS1830的下层和80nm厚包括硅酮的负电子束抗蚀剂的上层的光敏双层被提供在所得半导体衬底5上，如图1A所示。借助辐射(电子束，100KV，100μC/cm2)构图所述双层，由此定义了隔离区20。这些隔离区20具有50×50nm的直径并相互间隔0.5μm。在二甲苯中显影顶层20秒钟，之后在异丙醇中浸泡30秒钟。然后以0.07W/cm2的低rf功率密度和-170V的dc偏压下通过0.3Pa的氧等离子体刻蚀，将图形各向异性地从顶层转移到下层。
随后沿基本上垂直于表面1的方向来刻蚀半导体衬底5。这利用感应耦合等离子体(ICP)装置通过干法刻蚀完成，其中交替进行刻蚀步骤和钝化步骤。该处理是rf控制的(13.56MHz)。用于刻蚀步骤的气体混合物为SF6/O2/C4F8。这里的标准值为约2Pa压力下130sccm的SF6气体流、13sccm的O2气体流、以及40sccm的C4F8气体流。以140sccm气体流速的C4F8被用作钝化步骤的气体。用于刻蚀步骤和钝化步骤的标准周期是8秒钟。
将半导体衬底5刻蚀到约1.0μm的深度。然后首先除去刻蚀掩模20。随后，在氧气气氛中加热半导体衬底5到约850℃持续2小时。这使硅热氧化。然后将半导体衬底5放置在具有浓度约每升5摩尔的氢氟酸的槽中。在槽中保持循环以使槽的组分不变。结果是得到10nm直径的纳米线10。具有纳米线10的半导体衬底5放置在乙醇的槽中。该槽放置在超声装置中。借助超声振动从衬底5分离纳米线10。以此方式得到具有内部n-p-n结的纳米线10。
形成的纳米线10的分散被提供在硅衬底上。借助电子束(e束)，在2nm的Ti和10nm的Au的双层中以光刻方式来定义电接触。在施加布线之后，加热到400℃。
实施例2
用具有p型掺杂的第一层13和具有n型掺杂的第二层14制备半导体衬底5。通过阳极浸蚀法从该半导体衬底5形成纳米线10。用于该目的的凹槽15首先提供在表面1中，随后将半导体衬底5放置在阳极电解槽中。然后半导体衬底5的背面2置于硫酸钾溶液中，以致该背面2以导电方式连接到阳极。半导体衬底5的表面1处于氢氟酸溶液中。通过超声振动，纳米线10最终从半导体衬底5脱离。备选地，可以使用具有n型掺杂的第一层13和具有p型掺杂的第二层14。在那种情况下，将暴露出半导体衬底5的背面2。
图2A示出了在正面1已提供了凹槽15之后的半导体衬底5。在预先提供的构图的刻蚀掩模的开口中形成凹槽15。刻蚀掩模如下制备：依次在衬底5上提供140nm厚的Si3N4层和光致抗蚀剂。通过其中存在1.5μm直径孔的掩模而局部地露出所述光致抗蚀剂。开口之间的间距12为3.5μm。该间距定义为两个相互邻接开口的中心之间的距离。在露出的位置中光致抗蚀剂溶解，而Si3N4到达表面。用优选浓度的H3PO4溶液刻蚀Si3N4。然后在氧等离子体中除去光致抗蚀剂。将半导体衬底5放置在70℃的8.8摩尔KOH浴槽中8分钟。由此，KOH浴槽沿快(100)晶向刻蚀掉Si的半导体衬底5，而慢(111)晶向基本上不受影响。以此方式，在150mm直径的半导体衬底5的表面1中定义了基本相同形状的多于十亿个金字塔形尖头凹槽15。由此形成的图形为六角形栅格。
图2B示出了阳极浸蚀一段时间之后的半导体衬底5。对于该刻蚀来讲，设置温度、HF浓度以及施加的电压值使得电流密度超过峰值电流密度ips的90％。例如在温度为30℃、3.0M的HF浓度、且电流密度为130mA/cm2的槽中就是这样的情形。在第一相中进行各向同性刻蚀。然后继续各向异性刻蚀。
图2C示出了在另一阶段的半导体衬底。结果是微孔交错之后得到纳米线10。纳米线10的长度可以设置为1和100μm之间或更长的所需要的值。这些可以通过选择刻蚀时间来设置。在以上设置的情况下，为了得到100μm长度的纳米线10必需约20分钟的刻蚀时间。得到具有直径50和80μm以及更大的纳米线10。通过约800℃热氧化纳米线10并在HF溶液中刻蚀掉所得的SiO2可以减小直径。在一个半导体衬底5上得到的纳米线10的数量多于二十亿个(2.109)。
实施例3
通过在HF中浸泡表面，在900℃清洁具有Si作为其第一材料的第一层13的表面。借助H2/SiH2Cl2/GeH4的气体混合物的化学汽相淀积，在625℃生长第二层14。在标准的可买到的外延反应器的气压下生长第二层14。第二层的第二材料是SixGe1-x，其中x取决于气体混合物中的SiH2Cl2与GeH4的相互浓度。优选0.4≤x≤0.6。配置第二层的厚度到30nm。然后通过将气体混合物改变为H2/SiH2Cl2而在相同的反应器中外延地生长Si的第三层16。第三层16生长到400nm的厚度。随后如实施例1中介绍的，将刻蚀掩模20提供在半导体衬底5上。得到的是具有SiGe内部点的Si的纳米线10。
实施例4
图2示出了薄膜晶体管的半导体元件100的示意性剖视图。源电极101和漏电极102提供在聚酰亚胺衬底110上。电极101，102例如包括Au，并通过光刻装置定义。通过包括电介质材料的沟道(channel)105将电极101，102分开，该电介质材料优选具有低介电常数。本领域中的技术人员已知的合适材料为二氧化硅、氢硅酸盐(silesquioxa-ne)以及甲基硅酸盐(methyl silesquioxane)、多孔二氧化硅、SiLK以及苯环丁烯。材料的选择还取决于衬底的选择。将电极101，102以及沟道105的表面11平坦化，由此纳米线10出现在基本上平坦的表面111上。纳米线10被铺放且对准，原因在于施加电压的同时，包括纳米线的分散液滴被提供在表面111上。所施加的频率为1kHz且大于25V的AC电压使纳米线10对准。将栅电极103与纳米线10分开的电介质层106存在于纳米线10之上。可以以可选地方式进行对准，原因在于带有沟道的模型被提供在表面111上，整个组件放置在分散纳米线的槽内。借助压力差产生流动，使得纳米线被吸入模型的沟道内。这导致对准的纳米线10的定位。
对于本领域中的技术人员来说显而易见的是，电子装置优选包括大量半导体元件100，这些半导体元件100以需要的图形互连以便形成电路。还应该注意的是，大量的纳米线10可以存在于一个单独的半导体元件100中，而且如薄膜晶体管领域的技术人员已知的那样可以选择多种材料用于衬底110、电极101，102，103以及电介质层105，106。

Claims (8)

1.一种制造纳米线的方法，包括以下步骤：
-在半导体衬底的表面提供构图的刻蚀掩模，以及
-沿垂直于该半导体衬底表面的方向刻蚀该半导体衬底以形成纳米线，
其特征在于：
-该半导体衬底包括第一材料的第一层、第二材料的第二层和第三材料的第三层，这些层相互邻接；
-第二层夹在第一层和第三层之间，并具有至多100nm的厚度，以及
-刻蚀穿过第一层、第二层和第三层以用于形成纳米线，使得该纳米线包括第一材料的第一区、第二材料的第二区和包含第三材料的第三区。
2.根据权利要求1所述的方法，其特征在于，第一和第二材料是具有不同掺杂的相同的半导体。
3.根据权利要求1或2所述的方法，其特征在于，通过在第一层上外延生长第二材料来形成第二层。
4.根据权利要求1或2所述的方法，其特征在于，第一材料是Si，第二材料选自包括SiC、SiGe以及SiGeC构成的组。
5.根据权利要求1或2所述的方法，其特征在于，第三材料与第一材料相同。
6.根据权利要求1或2所述的方法，其特征在于，在刻蚀衬底之后从该衬底除去所述纳米线。
7.一种装备有第一材料的第一区、第二材料的第二区和第三材料的第三区的纳米线，其中第一和第二材料不同，同时所述第二区夹在所述第一区和所述第三区之间，并具有至多100nm的厚度，其中通过根据权利要求1到6中任一项所述的方法可得到所述纳米线。
8.一种装备有通过一根或多根纳米线互连的第一和第二电极的电子装置，其特征在于，权利要求7所述的纳米线存在于第一和第二电极之间。
CNB038071436A 2002-03-28 2003-03-26 制造纳米线的方法、纳米线和电子装置 Expired - Lifetime CN100380603C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02076280.3 2002-03-28
EP02076280 2002-03-28

Publications (2)

Publication Number Publication Date
CN1643661A CN1643661A (zh) 2005-07-20
CN100380603C true CN100380603C (zh) 2008-04-09

Family

ID=28459540

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038071436A Expired - Lifetime CN100380603C (zh) 2002-03-28 2003-03-26 制造纳米线的方法、纳米线和电子装置

Country Status (6)

Country Link
US (1) US7192533B2 (zh)
EP (1) EP1493178B1 (zh)
JP (1) JP2005522030A (zh)
CN (1) CN100380603C (zh)
AU (1) AU2003215837A1 (zh)
WO (1) WO2003083919A2 (zh)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7552645B2 (en) * 2003-05-07 2009-06-30 California Institute Of Technology Detection of resonator motion using piezoresistive signal downmixing
US7434476B2 (en) * 2003-05-07 2008-10-14 Califronia Institute Of Technology Metallic thin film piezoresistive transduction in micromechanical and nanomechanical devices and its application in self-sensing SPM probes
US7302856B2 (en) * 2003-05-07 2007-12-04 California Institute Of Technology Strain sensors based on nanowire piezoresistor wires and arrays
US6905975B2 (en) * 2003-07-03 2005-06-14 Micron Technology, Inc. Methods of forming patterned compositions
CN100444338C (zh) * 2003-12-22 2008-12-17 皇家飞利浦电子股份有限公司 制造半导体纳米线组以及包括纳米线组的电器件
US20050208769A1 (en) * 2004-03-19 2005-09-22 Manish Sharma Semiconductor structure
KR100552707B1 (ko) * 2004-04-07 2006-02-20 삼성전자주식회사 나노와이어 발광소자 및 그 제조방법
WO2006046177A2 (en) * 2004-10-27 2006-05-04 Koninklijke Philips Electronics N.V. Semiconductor device with tunable energy band gap
TWI311213B (en) * 2004-12-24 2009-06-21 Au Optronics Corp Crystallizing method for forming poly-si films and thin film transistors using same
KR100643473B1 (ko) 2005-09-06 2006-11-10 엘지전자 주식회사 나노 로드를 갖는 발광 소자 및 그의 제조 방법
EP1786027A3 (en) * 2005-11-14 2009-03-04 Schott AG Plasma etching of tapered structures
WO2007086009A1 (en) * 2006-01-25 2007-08-02 Nxp B.V. Nanowire tunneling transistor
KR101198763B1 (ko) * 2006-03-23 2012-11-12 엘지이노텍 주식회사 기둥 구조와 이를 이용한 발광 소자 및 그 형성방법
US7924413B2 (en) * 2006-04-28 2011-04-12 Hewlett-Packard Development Company, L.P. Nanowire-based photonic devices
JP2008007376A (ja) * 2006-06-29 2008-01-17 National Univ Corp Shizuoka Univ ナノワイヤ部材およびその製造方法
US8643087B2 (en) 2006-09-20 2014-02-04 Micron Technology, Inc. Reduced leakage memory cells
TWI340481B (en) * 2007-06-11 2011-04-11 Univ Nat Chiao Tung The method for promoting light emission efficiency of led using nano-rod structure
US8025776B2 (en) * 2007-10-29 2011-09-27 Korea Institute Of Science And Technology Glass electrophoresis microchip and method of manufacturing the same by MEMS fabrication
US8405041B2 (en) 2007-11-20 2013-03-26 Nxp B.V. Electrode for an ionization chamber and method producing the same
CN101229912B (zh) * 2007-12-26 2010-06-16 中国科学院上海微系统与信息技术研究所 采用干法刻蚀制备氮化镓纳米线阵列的方法
US8273591B2 (en) * 2008-03-25 2012-09-25 International Business Machines Corporation Super lattice/quantum well nanowires
KR101005803B1 (ko) * 2008-08-11 2011-01-05 한국표준과학연구원 양자점나노선 어레이 태양광 소자 및 그 제조 방법
US8546742B2 (en) 2009-06-04 2013-10-01 Zena Technologies, Inc. Array of nanowires in a single cavity with anti-reflective coating on substrate
US8274039B2 (en) 2008-11-13 2012-09-25 Zena Technologies, Inc. Vertical waveguides with various functionality on integrated circuits
US9000353B2 (en) 2010-06-22 2015-04-07 President And Fellows Of Harvard College Light absorption and filtering properties of vertically oriented semiconductor nano wires
US8866065B2 (en) 2010-12-13 2014-10-21 Zena Technologies, Inc. Nanowire arrays comprising fluorescent nanowires
US8748799B2 (en) 2010-12-14 2014-06-10 Zena Technologies, Inc. Full color single pixel including doublet or quadruplet si nanowires for image sensors
US8229255B2 (en) 2008-09-04 2012-07-24 Zena Technologies, Inc. Optical waveguides in image sensors
US8835831B2 (en) 2010-06-22 2014-09-16 Zena Technologies, Inc. Polarized light detecting device and fabrication methods of the same
US20100148221A1 (en) * 2008-11-13 2010-06-17 Zena Technologies, Inc. Vertical photogate (vpg) pixel structure with nanowires
US9082673B2 (en) 2009-10-05 2015-07-14 Zena Technologies, Inc. Passivated upstanding nanostructures and methods of making the same
US9299866B2 (en) 2010-12-30 2016-03-29 Zena Technologies, Inc. Nanowire array based solar energy harvesting device
US8735797B2 (en) 2009-12-08 2014-05-27 Zena Technologies, Inc. Nanowire photo-detector grown on a back-side illuminated image sensor
US9478685B2 (en) 2014-06-23 2016-10-25 Zena Technologies, Inc. Vertical pillar structured infrared detector and fabrication method for the same
US9343490B2 (en) 2013-08-09 2016-05-17 Zena Technologies, Inc. Nanowire structured color filter arrays and fabrication method of the same
US9515218B2 (en) * 2008-09-04 2016-12-06 Zena Technologies, Inc. Vertical pillar structured photovoltaic devices with mirrors and optical claddings
US8299472B2 (en) 2009-12-08 2012-10-30 Young-June Yu Active pixel sensor with nanowire structured photodetectors
US9406709B2 (en) 2010-06-22 2016-08-02 President And Fellows Of Harvard College Methods for fabricating and using nanowires
US7981772B2 (en) * 2008-12-29 2011-07-19 International Business Machines Corporation Methods of fabricating nanostructures
US8610100B2 (en) * 2009-06-30 2013-12-17 Nokia Corporation Apparatus comprising nanowires
JP4927223B2 (ja) * 2010-09-01 2012-05-09 シャープ株式会社 発光素子およびその製造方法、発光装置の製造方法、照明装置、バックライト並びに表示装置
US9190590B2 (en) 2010-09-01 2015-11-17 Sharp Kabushiki Kaisha Light emitting element and production method for same, production method for light-emitting device, illumination device, backlight, display device, and diode
WO2012029381A1 (ja) * 2010-09-01 2012-03-08 シャープ株式会社 発光素子およびその製造方法、発光装置の製造方法、照明装置、バックライト、表示装置、並びにダイオード
CN102646750A (zh) * 2011-02-22 2012-08-22 中国科学院微电子研究所 一种硅基纳米柱阵列太阳能电池的制备方法
US9852870B2 (en) * 2011-05-23 2017-12-26 Corporation For National Research Initiatives Method for the fabrication of electron field emission devices including carbon nanotube field electron emisson devices
CN102569034A (zh) * 2012-02-15 2012-07-11 中国科学院半导体研究所 在自然氧化的Si衬底上生长InAs纳米线的方法
US8835255B2 (en) * 2013-01-23 2014-09-16 Globalfoundries Inc. Method of forming a semiconductor structure including a vertical nanowire
US9595525B2 (en) 2014-02-10 2017-03-14 International Business Machines Corporation Semiconductor device including nanowire transistors with hybrid channels
US9698025B2 (en) 2014-09-04 2017-07-04 Globalfoundries Inc. Directed self-assembly material growth mask for forming vertical nanowires
US10186577B2 (en) 2014-09-04 2019-01-22 Globalfoundries Inc. Multiple directed self-assembly material mask patterning for forming vertical nanowires
US9865682B2 (en) 2014-09-04 2018-01-09 Globalfoundries Inc. Directed self-assembly material etch mask for forming vertical nanowires
CN105097449B (zh) * 2015-06-09 2018-07-31 华为技术有限公司 一种制作纳米线的方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0544408A2 (en) * 1991-10-28 1993-06-02 Xerox Corporation Quantum confinement semiconductor light emitting devices

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE544408C (de) * 1929-07-24 1932-02-24 Thomas Henry Jones Rundstrickmaschine mit zwei staendig entgegengesetzt zueinander umlaufenden Schloessern und in Gruppen unterteilten Nadeln
JPH05175123A (ja) * 1991-06-20 1993-07-13 Sanyo Electric Co Ltd 半導体装置の製造方法
JPH05102198A (ja) * 1991-10-04 1993-04-23 Nec Corp 擬１次元電界効果トランジスタとその製造方法
JP2624450B2 (ja) * 1994-02-10 1997-06-25 光技術研究開発株式会社 量子細線構造の製造方法
JPH10106960A (ja) * 1996-09-25 1998-04-24 Sony Corp 量子細線の製造方法
JP3295373B2 (ja) * 1998-06-03 2002-06-24 松下電器産業株式会社 半導体装置
JP2002220300A (ja) * 2001-01-18 2002-08-09 Vision Arts Kk ナノファイバーおよびナノファイバーの作製方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0544408A2 (en) * 1991-10-28 1993-06-02 Xerox Corporation Quantum confinement semiconductor light emitting devices

Also Published As

Publication number Publication date
WO2003083919A3 (en) 2003-12-24
WO2003083919A2 (en) 2003-10-09
CN1643661A (zh) 2005-07-20
AU2003215837A8 (en) 2003-10-13
JP2005522030A (ja) 2005-07-21
US20050236357A1 (en) 2005-10-27
US7192533B2 (en) 2007-03-20
EP1493178B1 (en) 2018-09-26
AU2003215837A1 (en) 2003-10-13
EP1493178A2 (en) 2005-01-05

Similar Documents

Publication Publication Date Title
CN100380603C (zh) 制造纳米线的方法、纳米线和电子装置
US10553716B2 (en) Formation of a bottom source-drain for vertical field-effect transistors
US9761724B2 (en) Semiconductor device structures and methods of forming semiconductor structures
US10074536B2 (en) Lattice-mismatched semiconductor structures and related methods for device fabrication
CN102176465B (zh) 可印刷半导体结构以及相关制造和组装方法
DE102011053819B4 (de) Halbleiterbauelement und Verfahren zum Ausbilden eines Halbleiterbauelements
US20070120254A1 (en) Semiconductor device comprising a pn-heterojunction
CN103311305B (zh) 硅基横向纳米线多面栅晶体管及其制备方法
CN100409450C (zh) 纳米线和电子器件
CN106711329A (zh) 形成纳米线基装置的方法
WO2015109456A1 (zh) Soi衬底制备方法和soi衬底
US7833884B2 (en) Strained semiconductor-on-insulator by Si:C combined with porous process
Yoon et al. Electrical characteristics of GaAs nanowire-based MESFETs on flexible plastics
US20080164577A1 (en) Patterned silicon submicron tubes
JPH0582441A (ja) 炭化シリコンバイポーラ半導体装置およびその製造方法
KR20090012472A (ko) 실리콘 기판 상에 게르마늄 메사 구조를 형성하는 방법
CN110120365A (zh) 隔离结构及其形成方法
Taniyama et al. Selective-Area Growth of InGaAs Nanowires on SOI and the Vertical Transistor Application
CN111243960A (zh) 一种半导体纳米线及场效应晶体管的制备方法
JP3249101B2 (ja) Ｍｏｓ半導体装置
CN113555311A (zh) 一种含绝缘衬底的氮化镓晶片材料及其制备与应用
Levin Heterogeneous Integration of III-V and II-IV Semiconductor Sheets onto Silicon Substrate through Electric-Field Assisted Assembly for Device Applications
Dowdy Planar Gallium arsenide nanowire arrays for nanoelectronics: Controlled growth, doping, characterization, and devices
EP3465737A2 (en) Method for producing complimentary devices
KR20140022328A (ko) 나노와이어 소자 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Eindhoven, Netherlands

Patentee after: KONINKLIJKE PHILIPS N.V.

Address before: Eindhoven, Netherlands

Patentee before: KONINKLIJKE PHILIPS ELECTRONICS N.V.

CP01 Change in the name or title of a patent holder
TR01 Transfer of patent right

Effective date of registration: 20200724

Address after: Holland Schiphol

Patentee after: KONINKLIJKE PHILIPS NV

Address before: Eindhoven, Netherlands

Patentee before: KONINKLIJKE PHILIPS N.V.

TR01 Transfer of patent right
CX01 Expiry of patent term

Granted publication date: 20080409

CX01 Expiry of patent term