CN100380576C - 以减少远处散射的栅极氧化制造高性能金属氧化物半导体晶体管的方法 - Google Patents
以减少远处散射的栅极氧化制造高性能金属氧化物半导体晶体管的方法 Download PDFInfo
- Publication number
- CN100380576C CN100380576C CNB038114208A CN03811420A CN100380576C CN 100380576 C CN100380576 C CN 100380576C CN B038114208 A CNB038114208 A CN B038114208A CN 03811420 A CN03811420 A CN 03811420A CN 100380576 C CN100380576 C CN 100380576C
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon dioxide
- dielectric
- gate
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
- H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/689—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having ferroelectric layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/84—Manufacture, treatment, or detection of nanostructure
- Y10S977/88—Manufacture, treatment, or detection of nanostructure with arrangement, process, or apparatus for testing
- Y10S977/881—Microscopy or spectroscopy, e.g. sem, tem
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/151,269 US6621114B1 (en) | 2002-05-20 | 2002-05-20 | MOS transistors with high-k dielectric gate insulator for reducing remote scattering |
| US10/151,269 | 2002-05-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1656596A CN1656596A (zh) | 2005-08-17 |
| CN100380576C true CN100380576C (zh) | 2008-04-09 |
Family
ID=27804574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB038114208A Expired - Lifetime CN100380576C (zh) | 2002-05-20 | 2003-05-13 | 以减少远处散射的栅极氧化制造高性能金属氧化物半导体晶体管的方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6621114B1 (enExample) |
| EP (1) | EP1508158A2 (enExample) |
| JP (1) | JP4624782B2 (enExample) |
| KR (1) | KR100966360B1 (enExample) |
| CN (1) | CN100380576C (enExample) |
| AU (1) | AU2003230394A1 (enExample) |
| TW (1) | TWI284983B (enExample) |
| WO (1) | WO2003100835A2 (enExample) |
Families Citing this family (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6906398B2 (en) * | 2003-01-02 | 2005-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor chip with gate dielectrics for high-performance and low-leakage applications |
| KR100885910B1 (ko) * | 2003-04-30 | 2009-02-26 | 삼성전자주식회사 | 게이트 적층물에 oha막을 구비하는 비 휘발성 반도체메모리 장치 및 그 제조방법 |
| US20040232408A1 (en) * | 2003-05-21 | 2004-11-25 | Heeger Alan J. | Bilayer high dielectric constant gate insulator |
| US7045847B2 (en) * | 2003-08-11 | 2006-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with high-k gate dielectric |
| US7256465B2 (en) * | 2004-01-21 | 2007-08-14 | Sharp Laboratories Of America, Inc. | Ultra-shallow metal oxide surface channel MOS transistor |
| US20050202659A1 (en) * | 2004-03-12 | 2005-09-15 | Infineon Technologies North America Corp. | Ion implantation of high-k materials in semiconductor devices |
| US8399934B2 (en) * | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
| US8178902B2 (en) | 2004-06-17 | 2012-05-15 | Infineon Technologies Ag | CMOS transistor with dual high-k gate dielectric and method of manufacture thereof |
| KR101061168B1 (ko) | 2004-06-23 | 2011-09-01 | 주식회사 하이닉스반도체 | 반도체 소자의 게이트 형성방법 |
| US7320931B2 (en) * | 2004-07-30 | 2008-01-22 | Freescale Semiconductor Inc. | Interfacial layer for use with high k dielectric materials |
| JP2006086151A (ja) * | 2004-09-14 | 2006-03-30 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP2006114747A (ja) * | 2004-10-15 | 2006-04-27 | Seiko Epson Corp | 半導体装置の製造方法 |
| US7183596B2 (en) | 2005-06-22 | 2007-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite gate structure in an integrated circuit |
| US20070001231A1 (en) * | 2005-06-29 | 2007-01-04 | Amberwave Systems Corporation | Material systems for dielectrics and metal electrodes |
| WO2007005312A1 (en) * | 2005-06-29 | 2007-01-11 | Amberwave Systems Corporation | Material systems for dielectrics and metal electrodes and methods for formation thereof |
| US7432139B2 (en) * | 2005-06-29 | 2008-10-07 | Amberwave Systems Corp. | Methods for forming dielectrics and metal electrodes |
| US8053849B2 (en) * | 2005-11-09 | 2011-11-08 | Advanced Micro Devices, Inc. | Replacement metal gate transistors with reduced gate oxide leakage |
| US7436034B2 (en) * | 2005-12-19 | 2008-10-14 | International Business Machines Corporation | Metal oxynitride as a pFET material |
| US7524727B2 (en) * | 2005-12-30 | 2009-04-28 | Intel Corporation | Gate electrode having a capping layer |
| KR100762239B1 (ko) | 2006-05-03 | 2007-10-01 | 주식회사 하이닉스반도체 | 반도체 소자의 pmos 트랜지스터, 이를 포함하는 반도체소자와 그의 제조 방법 |
| US7582549B2 (en) | 2006-08-25 | 2009-09-01 | Micron Technology, Inc. | Atomic layer deposited barium strontium titanium oxide films |
| US8735243B2 (en) | 2007-08-06 | 2014-05-27 | International Business Machines Corporation | FET device with stabilized threshold modifying material |
| CN100561692C (zh) * | 2007-11-09 | 2009-11-18 | 北京大学 | Mos晶体管体区的掺杂方法 |
| JP2009302373A (ja) * | 2008-06-16 | 2009-12-24 | Nec Electronics Corp | 半導体装置の製造方法 |
| CN101783298B (zh) * | 2009-01-21 | 2012-11-14 | 中国科学院微电子研究所 | 抑制高k栅介质/金属栅结构界面层生长的方法 |
| DE102009010883B4 (de) * | 2009-02-27 | 2011-05-26 | Amd Fab 36 Limited Liability Company & Co. Kg | Einstellen eines nicht-Siliziumanteils in einer Halbleiterlegierung während der FET-Transistorherstellung mittels eines Zwischenoxidationsprozesses |
| US9490179B2 (en) | 2010-05-21 | 2016-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and semiconductor device |
| US8492852B2 (en) | 2010-06-02 | 2013-07-23 | International Business Machines Corporation | Interface structure for channel mobility improvement in high-k metal gate stack |
| US20120313186A1 (en) * | 2011-06-08 | 2012-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polysilicon gate with nitrogen doped high-k dielectric and silicon dioxide |
| CN102820327A (zh) * | 2011-06-09 | 2012-12-12 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
| JP2013162073A (ja) * | 2012-02-08 | 2013-08-19 | Toyota Central R&D Labs Inc | 半導体装置とその製造方法 |
| US8883598B2 (en) * | 2012-03-05 | 2014-11-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thin capped channel layers of semiconductor devices and methods of forming the same |
| CN103632966B (zh) * | 2012-08-21 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管的形成方法 |
| CN103632940B (zh) * | 2012-08-23 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
| US20140070169A1 (en) * | 2012-09-12 | 2014-03-13 | Chongwu Zhou | Separated Carbon Nanotube-Based Active Matrix Organic Light-Emitting Diode Displays |
| CN110610983A (zh) * | 2019-09-06 | 2019-12-24 | 电子科技大学 | 抗辐照器件及制备方法 |
| US11264499B2 (en) * | 2019-09-16 | 2022-03-01 | Globalfoundries U.S. Inc. | Transistor devices with source/drain regions comprising an interface layer that comprises a non-semiconductor material |
| CN110620155A (zh) * | 2019-09-24 | 2019-12-27 | 天津大学 | 异质栅介质层柔性硅薄膜晶体管及其制造方法 |
| US12490510B2 (en) * | 2020-08-12 | 2025-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of forming the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1128898A (zh) * | 1994-09-19 | 1996-08-14 | 株式会社日立制作所 | 半导体器件及其制作方法 |
| CN1214540A (zh) * | 1997-10-15 | 1999-04-21 | 世界先进积体电路股份有限公司 | 具有p+多晶硅栅极的金属氧化物半导体晶体管的制作方法 |
| US6278164B1 (en) * | 1996-12-26 | 2001-08-21 | Kabushiki Kaisha Toshiba | Semiconductor device with gate insulator formed of high dielectric film |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555560A (ja) * | 1991-08-23 | 1993-03-05 | Fujitsu Ltd | 半導体装置 |
| JPH05102466A (ja) * | 1991-10-09 | 1993-04-23 | Olympus Optical Co Ltd | Mos型半導体装置及びその製造方法 |
| US5780891A (en) * | 1994-12-05 | 1998-07-14 | Micron Technology, Inc. | Nonvolatile floating gate memory with improved interploy dielectric |
| JPH09246551A (ja) * | 1996-03-13 | 1997-09-19 | Ricoh Co Ltd | Mos型半導体装置及びその製造方法 |
| US6008091A (en) * | 1998-01-27 | 1999-12-28 | Lucent Technologies Inc. | Floating gate avalanche injection MOS transistors with high K dielectric control gates |
| US6246076B1 (en) * | 1998-08-28 | 2001-06-12 | Cree, Inc. | Layered dielectric on silicon carbide semiconductor structures |
| JP2000332235A (ja) * | 1999-05-17 | 2000-11-30 | Hitachi Ltd | 半導体装置およびその製造方法 |
| JP3415496B2 (ja) * | 1999-07-07 | 2003-06-09 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
| US6407435B1 (en) * | 2000-02-11 | 2002-06-18 | Sharp Laboratories Of America, Inc. | Multilayer dielectric stack and method |
| US6444516B1 (en) * | 2000-07-07 | 2002-09-03 | International Business Machines Corporation | Semi-insulating diffusion barrier for low-resistivity gate conductors |
| US6504214B1 (en) * | 2002-01-11 | 2003-01-07 | Advanced Micro Devices, Inc. | MOSFET device having high-K dielectric layer |
| JP2003224268A (ja) * | 2002-01-31 | 2003-08-08 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
-
2002
- 2002-05-20 US US10/151,269 patent/US6621114B1/en not_active Expired - Lifetime
-
2003
- 2003-05-13 AU AU2003230394A patent/AU2003230394A1/en not_active Abandoned
- 2003-05-13 WO PCT/US2003/015194 patent/WO2003100835A2/en not_active Ceased
- 2003-05-13 KR KR1020047018671A patent/KR100966360B1/ko not_active Expired - Fee Related
- 2003-05-13 CN CNB038114208A patent/CN100380576C/zh not_active Expired - Lifetime
- 2003-05-13 EP EP03724576A patent/EP1508158A2/en not_active Withdrawn
- 2003-05-13 JP JP2004508392A patent/JP4624782B2/ja not_active Expired - Fee Related
- 2003-05-19 TW TW092113428A patent/TWI284983B/zh not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1128898A (zh) * | 1994-09-19 | 1996-08-14 | 株式会社日立制作所 | 半导体器件及其制作方法 |
| US6278164B1 (en) * | 1996-12-26 | 2001-08-21 | Kabushiki Kaisha Toshiba | Semiconductor device with gate insulator formed of high dielectric film |
| CN1214540A (zh) * | 1997-10-15 | 1999-04-21 | 世界先进积体电路股份有限公司 | 具有p+多晶硅栅极的金属氧化物半导体晶体管的制作方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2003100835A3 (en) | 2004-07-22 |
| KR20040106568A (ko) | 2004-12-17 |
| CN1656596A (zh) | 2005-08-17 |
| WO2003100835A2 (en) | 2003-12-04 |
| US6621114B1 (en) | 2003-09-16 |
| AU2003230394A8 (en) | 2003-12-12 |
| JP4624782B2 (ja) | 2011-02-02 |
| JP2005531136A (ja) | 2005-10-13 |
| EP1508158A2 (en) | 2005-02-23 |
| KR100966360B1 (ko) | 2010-06-28 |
| TW200401451A (en) | 2004-01-16 |
| TWI284983B (en) | 2007-08-01 |
| AU2003230394A1 (en) | 2003-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100380576C (zh) | 以减少远处散射的栅极氧化制造高性能金属氧化物半导体晶体管的方法 | |
| CN1332437C (zh) | 新型场效应晶体管和制造方法 | |
| US7314802B2 (en) | Structure and method for manufacturing strained FINFET | |
| US20200020710A1 (en) | Method of integrating a charge-trapping gate stack into a cmos flow | |
| US6784101B1 (en) | Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation | |
| JP5535706B2 (ja) | 半導体装置の製造方法 | |
| US9281390B2 (en) | Structure and method for forming programmable high-K/metal gate memory device | |
| US7618853B2 (en) | Field effect transistors with dielectric source drain halo regions and reduced miller capacitance | |
| US7928502B2 (en) | Transistor devices with nano-crystal gate structures | |
| US20060097318A1 (en) | Transistor with silicon and carbon layer in the channel region | |
| US7001818B2 (en) | MIS semiconductor device and manufacturing method thereof | |
| US20090163005A1 (en) | Schottky barrier source/drain N-MOSFET using ytterbium silicide | |
| US20050212041A1 (en) | Novel process method of source drain spacer engineering to improve transistor capacitance | |
| US20070166906A1 (en) | Method to Reduce Transistor Gate to Source/Drain Overlap Capacitance by Incorporation of Carbon | |
| JP2004247341A (ja) | 半導体装置 | |
| US20050263834A1 (en) | Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology | |
| US20070187758A1 (en) | SB-MOSFET (Schottky barrier metal-oxide-semiconductor field effect transistor) with low barrier height and fabricating method thereof | |
| US20060220158A1 (en) | Semiconductor device and manufacturing method thereof | |
| JP2003023147A (ja) | 半導体装置及びその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: GLOBALFOUNDRIES SEMICONDUCTORS CO., LTD Free format text: FORMER OWNER: ADVANCED MICRO DEVICES CORPORATION Effective date: 20100721 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA STATE, THE USA TO: GRAND CAYMAN ISLAND, BRITISH CAYMAN ISLANDS |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20100721 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES Inc. Address before: California, USA Patentee before: ADVANCED MICRO DEVICES, Inc. |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20210329 Address after: California, USA Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd. Address before: Greater Cayman Islands, British Cayman Islands Patentee before: GLOBALFOUNDRIES Inc. |
|
| TR01 | Transfer of patent right | ||
| CX01 | Expiry of patent term |
Granted publication date: 20080409 |
|
| CX01 | Expiry of patent term |