CN100367462C - 在体硅衬底具有增强自对准介电区域的soi半导体器件的制造方法 - Google Patents

在体硅衬底具有增强自对准介电区域的soi半导体器件的制造方法 Download PDF

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Publication number
CN100367462C
CN100367462C CNB038128373A CN03812837A CN100367462C CN 100367462 C CN100367462 C CN 100367462C CN B038128373 A CNB038128373 A CN B038128373A CN 03812837 A CN03812837 A CN 03812837A CN 100367462 C CN100367462 C CN 100367462C
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China
Prior art keywords
gate electrode
bulk substrate
dielectric
oxygen
regions
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Expired - Lifetime
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CNB038128373A
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English (en)
Chinese (zh)
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CN1659687A (zh
Inventor
A·C·韦
D·J·瑞斯特
M·B·菲塞利耶
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GlobalFoundries US Inc
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Advanced Micro Devices Inc
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Publication of CN1659687A publication Critical patent/CN1659687A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials

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  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
CNB038128373A 2002-06-04 2003-05-28 在体硅衬底具有增强自对准介电区域的soi半导体器件的制造方法 Expired - Lifetime CN100367462C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/162,299 US6884702B2 (en) 2002-06-04 2002-06-04 Method of making an SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate
US10/162,299 2002-06-04

Publications (2)

Publication Number Publication Date
CN1659687A CN1659687A (zh) 2005-08-24
CN100367462C true CN100367462C (zh) 2008-02-06

Family

ID=29583580

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038128373A Expired - Lifetime CN100367462C (zh) 2002-06-04 2003-05-28 在体硅衬底具有增强自对准介电区域的soi半导体器件的制造方法

Country Status (8)

Country Link
US (2) US6884702B2 (https=)
EP (1) EP1509950A2 (https=)
JP (1) JP2005528797A (https=)
KR (1) KR20050004285A (https=)
CN (1) CN100367462C (https=)
AU (1) AU2003240569A1 (https=)
TW (1) TWI278025B (https=)
WO (1) WO2003103040A2 (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4412710B2 (ja) * 2003-11-25 2010-02-10 キヤノン株式会社 光電変換装置の設計方法
KR20070034519A (ko) * 2004-05-27 2007-03-28 이 아이 듀폰 디 네모아 앤드 캄파니 광감성 중합체 보호층용 현상제
JP5113999B2 (ja) * 2004-09-28 2013-01-09 シャープ株式会社 水素イオン注入剥離方法
US7250351B2 (en) * 2005-04-14 2007-07-31 International Business Machines Corporation Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors
US20070069300A1 (en) * 2005-09-29 2007-03-29 International Business Machines Corporation Planar ultra-thin semiconductor-on-insulator channel mosfet with embedded source/drain
KR100724560B1 (ko) * 2005-11-18 2007-06-04 삼성전자주식회사 결정질 반도체층을 갖는 반도체소자, 그의 제조방법 및그의 구동방법
DE102006027969A1 (de) * 2006-06-17 2007-12-20 X-Fab Semiconductor Foundries Ag Verfahren zur selektiven Entspiegelung einer Halbleitergrenzfläche durch eine besondere Prozessführung
US7550330B2 (en) * 2006-11-29 2009-06-23 International Business Machines Corporation Deep junction SOI MOSFET with enhanced edge body contacts
US8053327B2 (en) * 2006-12-21 2011-11-08 Globalfoundries Singapore Pte. Ltd. Method of manufacture of an integrated circuit system with self-aligned isolation structures
US7998815B2 (en) * 2008-08-15 2011-08-16 Qualcomm Incorporated Shallow trench isolation
DE102009010843B4 (de) * 2009-02-27 2014-04-10 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Substrate und Halbleiterbauelemente hergestellt unter Einsatz einer Verformungstechnologie unter Anwendung eines piezoelektrischen Materials und Verfahren zum Einsatz einer derartigen Verformungstechnolgie
US20140197462A1 (en) * 2013-01-14 2014-07-17 International Rectifier Corporation III-Nitride Transistor with High Resistivity Substrate
US20140197461A1 (en) * 2013-01-14 2014-07-17 International Rectifier Corporation Semiconductor Structure Including A Spatially Confined Dielectric Region
DE102015211087B4 (de) * 2015-06-17 2019-12-05 Soitec Verfahren zur Herstellung eines Hochwiderstands-Halbleiter-auf-Isolator-Substrates
KR101921627B1 (ko) * 2017-06-16 2018-11-26 한국과학기술연구원 전계 효과 트랜지스터, 이를 구비한 바이오 센서, 전계 효과 트랜지스터의 제조방법 및 바이오 센서의 제조방법
US11189566B2 (en) * 2018-04-12 2021-11-30 International Business Machines Corporation Tight pitch via structures enabled by orthogonal and non-orthogonal merged vias
US12588282B2 (en) 2022-11-13 2026-03-24 Globalfoundries U.S. Inc. Integrated structure with trap rich regions and low resistivity regions

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510640A (en) * 1990-04-17 1996-04-23 Cannon Kabushiki Kaisha Semiconductor device and process for preparing the same
US20010020722A1 (en) * 2000-03-07 2001-09-13 Chien-Kuo Yang Step-like silicon on isolation structure
US6313505B2 (en) * 1998-09-02 2001-11-06 Advanced Micro Devices, Inc. Method for forming shallow source/drain extension for MOS transistor
US20020063286A1 (en) * 2000-11-29 2002-05-30 De-Yuan Wu SOI device and method of fabrication

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278077A (en) * 1993-03-10 1994-01-11 Sharp Microelectronics Technology, Inc. Pin-hole patch method for implanted dielectric layer
JPH0778994A (ja) * 1993-09-07 1995-03-20 Hitachi Ltd Ｍｏｓ型半導体装置及びその製造方法
JP2000208393A (ja) * 1999-01-12 2000-07-28 Asahi Kasei Microsystems Kk 半導体装置の製造方法
US6103569A (en) * 1999-12-13 2000-08-15 Chartered Semiconductor Manufacturing Ltd. Method for planarizing local interconnects
US6407428B1 (en) * 2001-06-15 2002-06-18 Advanced Micro Devices, Inc. Field effect transistor with a buried and confined metal plate to control short channel effects

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510640A (en) * 1990-04-17 1996-04-23 Cannon Kabushiki Kaisha Semiconductor device and process for preparing the same
US6313505B2 (en) * 1998-09-02 2001-11-06 Advanced Micro Devices, Inc. Method for forming shallow source/drain extension for MOS transistor
US20010020722A1 (en) * 2000-03-07 2001-09-13 Chien-Kuo Yang Step-like silicon on isolation structure
US20020063286A1 (en) * 2000-11-29 2002-05-30 De-Yuan Wu SOI device and method of fabrication

Also Published As

Publication number Publication date
AU2003240569A1 (en) 2003-12-19
AU2003240569A8 (en) 2003-12-19
WO2003103040A2 (en) 2003-12-11
WO2003103040A3 (en) 2004-03-18
US20050151133A1 (en) 2005-07-14
CN1659687A (zh) 2005-08-24
TWI278025B (en) 2007-04-01
US20030223258A1 (en) 2003-12-04
TW200401349A (en) 2004-01-16
US7544999B2 (en) 2009-06-09
EP1509950A2 (en) 2005-03-02
KR20050004285A (ko) 2005-01-12
US6884702B2 (en) 2005-04-26
JP2005528797A (ja) 2005-09-22

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