CN100336213C - 再分配层中的控制阻抗传输线 - Google Patents
再分配层中的控制阻抗传输线 Download PDFInfo
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Abstract
在一个实施例中,本发明包括制作于半导体管芯(100)上再分配层中的第一(104)和第二(118)传输线。第一传输线(104)具有离第一金属层中第一接地返回通路的第一距离。第一传输线(104)具有对应于第一距离的第一阻抗。换句话说,第一传输线(104)的阻抗受第一传输线(104)和第一接地返回通路间距离的影响。与第一传输线(104)类似,第二传输线(118)具有离第二金属层中形成的第二接地返回通路的第二距离。第二传输线(118)具有对应于第二距离的第二阻抗。换句话说,第二传输线(118)的阻抗受第二传输线(118)和第二接地返回通路间距离的影响。
Description
发明背景
发明领域
本发明一般涉及半导体电路领域。尤其是,本发明涉及半导体电路中传输线阻抗控制的领域。
技术背景
对以高频工作的更小、更复杂和更快的装置,诸如无线通信装置和蓝牙RF收发器的消费者需求导致对具有更高密度的半导体管芯的需求增长。随着半导体管芯的密度增加,半导体管芯周边上的输入/输出(I/O)焊盘的数量也增加。结果,在半导体管芯的周边上放置I/O焊盘的空间量减少。为了解决这个问题,半导体制造商转移到区域阵列I/O设计。
在区域阵列I/O设计中,使用再分配层(RDL)将半导体管芯周边上的I/O焊盘重新设置到半导体管芯中间的区域阵列处。通常,RDL是主要由铝或铜构成的薄膜选路(routing)层。RDL包括互连线,本申请中也称作传输线,它提供半导体管芯周边上的I/O焊盘与区域阵列配置中的焊料凸起之间的电连接。在凸起下,金属(UBM)用来将焊料凸起贴附到互连线上。
RDL中的互连线,即传输线,由半导体管芯中位于I/O焊盘附近的I/O驱动器(或“线路驱动器”)驱动。I/O驱动器预计与具有特定阻抗的传输线对接。如果传输线的阻抗不与各相应的I/O驱动器的阻抗匹配,则不能以优化方式产生电信号通过传输线的传输并且电信号的传输通常将变慢。
用来降低该阻抗不匹配问题影响的一种方法是增加I/O驱动器的强度。但是,实质更强的I/O驱动器的使用将增加制造半导体管芯的成本。针对该问题的另一种方法是增加驱动传输线的I/O驱动器的数量。但是,增加I/O驱动器的数量也会增加制造半导体管芯的成本。
因此,本技术领域中需要一种RDL中的传输线,它能与半导体管芯中I/O驱动器的所需阻抗匹配。
发明概述
本发明针对再分配层中的控制阻抗传输线。本发明满足了本技术领域中对再分配层中能与半导体管芯中I/O驱动器的所需阻抗匹配的传输线的需要。
在一个实施例中,本发明包括制造于半导体管芯上的再分配层中的第一和第二传输线。第一传输线具有离第一金属层中形成的第一接地返回通路的第一距离。例如,第一接地返回通路可以形成在半导体管芯内的金属层六中。第一传输线具有对应于第一距离的第一阻抗。换句话说,第一传输线的阻抗受第一传输线和第一接地返回通路间距离的影响,在该实例中即第一传输线和金属层六中形成的接地返回通路间的距离。
与第一传输线类似,所述第二传输线具有离第二金属层中形成的第二接地返回通路的第二距离。例如,第二接地返回通路可以形成在半导体管芯内的金属层五中。第二传输线具有对应于第二距离的第二阻抗。换句话说,第二传输线的阻抗受第二传输线和第二接地返回通路间距离的影响,在该实例中即第二传输线和金属层五中形成的接地返回通路间的距离。
因此,通过确定半导体管芯中哪个特定金属层用作特定传输线的接地返回通路,本发明形成对传输线阻抗的附加控制,这超出了对阻抗的常规控制,其中所述常规控制包括控制诸如传输线宽度和厚度的参数。
本发明的以下部分中将讨论本发明的各种其它概念、特点和优点。
附图概述
图1示出根据本发明的一个实施例的实例性结构的顶视图。
图2示出根据本发明的一个实施例的图1中实例性结构的一部分的展开图。
图3示出根据本发明的一个实施例的半导体管芯的一部分的剖视图。
具体实施方式
本发明针对再分配层中的控制阻抗传输线。以下的描述包含从属于本发明各种实施例和实现方式的特定信息。本技术领域中熟练的技术人员将理解,本发明可以以与本申请中所特别讨论不同的方式实现。此外,不讨论本发明的某些特定细节以使本发明更便于理解。本申请中不描述的特定细节在本技术领域内普通技术人员的知识范围内。
本申请的附图和其所附的详细描述将仅仅针对本发明的实例性实施例。为了保持简洁,本申请中将不描述应用本发明原理的本发明的其它实施例并不由本附图特别示出。
图1中半导体管芯100示出根据本发明一个实施例的实例性半导体管芯的顶视图。应注意,本申请中诸如半导体管芯100的“半导体管芯”也称作“管芯”、“芯片”或“半导体芯片”。本技术领域内熟练的技术人员将理解,图1中没有示出各种元件和特点以使本发明更易于理解并便于图1的描述。例如,图1中未示出通常沉积在诸如传输线104的传输线上的诸如苯并环丁烯(“BCB”)的电介质层以便示出传输线。相对于图1并进一步相对于图2和3示出,可以控制本发明的传输线的实例性实施例的阻抗以便与诸如50.0欧姆的工业标准阻抗的所需阻抗匹配。同样,应注意,本申请中,属于“传输线”称作“互连线”且这两个术语可以交替使用。
图1示出半导体管芯结合焊盘102,它制作于半导体管芯100的周边上。半导体管芯结合焊盘102例如可以是与外部装置对接的输入/输出(“I/O”)焊盘。半导体管芯结合焊盘102可以包括铝或其它金属,诸如铜、铜铝合金或金。图1还示出传输线104,它提供半导体管芯结合焊盘102和焊料凸起106之间的电连接。根据本发明的实施例,传输线104可以制造于半导体管芯100的再分配层(RDL)中。例如,传输线104可以采用溅射沉积和深蚀刻处理制造于RDL中。传输线104可以包括铝或其它金属,诸如铜、铜铝合金或金。
经由本底,诸如焊料凸起106的焊料凸起允许半导体管芯100采用倒装晶片技术安置在互连基片(图1中未示出)上。如本技术领域内已知的,倒装晶片技术是表面安装技术,其中管芯被“翻转”从而管芯的工作(active)表面朝向互连基片。在倒装晶片技术中,通过由图1中诸如焊料凸起106的焊料凸起构成的区域阵列实现管芯和互连基片之间的电接触。
如图1所示,半导体管芯结合焊盘108、110、112、114和116制造于半导体管芯100的周边。半导体管芯结合焊盘108、110、112、114和116类似于以上讨论的半导体管芯结合焊盘102,并包括与半导体管芯结合焊盘102类似的材料。进一步如图1所示,传输线118、120、122、124和126分别将半导体管芯结合焊盘108、110、112、114和116电连接到焊料凸起128、130、132、134和136。以与上述传输线104类似的方式制造传输线118、120、122、124和126。同样,传输线118、120、122、124和126包括类似于传输线104的材料。将参考图2并特别针对虚线38所包围的部位(对应于由图2中虚线238包围的部位)更详细地描述传输线118、120、122、124和126。
诸如传输线118的每个上述传输线由连接到诸如半导体管芯结合焊盘108的I/O焊盘的各I/O驱动器(图1中未示出)驱动。在另一个实施例中I/O驱动器可以直接耦合到传输线而不经由半导体管芯结合焊盘。当诸如传输线104的传输线的阻抗接近地与其各I/O驱动器的阻抗匹配时,从I/O驱动器发送的信号可以以最优方式穿过传输线,其中最优方式即最优速度和具有最小能量损耗。结果,可以使诸如焊料凸起106的半导体管芯焊料凸起处输出的信号品质的退化最小化。
互连线(即传输线)的宽度和厚度以及从参考接地线或平面(也称作“接地返回通路”)起的互连线距离影响互连线的电阻、电感和电容,从而影响其总阻抗。例如,假定传输线118是接地线,即“接地返回通路”。进一步假定传输线126和122具有相同的宽度和厚度。假定所有其它参数都是相等的,由于传输线122更靠近传输线118,每毫米长度的传输线122的电感将低于每毫米长度传输线126的电感,其中该实例中传输线126远离接地线,即传输线118。这样,如果所有其它参数相等,传输线126的阻抗将大于传输线122的阻抗。
因此,如以下将示出的,本发明提供了一种诸如图1传输线126的传输线以便通过控制传输线的宽度和厚度以及它离参考返回接地通路的距离来满足诸如50.0欧姆的所需阻抗。
图2示出部位238的顶视图,其中部位238是图1中部位138的展开图。特别地,半导体管芯结合焊盘208、210、212、214和216,传输线204、218、220、222、224和226,以及焊料凸起206、228、230、232、234和236分别对应于图1中的半导体管芯结合焊盘108、110、112、114和116,传输线104、118、120、122、124和126,以及焊料凸起106、128、130、132、134和136。
同样如图2所示,宽度240称作传输线220的宽度。作为实例,宽度240可以是20.0微米。如果所有其它参数保持不变,增加传输线宽度通常造成传输线阻抗的相应减少。例如,假定所有其它参数保持不变,对于传输线220和返回接地通路之间10.0微米的距离,将宽度240的值从20.0微米增加到35.0微米将导致传输线220的阻抗从50.0欧姆降低到35.0欧姆。
进一步如图2所示,线间距242表示诸如传输线224和226的两个传输线之间的间距,它分别从连接到半导体管芯结合焊盘214和216的传输线224和226的点附近测量。通过实例,线间距242可以是5.0微米。同样如图2所示,节距244表示诸如焊料球234和236的两个邻近的焊料球的中心间的距离。作为实例,节距244的值可以是250.0微米(应注意,图2中的距离不是按比例画的)。
对于线宽和线间距的给定值,诸如传输线220的传输线的电阻、电容和电感随每毫米长度而改变。例如,对于线宽等于20.0微米而线间距等于5.0微米的情况,传输线的电阻可以是每毫米长度约1.5欧姆。同样,对线宽和线间距采用上述值,传输线的电容和电感可以分别是每毫米长度约0.13到0.15pF和约0.2到0.9nH。
每毫米长度传输线的电感的上述变化,即0.2到0.9nH是极高的,因为传输线的电感取决于传输线和接地返回通路之间的距离。例如,如果诸如传输线220的传输线接近于接地返回通路,每毫米长度的传输线电感将接近于上述电感范围的下端,即0.2nH。另一方面,随着传输线和接地返回通路间的距离增加,每毫米长度的传输线电感接近上述电感范围的高端,即0.9nH。
如以下所描述的,为了使传输线实现并与所需阻抗匹配而适当地通过使用以下描述的本发明的技术控制诸如传输线和接地返回通路之间距离的临界参数。以下将参考图3进一步讨论根据本发明的各种参数的控制,特别是传输线和接地返回通路之间距离的控制。
图3示出根据本发明一个实施例的半导体管芯的剖视图。图3示出安置在下凸起金属(UBM)304上的焊料凸起302。焊料凸起302可以提供半导体管芯300和互连基片(图3中未示出)之间的电连接。UBM304提供让焊料凸起302粘附的表面还提供焊料凸起302和传输线306间的低电阻电连接。以“再分配”工艺制造UBM304。例如,UBM304可以用溅射沉积工艺制造于再分配层上。UBM304可以包括铜铬合金。但是,UBM304可以包括许多金属,诸如铝、镍、钒和铜。
作为背景知识,“再分配工艺”表示一种工艺,借此半导体管芯的周边上的I/O焊盘重新选路到焊料凸起的区域阵列配置。I/O焊盘通过再分配层中制造的互连线(即传输线)被重新选路到区域阵列配置。所得到的焊料凸起的区域阵列配置允许半导体管芯例如采用倒装晶片技术连接到互连基片。
图3还示出传输线306,它设置在电介质层308上。传输线306的第一端子由通路312耦合到半导体管芯结合焊盘313,而传输线306的第二端子耦合到UBM304。在另一个实施例中,可以不使用半导体管芯结合焊盘313。在这种情况中,通路312可以直接将传输线306耦合到互连金属线311,在本实例中互连金属线311制造于金属层六中。传输线306可以通过本技术领域内普通技术人员已知的方法制造于电介质层308的上表面上。例如,传输线306可以采用溅射沉积工艺在电介质层308的上表面上形成图案。通过进一步的实例,可以采用光阻材料图案形成和移离(lift-off)工艺将传输线306形成图案。传输线306可以包括铝或其它金属,诸如铜、铜铝合金或金。传输线306和其它类似地制造于电介质层308上表面上的传输线是再分配层的一部分。
电介质层308可以通过本技术领域内熟知的方法沉积在半导体管芯300的上表面上的钝化层(图3中未示出)上,诸如通过旋转(spin on)工艺。在本实施例中,电介质层308可以包括诸如BCB的聚合物电介质,它具有约3.0到3.5的介电常数。电介质层308的厚度可以是约5.0到10.0微米。在另一个实施例中,电介质层308可以包括二氧化硅。在这种情况中,电介质层308的厚度可以是约3.0微米。
同样如图3所示,电介质层310设置在电介质层308上。电介质层310覆盖电介质层308,还覆盖包括诸如传输线306的传输线的再分配层。电介质层310通过本技术领域内公知的方法沉积在电介质层308上。电介质层310可以包括与电介质层308类似的材料,诸如BCB。
通路312提供传输线306和金属层六中的半导体管芯结合焊盘313之间的连接。通路312可以通过采用光刻工艺或其它本技术领域内普通技术人员已知的方法形成于电介质层308中。在该实例中,金属层六是半导体管芯300内的最后金属层。在其它实施例中,半导体管芯内最后的金属层可以是金属层六之外的金属层。
同样如图3所示,焊料凸起314置于UBM316上。与上述焊料凸起302类似,焊料凸起314也可以提供半导体管芯300和互连基片(图3中未示出)之间的电连接。UBM316向焊料凸起314提供表面以便粘附,并提供焊料凸起314和传输线318之间的低电阻电连接。UBM316包括与上述UBM304类似的材料,并以与UBM304类似的方法制造。
图3还示出传输线318,它设置在电介质层308上。传输线318的第一端子由通路320耦合到半导体管芯结合焊盘321,而传输线318的第二端子耦合到UBM316。传输线318包括与上述传输线306类似的材料,并以与传输线306类似的方法制造。通路320提供传输线318和金属层六中半导体管芯结合焊盘321之间的连接。通路320以与上述通路312类似的方式形成在电介质层308内。半导体管芯结合焊盘321耦合到互连金属线315,在该实例中互连金属线制造于金属层六中。
同样参考图3,距离322表示金属层六中接地返回通路324和传输线306之间的距离。由于电介质层308设置在金属层六和传输线306之间,距离322还表示电介质层308的厚度。在一个实例性实施例中,距离322可以是约5.0到10.0微米。进一步如图3所示,通路326提供金属层六中接地返回通路324和接地线328之间的连接,其中所述接地线328在金属层五中。在另一个实施例中,本发明的传输线的接地返回通路可以在RDL中。在这种情况中,接地返回通路将在与本发明的传输线相同的“平面”内。
同样如图3所示,电介质层330表示半导体管芯300内金属层6和金属层5之间的电介质层。电介质层330可以包括诸如二氧化硅的电介质。进一步如图3所示,距离332表示金属层五中的接地返回通路328和传输线318之间的距离。
传输线306的阻抗受距离322影响,距离322即传输线306和金属层六中的接地返回通路324之间的距离。例如,当距离322等于20.0微米并对于传输线306的40.0微米的线宽,传输线306的阻抗可以是约50.0欧姆。但是,通过增加距离322,传输线306的阻抗可以变成超过50.0欧姆。
对于给定的线宽和厚度,可以通过增加或降低距离322来增加或降低传输线306的阻抗。例如,可以通过增加电介质层308的厚度来增加距离322,其中增加电介质层的厚度有效地增加了传输线306和返回接地通路324之间的距离,即间隙。还可以利用半导体管芯300中诸如金属层五的较低金属层中的返回接地通路增加距离322。例如,传输线318可以利用金属层五中的返回接地通路328。因此,距离332大于距离322,其中距离332即传输线318和金属层五中的返回接地通路328之间的距离,而距离322即传输线306和金属层六中的返回接地通路324之间的距离。因此,对于相同的线宽和线厚度并假定所有其它参数不变,传输线318的阻抗将大于传输线306的阻抗。
根据本发明,诸如图3中传输线306和318的各种传输线的阻抗不仅可以通过使用常规阻抗控制技术进行控制,也可以通过对半导体管芯中每个传输线和其下设置的接地返回通路之间特定距离的设计来加以控制,其中常规阻抗控制技术诸如控制传输线的宽度和厚度。通过使用RDL制造传输线和通过设计每个传输线离下面接地返回通路的距离形成诸如50.0欧姆阻抗的所需阻抗,从而使得传输线和其下接地返回通路之间距离的设计和控制成为可能。
换句话说,通过确定半导体管芯中哪个特定金属层应用作特定传输线的接地返回通路,本发明导致对传输线阻抗的附加控制,这超过了对阻抗的常规控制,其中所述常规控制由控制诸如传输线的宽度和厚度的参数组成。例如,通过选择金属层五用作一个传输线的接地返回通路,选择金属层六用作另一个传输线的接地返回通路,和选择金属层4用作又一个传输线的接地返回通路,可以精细地调整和优化RDL中制造的各种传输线的阻抗。通过特定实例,图3示出,通过选择金属层六用作传输线306的接地返回通路,相对于使用金属层五作为其接地返回通路的传输线318的阻抗,降低了传输线306的阻抗。
这样,本发明形成半导体管芯内接地返回通路的更精巧的设计并考虑设置在半导体管芯的接地线上的RDL传输线。相反地,在常规技术中,不考虑各种金属层中的接地线和由半导体管芯的I/O驱动器启动或耦合到其的任何传输线之间的距离,且不存在本发明有价值的对RDL传输线阻抗的控制。例如,通过合适的设计考虑产生RDL中制造的传输线下的接地线的适当分配,这依次导致所需“深度”处,即所需金属层处,接地线的合适分配,从而导致连接到特定I/O驱动器的给定传输线的精确的阻抗,例如50.0欧姆的阻抗。作为一个有利方面,本发明产生通过降低驱动传输线的I/O驱动器的所需数量和强度而降低制造成本的传输线。
通过本发明的上述描述,表明各种技术可以用于实现本发明的概念而不背离其范围。此外,虽然已参考特定实施例描述了本发明,但本技术领域内熟练的技术人员可以理解,可以在形式上和细节上改变而不背离本发明的精神和范围。所述实施例被认为在所有方面都是示意性而非限制性的。应理解,本发明不限于这里所述的特定实施例,能进行许多重新配置、修改和替换而不背离本发明的范围。
因此,已经描述了再分配层中的控制阻抗传输线。
Claims (23)
1.一种包括半导体管芯的结构,所述结构具有在所述半导体管芯上制作的第一和第二传输线,所述结构进一步包括:
所述第一传输线制作于所述半导体管芯上的再分配层中,所述第一传输线具有离所述半导体管芯中第一金属层中形成的第一接地返回通路的第一距离,所述第一传输线具有对应于所述第一距离的第一阻抗;
所述第二传输线制作于所述半导体管芯上的再分配层中,所述第二传输线具有离所述半导体管芯中第二金属层中形成的第二接地返回通路的第二距离,所述第二传输线具有对应于所述第二距离的第二阻抗;
当选择所述第一金属层和所述第二金属层使得所述第一距离小于所述第二距离时,所述第一阻抗小于所述第二阻抗。
2.如权利要求1所述的结构,其特征在于,当选择所述第一金属层和所述第二金属层使得所述第一距离大于所述第二距离时,所述第一阻抗高于所述第二阻抗。
3.如权利要求1所述的结构,其特征在于,所述再分配层形成于电介质层之上,所述电介质层设置在所述半导体管芯之上。
4.如权利要求3所述的结构,其特征在于,所述电介质层包括苯并环丁烯。
5.如权利要求1所述的结构,其特征在于,在所述第一传输线下的位置处将所述第一金属层接地而形成所述第一接地返回通路。
6.如权利要求5所述的结构,其特征在于,在所述第二传输线下的位置处将所述第二金属层接地而形成所述第二接地返回通路。
7.如权利要求1所述的结构,其特征在于,所述第一传输线耦合到第一焊料球。
8.如权利要求7所述的结构,其特征在于,所述第二传输线耦合到第二焊料球。
9.如权利要求1所述的结构,其特征在于,所述第一传输线的阻抗基本等于50欧姆。
10.如权利要求1所述的结构,其特征在于,所述第二传输线的阻抗基本等于50欧姆。
11.如权利要求1所述的结构,其特征在于,所述再分配层包括一选自铜、铜铝合金或金的导体。
12.如权利要求1所述的结构,其特征在于,还包括沉积在所述再分配层上的电介质层。
13.如权利要求12所述的结构,其特征在于,所述电介质层包括苯并环丁烯。
14.一种结构,其特征在于,包括:
第一传输线,设置在半导体管芯上的再分配层中,所述第一传输线具有离所述半导体管芯中第一金属层中形成的第一接地返回通路的第一距离,所述第一传输线具有对应于所述第一距离的第一阻抗;
所述半导体管芯中的第一互连金属线,所述第一互连金属线由所述半导体管芯的第一I/O驱动器驱动,所述第一互连金属线经由第一通路耦合到所述第一传输线;
第二传输线,设置在所述半导体管芯上的所述再分配层中,所述第二传输线具有离所述半导体管芯中所述第二金属层中形成的第二接地返回通路的第二距离,所述第二传输线具有对应于所述第二距离的第二阻抗;
所述半导体管芯中的第二互连金属线,所述第二互连金属线由所述半导体管芯的第二I/O驱动器驱动,所述第二互连线经由第二通路耦合到所述第二传输线;
当选择所述第一金属层和所述第二金属层使得所述第一距离小于所述第二距离时,所述第一阻抗小于所述第二阻抗。
15.如权利要求14所述的结构,其特征在于,所述第一阻抗还对应于所述第一传输线和设置在所述再分配层中的第三传输线之间的线间距。
16.如权利要求14所述的结构,其特征在于,所述第一阻抗进一步对应于所述第一传输线的宽度。
17.如权利要求14所述的结构,其特征在于,所述第一阻抗进一步对应于所述第一传输线的厚度。
18.如权利要求14所述的结构,其特征在于,所述第二阻抗进一步对应于所述第二传输线和设置在所述再分配层中的第三传输线之间的线间距。
19.如权利要求14所述的结构,其特征在于,所述第二阻抗进一步对应于所述第二传输线的宽度。
20.如权利要求14所述的结构,其特征在于,所述第二阻抗进一步对应于所述第二传输线的厚度。
21.如权利要求14所述的结构,其特征在于,当选择所述第一金属层和所述第二金属层使得所述第一距离大于所述第二距离时,所述第一阻抗高于所述第二阻抗。
22.如权利要求14所述的结构,其特征在于,在所述第一传输线下的位置处将所述第一金属层接地而形成所述第一接地返回通路。
23.如权利要求22所述的结构,其特征在于,在所述第二传输线下的位置处将所述第二金属层接地而形成所述第二接地返回通路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/012,812 US6674174B2 (en) | 2001-11-13 | 2001-11-13 | Controlled impedance transmission lines in a redistribution layer |
US10/012,812 | 2001-11-13 |
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CN100336213C true CN100336213C (zh) | 2007-09-05 |
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US (1) | US6674174B2 (zh) |
EP (1) | EP1444731B1 (zh) |
KR (1) | KR100534048B1 (zh) |
CN (1) | CN100336213C (zh) |
AT (1) | ATE508474T1 (zh) |
DE (1) | DE60239950D1 (zh) |
WO (1) | WO2003043083A1 (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6822327B1 (en) * | 2003-06-13 | 2004-11-23 | Delphi Technologies, Inc. | Flip-chip interconnected with increased current-carrying capability |
US7098518B1 (en) * | 2003-08-27 | 2006-08-29 | National Semiconductor Corporation | Die-level opto-electronic device and method of making same |
US7342312B2 (en) | 2004-09-29 | 2008-03-11 | Rohm Co., Ltd. | Semiconductor device |
DE102005002707B4 (de) * | 2005-01-19 | 2007-07-26 | Infineon Technologies Ag | Verfahren zur Herstellung elektrischer Verbindungen in einem Halbleiterbauteil mittels koaxialer Mikroverbindungselemente |
US7541251B2 (en) * | 2006-02-10 | 2009-06-02 | California Micro Devices | Wire bond and redistribution layer process |
US8946873B2 (en) * | 2007-08-28 | 2015-02-03 | Micron Technology, Inc. | Redistribution structures for microfeature workpieces |
US8193878B2 (en) | 2008-06-24 | 2012-06-05 | International Business Machines Corporation | Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
CN102027633B (zh) * | 2008-06-24 | 2014-11-05 | 国际商业机器公司 | 用于提供具有固定特性阻抗的片上可变延迟传输线的设计结构、结构和方法 |
US8138857B2 (en) * | 2008-06-24 | 2012-03-20 | International Business Machines Corporation | Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
US8410863B2 (en) * | 2008-07-15 | 2013-04-02 | Panasonic Corporation | Slow wave transmission line |
US8659170B2 (en) * | 2010-01-20 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having conductive pads and a method of manufacturing the same |
KR101685057B1 (ko) * | 2010-01-22 | 2016-12-09 | 삼성전자주식회사 | 반도체 소자의 적층 패키지 |
KR101666192B1 (ko) | 2010-02-02 | 2016-10-14 | 삼성전자 주식회사 | 반도체 칩 및 이를 포함하는 반도체 모듈 |
CN102469679A (zh) * | 2010-11-05 | 2012-05-23 | 富士康(昆山)电脑接插件有限公司 | 印刷电路板 |
US9171798B2 (en) | 2013-01-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for transmission lines in packages |
US9711471B2 (en) | 2015-11-18 | 2017-07-18 | Nxp Usa, Inc. | Semiconductor device package, electronic device and method of manufacturing electronic devices using wafer level chip scale package technology |
JP6798252B2 (ja) * | 2016-10-31 | 2020-12-09 | 住友電気工業株式会社 | 高周波装置 |
KR20220019331A (ko) | 2020-08-10 | 2022-02-17 | 삼성전자주식회사 | 패키지 기판 및 이를 포함하는 반도체 패키지 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025647A (en) * | 1997-11-24 | 2000-02-15 | Vlsi Technology, Inc. | Apparatus for equalizing signal parameters in flip chip redistribution layers |
US6048753A (en) * | 1996-04-02 | 2000-04-11 | Micron Technology, Inc. | Standardized bonding location process and apparatus |
US6262473B1 (en) * | 1996-10-17 | 2001-07-17 | Seiko Epson Corporation | Film carrier tape and semiconductor device, method of making the same and circuit board |
US6297553B1 (en) * | 1998-10-30 | 2001-10-02 | Shinko Electric Industries Co., Ltd | Semiconductor device and process for producing the same |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4498122A (en) | 1982-12-29 | 1985-02-05 | At&T Bell Laboratories | High-speed, high pin-out LSI chip package |
JP2833996B2 (ja) * | 1994-05-25 | 1998-12-09 | 日本電気株式会社 | フレキシブルフィルム及びこれを有する半導体装置 |
JP3142723B2 (ja) * | 1994-09-21 | 2001-03-07 | シャープ株式会社 | 半導体装置及びその製造方法 |
JP2546192B2 (ja) * | 1994-09-30 | 1996-10-23 | 日本電気株式会社 | フィルムキャリア半導体装置 |
KR100218996B1 (ko) * | 1995-03-24 | 1999-09-01 | 모기 쥰이찌 | 반도체장치 |
US6072236A (en) * | 1996-03-07 | 2000-06-06 | Micron Technology, Inc. | Micromachined chip scale package |
JP2982738B2 (ja) | 1997-04-04 | 1999-11-29 | 日本電気株式会社 | セラミック・チップサイズパッケージの構造 |
JP3335575B2 (ja) * | 1997-06-06 | 2002-10-21 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
JP3152180B2 (ja) * | 1997-10-03 | 2001-04-03 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6248429B1 (en) * | 1998-07-06 | 2001-06-19 | Micron Technology, Inc. | Metallized recess in a substrate |
US5994766A (en) * | 1998-09-21 | 1999-11-30 | Vlsi Technology, Inc. | Flip chip circuit arrangement with redistribution layer that minimizes crosstalk |
US6078100A (en) * | 1999-01-13 | 2000-06-20 | Micron Technology, Inc. | Utilization of die repattern layers for die internal connections |
US6407450B1 (en) * | 1999-07-15 | 2002-06-18 | Altera Corporation | Semiconductor package with universal substrate for electrically interfacing with different sized chips that have different logic functions |
US6249047B1 (en) * | 1999-09-02 | 2001-06-19 | Micron Technology, Inc. | Ball array layout |
JP4301661B2 (ja) * | 1999-11-12 | 2009-07-22 | 富士通マイクロエレクトロニクス株式会社 | ボールグリッドアレイ構造のデバイスに使用されるコンタクトフィルム及びデバイス実装構造体 |
JP3578964B2 (ja) * | 2000-03-21 | 2004-10-20 | 富士通株式会社 | 半導体装置及びその製造方法 |
-
2001
- 2001-11-13 US US10/012,812 patent/US6674174B2/en not_active Expired - Lifetime
-
2002
- 2002-11-12 CN CNB028221672A patent/CN100336213C/zh not_active Expired - Lifetime
- 2002-11-12 DE DE60239950T patent/DE60239950D1/de not_active Expired - Lifetime
- 2002-11-12 WO PCT/US2002/036207 patent/WO2003043083A1/en active Application Filing
- 2002-11-12 EP EP02780619A patent/EP1444731B1/en not_active Expired - Lifetime
- 2002-11-12 KR KR10-2004-7005462A patent/KR100534048B1/ko active IP Right Grant
- 2002-11-12 AT AT02780619T patent/ATE508474T1/de not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6048753A (en) * | 1996-04-02 | 2000-04-11 | Micron Technology, Inc. | Standardized bonding location process and apparatus |
US6262473B1 (en) * | 1996-10-17 | 2001-07-17 | Seiko Epson Corporation | Film carrier tape and semiconductor device, method of making the same and circuit board |
US6025647A (en) * | 1997-11-24 | 2000-02-15 | Vlsi Technology, Inc. | Apparatus for equalizing signal parameters in flip chip redistribution layers |
US6297553B1 (en) * | 1998-10-30 | 2001-10-02 | Shinko Electric Industries Co., Ltd | Semiconductor device and process for producing the same |
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KR100534048B1 (ko) | 2005-12-06 |
WO2003043083A1 (en) | 2003-05-22 |
EP1444731A4 (en) | 2005-04-06 |
US6674174B2 (en) | 2004-01-06 |
ATE508474T1 (de) | 2011-05-15 |
DE60239950D1 (de) | 2011-06-16 |
EP1444731B1 (en) | 2011-05-04 |
KR20050044326A (ko) | 2005-05-12 |
EP1444731A1 (en) | 2004-08-11 |
US20030193078A1 (en) | 2003-10-16 |
CN1599957A (zh) | 2005-03-23 |
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