CH631291A5 - Verfahren zur stabilisierenden oberflaechenbehandlung von halbleiterkoerpern. - Google Patents

Verfahren zur stabilisierenden oberflaechenbehandlung von halbleiterkoerpern. Download PDF

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Publication number
CH631291A5
CH631291A5 CH833578A CH833578A CH631291A5 CH 631291 A5 CH631291 A5 CH 631291A5 CH 833578 A CH833578 A CH 833578A CH 833578 A CH833578 A CH 833578A CH 631291 A5 CH631291 A5 CH 631291A5
Authority
CH
Switzerland
Prior art keywords
semiconductor
layer
glass
coating
thickness
Prior art date
Application number
CH833578A
Other languages
German (de)
English (en)
Inventor
Madan Mohan Chadda
Original Assignee
Semikron Gleichrichterbau
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron Gleichrichterbau filed Critical Semikron Gleichrichterbau
Publication of CH631291A5 publication Critical patent/CH631291A5/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/134—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being in grooves in the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6928—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H10P14/6929—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing aluminium, e.g. AlSiOx

Landscapes

  • Formation Of Insulating Films (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Glass Compositions (AREA)
CH833578A 1977-09-03 1978-08-04 Verfahren zur stabilisierenden oberflaechenbehandlung von halbleiterkoerpern. CH631291A5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2739762A DE2739762C2 (de) 1977-09-03 1977-09-03 Verfahren zur Passivierung von Halbleiterkörpern

Publications (1)

Publication Number Publication Date
CH631291A5 true CH631291A5 (de) 1982-07-30

Family

ID=6018047

Family Applications (1)

Application Number Title Priority Date Filing Date
CH833578A CH631291A5 (de) 1977-09-03 1978-08-04 Verfahren zur stabilisierenden oberflaechenbehandlung von halbleiterkoerpern.

Country Status (8)

Country Link
US (1) US4202916A (enExample)
JP (1) JPS5444476A (enExample)
BR (1) BR7805571A (enExample)
CH (1) CH631291A5 (enExample)
DE (1) DE2739762C2 (enExample)
FR (1) FR2402303A1 (enExample)
GB (1) GB2003662B (enExample)
IT (1) IT1098444B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2071411B (en) * 1980-03-07 1983-12-21 Philips Electronic Associated Passivating p-n junction devices
IN154896B (enExample) * 1980-07-10 1984-12-22 Westinghouse Electric Corp
JPS57120341A (en) * 1981-01-17 1982-07-27 Toshiba Corp Glass passivation semiconductor device
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
US4544576A (en) * 1981-07-27 1985-10-01 International Business Machines Corporation Deep dielectric isolation by fused glass
DE3247938A1 (de) * 1982-12-24 1984-07-05 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Halbleiterbauelement hoher sperrspannungsbelastbarkeit
US4515668A (en) * 1984-04-25 1985-05-07 Honeywell Inc. Method of forming a dielectric layer comprising a gettering material
FR2631488B1 (fr) * 1988-05-10 1990-07-27 Thomson Hybrides Microondes Circuit integre hyperfrequence de type planar, comportant au moins un composant mesa, et son procede de fabrication
US5176771A (en) * 1991-12-23 1993-01-05 Hughes Aircraft Company Multilayer ceramic tape substrate having cavities formed in the upper layer thereof and method of fabricating the same by printing and delamination
US5882986A (en) * 1998-03-30 1999-03-16 General Semiconductor, Inc. Semiconductor chips having a mesa structure provided by sawing
WO2003025982A1 (en) * 2001-09-17 2003-03-27 Advion Biosciences, Inc. Uniform patterning for deep reactive ion etching
DE102006013076A1 (de) * 2006-03-22 2007-09-27 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleiterbauelement mit Passivierungsschicht und zugehöriges Herstellungsverfahren
US20100025809A1 (en) 2008-07-30 2010-02-04 Trion Technology, Inc. Integrated Circuit and Method of Forming Sealed Trench Junction Termination
US8163624B2 (en) * 2008-07-30 2012-04-24 Bowman Ronald R Discrete semiconductor device and method of forming sealed trench junction termination

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1522201A (fr) * 1961-07-06 1968-04-26 Procédé de fabrication de dispositifs semi-conducteurs à jonction
US3212921A (en) * 1961-09-29 1965-10-19 Ibm Method of forming a glass film on an object and the product produced thereby
US3303399A (en) * 1964-01-30 1967-02-07 Ibm Glasses for encapsulating semiconductor devices and resultant devices
US3546013A (en) * 1961-09-29 1970-12-08 Ibm Method of providing protective coverings for semiconductors
DE1260574B (de) * 1966-03-30 1968-02-08 Telefunken Patent Verfahren zur Herstellung von Glasschichten oder anderen Isolierschichten auf Substratoberflaechen
US3542572A (en) * 1968-06-24 1970-11-24 Corning Glass Works Germania-silica glasses
GB1283769A (en) * 1968-10-09 1972-08-02 Hitachi Ltd Semiconductor device having a passivation film and insulating films on a semiconductor substrate and method of making the same
US3967310A (en) * 1968-10-09 1976-06-29 Hitachi, Ltd. Semiconductor device having controlled surface charges by passivation films formed thereon
US3632434A (en) * 1969-01-21 1972-01-04 Jerald L Hutson Process for glass passivating silicon semiconductor junctions
GB1250099A (enExample) * 1969-04-14 1971-10-20
US3752701A (en) * 1970-07-27 1973-08-14 Gen Instrument Corp Glass for coating semiconductors, and semiconductor coated therewith
US3895127A (en) * 1974-04-19 1975-07-15 Rca Corp Method of selectively depositing glass on semiconductor devices
DE2548736C3 (de) * 1975-10-31 1978-05-18 Jenaer Glaswerk Schott & Gen., 6500 Mainz Composit-Passivierungsglas auf der Basis PbO-B2 Okskö-ab O3) m't einem thermischen Ausdehnungskoeffizienten (200-300 Grad C) zwischen 40 und 60 mal 10"7 / Grad C für Silicium-Halbleiterbauelemente mit Aufschmelztemperaturen von höchstens 600 Grad C
JPS5263160A (en) * 1975-11-20 1977-05-25 Toshitaka Yamagata Forming device for arc and annulus
FR2335951A1 (fr) * 1975-12-19 1977-07-15 Radiotechnique Compelec Dispositif semiconducteur a surface passivee et procede d'obtention de la structure de passivation
JPS535971A (en) * 1976-07-06 1978-01-19 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
GB2003662A (en) 1979-03-14
JPS5444476A (en) 1979-04-07
IT1098444B (it) 1985-09-07
US4202916A (en) 1980-05-13
BR7805571A (pt) 1979-04-10
FR2402303A1 (fr) 1979-03-30
DE2739762C2 (de) 1982-12-02
IT7827273A0 (it) 1978-09-01
GB2003662B (en) 1982-02-24
DE2739762A1 (de) 1979-03-15
JPS6120132B2 (enExample) 1986-05-21
FR2402303B1 (enExample) 1984-06-01

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Owner name: SEMIKRON ELEKTRONIK GMBH

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PL Patent ceased