CH585436A5 - - Google Patents

Info

Publication number
CH585436A5
CH585436A5 CH543975A CH543975A CH585436A5 CH 585436 A5 CH585436 A5 CH 585436A5 CH 543975 A CH543975 A CH 543975A CH 543975 A CH543975 A CH 543975A CH 585436 A5 CH585436 A5 CH 585436A5
Authority
CH
Switzerland
Prior art keywords
register
input
output
word
stages
Prior art date
Application number
CH543975A
Other languages
English (en)
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of CH585436A5 publication Critical patent/CH585436A5/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
CH543975A 1974-04-29 1975-04-28 CH585436A5 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US465014A US3887901A (en) 1974-04-29 1974-04-29 Longitudinal parity generator for mainframe memories

Publications (1)

Publication Number Publication Date
CH585436A5 true CH585436A5 (fr) 1977-02-28

Family

ID=23846167

Family Applications (1)

Application Number Title Priority Date Filing Date
CH543975A CH585436A5 (fr) 1974-04-29 1975-04-28

Country Status (8)

Country Link
US (1) US3887901A (fr)
JP (1) JPS50147836A (fr)
CH (1) CH585436A5 (fr)
DE (1) DE2515099A1 (fr)
FR (1) FR2269149A1 (fr)
IT (1) IT1031724B (fr)
NL (1) NL7504984A (fr)
SE (1) SE7505017L (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038537A (en) * 1975-12-22 1977-07-26 Honeywell Information Systems, Inc. Apparatus for verifying the integrity of information stored in a data processing system memory
US4016409A (en) * 1976-03-01 1977-04-05 Burroughs Corporation Longitudinal parity generator for use with a memory
DE2741050C2 (de) * 1977-09-12 1982-07-01 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum sendeseitigen Erzeugen eines Paritätsbits und zur empfangsseitigen Überprüfung der aus einem Informationswort und einem mitübertragenem Paritätsbit bestehenden Informationsblöcke
US4183463A (en) * 1978-07-31 1980-01-15 Sperry Rand Corporation RAM error correction using two dimensional parity checking
JPS5622300A (en) * 1979-08-01 1981-03-02 Fanuc Ltd Memory check method
US4335460A (en) * 1980-01-28 1982-06-15 International Business Machines Corporation Printer system having parity checking of print hammers using software control
US4335459A (en) * 1980-05-20 1982-06-15 Miller Richard L Single chip random access memory with increased yield and reliability
US4346474A (en) * 1980-07-03 1982-08-24 International Business Machines Corporation Even-odd parity checking for synchronous data transmission
US4433388A (en) * 1980-10-06 1984-02-21 Ncr Corporation Longitudinal parity
DE3716554C1 (en) * 1987-05-18 1988-08-04 Markus Wagner Method and circuit arrangement to secure digital memories
US5218691A (en) 1988-07-26 1993-06-08 Disk Emulation Systems, Inc. Disk emulation system
US5070474A (en) * 1988-07-26 1991-12-03 Disk Emulation Systems, Inc. Disk emulation system
US5191584A (en) * 1991-02-20 1993-03-02 Micropolis Corporation Mass storage array with efficient parity calculation
US6125466A (en) * 1992-01-10 2000-09-26 Cabletron Systems, Inc. DRAM parity protection scheme
US5537425A (en) * 1992-09-29 1996-07-16 International Business Machines Corporation Parity-based error detection in a memory controller
US5434871A (en) * 1992-11-17 1995-07-18 Unisys Corporation Continuous embedded parity checking for error detection in memory structures
US5666371A (en) * 1995-02-24 1997-09-09 Unisys Corporation Method and apparatus for detecting errors in a system that employs multi-bit wide memory elements
US5511164A (en) * 1995-03-01 1996-04-23 Unisys Corporation Method and apparatus for determining the source and nature of an error within a computer system
US5630054A (en) * 1995-04-18 1997-05-13 Mti Technology Center Method and apparatus for storing and retrieving error check information

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3075175A (en) * 1958-11-24 1963-01-22 Honeywell Regulator Co Check number generating circuitry for information handling apparatus
US3183483A (en) * 1961-01-16 1965-05-11 Sperry Rand Corp Error detection apparatus
US3566093A (en) * 1968-03-29 1971-02-23 Honeywell Inc Diagnostic method and implementation for data processors

Also Published As

Publication number Publication date
US3887901A (en) 1975-06-03
DE2515099A1 (de) 1975-11-13
NL7504984A (nl) 1975-10-31
FR2269149A1 (fr) 1975-11-21
IT1031724B (it) 1979-05-10
JPS50147836A (fr) 1975-11-27
SE7505017L (sv) 1975-10-30

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Legal Events

Date Code Title Description
PL Patent ceased