GB1330941A - Data processing system - Google Patents

Abstract

1330941 Digital computers INTERNATIONAL STANDARD ELECTRIC CORP 27 May 1971 [18 June 1970] 17515/71 Heading G4A A digital electric data processing system comprises a memory MEM holding first data words and at least one instruction word holding first information and an address which are used to find, in combination with information in a second word, a slice in a first word. The system includes a plurality of tables of first data words, each table being formed by a plurality of adjacent non-overlapping slices of equal length. The first information comprises a P bit binary number with decimal value M determining a slice length L = 2<SP>m</SP> and the address gives access only to the table containing slices of this length. The second word indicates the position of the slice in the accessed table. To define N different slice lengths in a 2<SP>n</SP> bit word where L = 2<SP>m</SP>, P bits are required where 2<SP>p-1</SP> < N # 2P. Using this formula the number of bits in the instruction word required to define a slice can be reduced. The Apparatus.-This comprises the memory MEM and an arithmetic and control unit ACU, the former holding 16 bit instruction words and 16 bit first data words. The data words are formed of equal slices SL0-SL3, and the data words are formed by slices of equal length being in a same table of the memory. Operation.-Before a load slice instruction is received, index register X is loaded from memory MEM with a second data word which comprises the address of the first word in a table followed by a position address of a slice in the first word. Then a 16 bit load slice instruction, comprising 67 function code bits, 2 bits indicating the slice length (i.e. 1, 2, 4 or 8), and 7 bits which, in combination with the second word, locate the desired slice, is read from memory MEM. The apparatus operates in up to four cycles, F, 1, A, and B, in each of which four timing pulses are generated in succession. The two slice length bits are transferred to a slice decoder SDEC at the same time as bits X12-X15 from the X register. The SDEC contains a first gate to determine the length of the slice from the two bits. The first and last positions of a slice in a word are obtained by completing N-M slice position indicating bits at the right hand with O<SP>1</SP>S and 1<SP>1</SP>S respectively until an N bit number is obtained. When the first and last bit positions of a slice have been determined, mask signals are generated in circuit MGC.