DE2129891A1 - Data processing system - Google Patents

Description

Patent attorney

Dipl.-Phys. Leo Thul

7 Stuttgart

J. Janssens 2-23-1

INTERNATIONAL STANDARD ELECTRIC CORPORATION, NEW YORK

Data processing system

The invention relates to a data processing system with a memory for storing a number of data words and one Number of command words, at least one of which is an address for locating a data word and a first piece of information has, with the in the found data word in connection with a second piece of information, a word part determined by the first and second pieces of information can be found.

Such a data processing system is already off the Belgian patent specification No. 736 922 known. Contains there the command word not only contains the first piece of information, which specifies the length of the word part - but also the second piece of information, which shows the position of the word part. This means that both types of Information.Bits must be reserved, for example four bits to indicate the word part length in words with 16 bits and further .. four bits to indicate the position of the word part. According to Belgian patent specification No. 736 923 it is possible to to keep the number of bits reserved for this purpose less than eight, for example to limit it to 7, through Use of a logic circuit that separates the two types of information from the two bit rows with fewer bits generated.

The object of the invention is to provide a data processing system of the type mentioned above, on June 14, 1971

Krü / Mr - / -

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fewer bits are required in a command word for the stated purpose are. According to the invention, this is achieved by that the second information is entered in a second data word, and that means are provided which the word part by means of extract the first and second information from the first data word.

Another embodiment of the invention is characterized in that that for a given length of the word part the position of the word part characterizing information the position of the word part in a series of non-overlapping parts of the word, which are defined in the first data word contains that the position of the word part identifying information from one of Ii-M bits consists that the first data word has a number of bits,

N-I N

which is greater than 2 and therefore about 2, and that the

M.
Word part has 2 bits, the word part length being P bits

P-ί P given and P is determined by 2 - £ r N - ^ f - 2.

Another object of the invention is to provide a data processing system of the type mentioned to indicate the particular 'for the simple, successive determination of a number of parts of a word is suitable. This task is solved by that tables formed from first data words are provided in the memory are, in each of which the word parts of the data words have the same length, and that the second data word is formed by an additional address consisting of a Binary number and a following word part length information consists of N-M bits, this total information being a position ' represents the address of the word part in one of the tables.

According to a further embodiment of the invention, before the Processing of the command word the second data word in one Register is stored and is used for successive reading of the word parts of the table, the inside of the second data word is reduced by 1 if a word part is determined

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has been.

According to a preferred embodiment of the invention, the Data processing system on a number of tables from first data words, each table by a number of adjacent, non-overlapping word parts of the same length is formed. Each of these parts of the word can with the help of a Command word can be determined. which one the word part length L = 2 determining binary number consisting of P bits with the decimal value M and an address that gives access to a provides such a table that only has word parts of this length. To determine such a part of the word, also uses a second data word, which in a Index register is stored and shows the position of the value part in the table * This position is determined by the address of a first word in this table and by, given the number of a first word part in this first word, this being

N number has N -M bits if the length of the first word is 2 amounts to.

The invention will now be explained in more detail using an exemplary embodiment.

The data processing system shown in Pig. 1 has a Memory MEM and a computer * and control device AOU.

The memory MEM is used to store a number of command words each consisting of 16 bits (LSX) and a number of data words from 16 bits each (DW1 and DW2) · ,, each D & tenwort DW1 is formed by a sequence of adjacent, non-overlapping word parts of the same length, for example SLO to SL3, with those formed by word parts of the same length Data words are each contained in a table of the memory.

The computing device of the device ACü has a register M for 16 bits, an accumulator A for 16 bits, eiaa

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address register Y for 16 bits, an instruction counter P for 16 bits for storing the address of an executed or to be executed command, an index register X for 16 bits and an adder circuit AD.

The control device of the device ACU consists of a control circuit CD for controlling the various Operations, a register P for 7 bits for storage of the operation code of an instruction, a buffer register MRB for 2 bits, a word part register S for 16 bits, a bistable circuits having BPCY, BICY, BACY and BBCY Phase register PR, a function decoder FDEG zar decoding the function or operation code of a command word, a word tell decoder SDEC and a mask generator MGC together.

The inputs of the cells 00 - I5 of the register M are connected to the outputs of the corresponding output cells 00 - 15 of the. SpeicheisMEM connected. The inputs of the cells 00 of the register P are connected to the outputs of the corresponding cells 00-06 of this memory MEM :. The outputs of said cells 00-15 of the register M are also connected to corresponding Addiereingängen agoo - the adder circuit AD _f connected via AND circuits GOOO-GOI5 AGI5 to be by the output signal of the control circuit CD CCoE controlled. The other inputs QOO-Q14 of the adder circuit AD are connected to the corresponding outputs of cells 00-14 of the index register X via AND circuits GlOO-Gl14 which are controlled by the output signal ccl of the jam circuit CD. The 16 outputs of the analog circuit AD are connected to the inputs of the corresponding cells ÖO-15 of the register Y via AND circuits G200-G215, which are controlled by the output signal cc2 of the control circuit CD. The register Y-stt-access to the memory MEM.

-A

The cells 07 and 08 of the register M are to the corresponding Cells 07 and 08 of the buffer register MRB connected via AND circuits G207 and G208, which are generated by an output signal cc3 of the jam circuit CD can be controlled. The cells 09 15 of the register M are to the corresponding cells 00 of the Register Y connected via AND circuits G4O9 - G4l5, which by an output signal cc4 of the control circuit CD being controlled. .

The cells 07 and 08 of the buffer register MRB are connected to the respective input wires m07 and m08 of the partial word decoder SDEC via AND circuits G507 and G508 which are controlled by an output signal cc5 of the control circuit CD. The memory cells 12 - 15 of the register X are connected to the corresponding input wires xl2 - xl5 of the same word part decoder SDEC via AND circuits G512-G515, which are controlled by the same output signal cc5 of the control circuit CD i The output wires fbO-

fb] 5 and IbO - IbJ of the word part decoder SDEC are with the Mask generator MGC connected, the outputs of which are mkOO - mkl5

) control the corresponding AND circuits G600 - G615. These AND circuits connect cells 00-15 of register M with cells 00 - I5 of the WorttelL register S and are furthermore by an output signal cc6 of the control circuit CD controlled. ■ · '· ■ ·.

ι The outputs of cells 00-06 of register P are to the Function decoder PDEC connected, its outputs are connected to the control circuit CD. The control circuit CD provides the aforementioned output signals cc0-cc6.

It should be noted that only those necessary to understand the Invention absolutely necessary parts of the data processing system are shown and described.

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The data processing system is designed so that it can handle every executes the command stored in the memory MEM in a minimum of one and a maximum of four processing cycles P, I, A and B, each cycle having a duration of, for example, one microsecond having. During each of these cycles there is a relevant one of the bistable circuits BPCY, BICY, BA.CY and BBCY of the phase register PR in their 1 state, each bistable circuit associated with a cycle is set to its 1 state at the end of the previous cycle and in their 0 state at the beginning of the associated cycle is reset by the control circuit CD.

The one at the 1 output of a bistable that is in the 1 state The circuit generated pulse is a one microsecond cycle pulse. During each such pulse, four successive time pulses TO1 to T04 are of the same length generated in the control circuit CD. The time pulses TOl - T04 of cycles P, I, A and B are in the flow charts of the Figures 2 and 3 shown, namely in Figure 2 the time pulses PTOl, - FT04 and in Figure 3 the time pulses ITOl - IT04, ATOL - AT04 and BTOl- BT04. The fact that these time pulses are shown with different lengths is irrelevant.

With reference to FIG. 1 and the flow charts in FIGS. 2 and 3, the mode of operation of the data processing system in connection with the execution of a command! Described in more detail below, which allows the determination of a word file in one of the above-mentioned tables of the memory MEM and the storage of this word part in an accumulator A. This command is. The command word LSX, which. / Is formed by the bits FCOO - FC06 forming the puncture code, by the length of the word parts to be identified by the bits M07; and Μθ8 _Λ and by the bits forming an address YB09.-YBl5 is formed, whereby in connection with J

-T- J. Janssens 2-23-1

information stored in an index register X Data word is contained, the desired word part in the word parts of the extended length having. can be found. It is therefore believed that during the processing of a previous command a data word has been stored in the index register X by the memory MEM, this data word being represented by the bits XO-Xl 5 is marked, which form the number or number of the word part to be determined in a memory table. This data word may an additional address of a word in a table and a subsequent location address of a word part in the contain the latter word. As will be explained in more detail later, the additional address is at least determined by the bits XO - XIl and formed at most by the bits XO- Xl4, while the partial word address is formed by the remaining bits.

During the execution of the last cycle of the command which immediately precedes the command word LSX, reading of the memory, MEM, is started. Here the memory word at the one stored in register Y and in program counter P. Address YA read out. The moment the last Cycle ends, registers M and F are cleared and will those contained in the phase register PR and an F or fetch cycle associated bistable circuit BFCY is set in its 1 state by the control circuit CD. As a result an F or fetch cycle is started in which four successive time pulses FTOl-FT04 by the control circuit CD can be generated.

During the first time pulse FTOl of the fetch cycle the 16-bit '^ instruction, which is stored in the memory MEM by means of the in the register Y stored address YA was addressed in the register M and the 7-bit function or operation code of this command received in register F. Assume that this command dTirch the T-SJit-Funktlonsexsdle indicating the above command LSX FCOO - FC06, through the bits MÖf, MöS fur

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Part of the word length display and the β-bit address YB09 - YB15 formed will.

The word part length is identified by the 2 bits M07 and MO8 in the command word, because this enables 4 different word part lengths to be determined according to the formula L = 2 in a 16-bit or 2-bit word, where M = M07 -2 ¹ + MO8 ■ · is. If MOT MOB = 00, 01, 10 and 11, the corresponding word part lengths are 1, 2, 4 and 8.

To generally N different word part lengths in one 2-bit word to be identified according to the formula L = 2, P bits are required, where P is indicated by

PI ρ
2 <N * ^ 2.

It should be noted that the identification of the Word part lengths in the command word in the above-mentioned manner Saving of bits is achieved.

The 7-bit function code FCOO - FCO6 is used in the decoder FDEC is decoded and thereby becomes one of the outputs of this decoder activated. It is assumed that the LSX output is activated will. This indicates that the command is the command word LSX 1st. After the control circuit CD the activated output LSX detects it, it takes the necessary steps Control the execution of the various operations identified by this command.

During the above-mentioned first time pulse FTO1 of the fetch cycle, the cells in the corresponding cells 07 and 08 of the register M stored bits MO? and M08 via the AND circuits G3O7 and G308 under control of the output signal cc3 of the control circuit Ci) to the buffer register Transfer MRB.

During the second time pulse PT02 of the fetch cycle and under control of the output signal cc5, bits M07 and M08 from the buffer register MRB through the AND circuits G507 and G5O8 and the inputs mO7 and mO8 to the word part decoder SDEC are transmitted while bits X12 to XI5 from register X via the AND circuits G512-G515 and the inputs xl2-xl§ to the same word part decoder SDEC.

The word part decoder SDEC has a (not shown) first logic circuit for calculating the length L of the word part from the received bits M07 and MO8. These first logic circuit contains 4 AND circuits, which generates the following output signals when the word part length equals 1, 2, 4 and 8 bits. These signals have the BOOLE punctures: XE12 = EBÖ7 LBO8, XE13 = LBÖ7- LBO8, XE14 = LB07 «LBÖ8 and XEI5 = LB07 · LBO8.

For each of these word part lengths 1, 2, 4 and 8 a corresponding table is provided in the memory MEM, which table consists of 16-bit words from 16, 8, 4 and adjacent, non-overlapping word parts. Of course, the partial word position within such a 16-bit word can be identified by 4, J>, 2 and 1 bits, namely by the bits X12-XI5, XI3-XI5, X14-XI5 and XI5. Depending on the length of the word part to be determined, a variable number of bits of the data word stored in the index register is required to identify the word part position in a word of a memory table. The same applies to the additional address, which forms part of the data word stored in the index register, because this additional address depends on the length of the word arrow 1,2,4 and 8 to be determined by the bits XO - XIl, XO - X12, XO - Xl ? and XO - X14 is formed.

In other words, the additional address in the im

N 4 / index register X stored word with 2 = 2 = 16 bits

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12 + M bits, while the word part position information N-M or has 4 - M bits.

Of the N-M or 4, 3> 2 or 1 bits that characterize the partial word position in a 16-bit word, the positions of the first and the last bit of the word part in this 16-bit word + by completing these N-M bits on the right-hand side with zeros or ones until an N-bit or 4-bit number is achieved.

For example, if L = 2, one word sub-position among 8 possible adjacent non-overlapping positions becomes in one l6rBit> Wbrt of a table marked by XI3, Xl4, X15. The first bit is then in position XI3 Xl4 Xl * jO, and the last bit is in position XI3 Xl4 X151. For the case XI3 Xl4 Xl5 = 011 the 2-bit word part is in the 2-bit position 3 of the 16-bit word, while the first bit of this word part is in position 0110 or 6 and the last bit this part of the word is in the position of Olli or 7 of this word.

For example, if L = 8, the sub-word will be below 2 possible positions in a 16-bit word identified by XI5. The first and last bit is in position XI5OOO or XI5111. For the case XI5 = 1 is the 8-bit word part in the 8-bit position of the 16-bit word while the first and last bit of this word part is in position 1000 or 8 or 1111 or 15 of this word.

The bits FBO - FB3 and LBO - LB3 of the 4-bit numbers characterizing the positions of the first and last bits of a word part in a 16-bit word have, taking into account the Predicted following values when L = I or XE12 = 1, L = 2 or XE13 = 1, L = 4 or XEl4 = 1, L = 8 or XEl5 = 1

+ indicating numbers

- 11 J. Janssens 2-23-1 9 19 QR QI

L. XE12 PBO FBI FB2 • FB3 EBO EBl LB2 LB3 1 XE13 X12 X13 X14 X15 " Xl 2 X13 X14 X15 2 XEl4 X13 Xl4 X5 0 X13 xi4 X15 1 4th XE15 Xl4 X15 0 0 X14 X15 1 1 8th XlS 0 0 0 X15 1 1 1

The word part decoder SDEC has a (also not shown) second logic circuit on which for the above Bits FBO - FB3 and LBO - LB3 and which is based on the table above. This second logical one The circuit supplies the following signals, which are shown in BOOIE form and at the outputs IbO - Ib3 and fbO- fb3 occur:

FBOs LBOS (ΧΕ12 · Χ12 + ΧΕ13 · Χ13 + ΧΕ14 * Χ14 + ΧΕ15 · Χ15) · ΟΟ5 FBlH (XE12-X13 + XE13'X14 + XE14-X15) «ec5 LBl = (XE12 · XI3 + XEI3» X14 + XE14- X15 + XE15) cc5 FB2H (XE12'Xl4 + XE13rX15); cc5
LB2S (XE12-'Xl4 + XE13-X15 + XEl4rXE15) * cc5 FB3 = (XE12 »X15) 'CC5
LB3s (XE12'X15 + XE13 + XE14 + XE15) 'CC5

the

It should be noted that the above-mentioned logic circuits have not been shown because they can be appropriately constructed in accordance with the BOOIE ¹ function.

As described above, the first and

N '

last bits of the word part in a 2-bit word by adding of the bits indicating the N-M word sub-position on the right-hand side with M zeros or ones until one N-bit number is obtained. In other words, the locations of the

N first and last bits of the word part in a 2-bit word are each given by an N-bit number, which is a Function of the word sub-position in this word is. this function there is a multiplication that characterizes the partial word position -

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the (N - M) -bit number with 2 ^M , which by adding an N-bit constant 0000 .bzw. 1111 is followed. These constants are only 0000 or 1111 if the first part of a word begins at the beginning of this word. For the first bit of a word part, this constant is generally a function of the position of the first bit of the first word part in relation to the beginning of this word, while for the last bit of a word part this constant is also a puncture of the word part length.

After the positions of the first and last bits of a word part in a 16-bit word are determined in the manner described above has been, mask signals are generated in the mask generator MGC in order to convert this word part from this a number of word parts extract containing 16-bit word. This is done during the second time pulse PT02 of the fetch cycle carried out by means of the mask generator MCC, which consists of a logic circuit that generates the output signals MKOO - MK15. The inverse signals MK00-MK15 have the following BODLE form:

MKOÖ = FBO + PBl + PB2 + FB3

MKÖT = PBO + -FBl + PB2 + ΕΒ "0 · ΕβΤ · ΕΒ2" · ΕΒΤ ■

MKÖ2 = PBO + PBl + FB2-FB3 + LBÖtLBT-LB2 " WÖ3 = PBO + FBl '+ LBÖ'EbT (LB2" + LB5) MKÖT = PBO + PBl (PB2 + FB3) + LBÖrLßT MKÖ5 = PBO + FB1 * FB2 + LBO (LET + LB2 «LB3) MÖ6 = PBO + PB1; PB2 · ΡΒ3 + EEÖ (EBT + ES?) MKÖT = PBO + LBÖ (EST + LB2 ~ + W3)

WGB = FBO (PBl + PB2 + FB?) + EBÖ "

MKÖ9 = PBO (PBl + FB2) + LBÖ + LBT * LB2.-LS5 WW '= PBO (FBl + FB2-PB3) + EBÖ "+ ΕβΤ · ΕΒ2" WTT = PBO'PBl + LBO + LBl (LB2 "+ LB3 ) MKT2 = PBO? PB1 (PB2 + PB?) + LBÖ + LET * PBO-PBl! FB2 + LBÖ + EBT + LB2-LB3

PBOiPBl · ΡΒ2 · ΡΒ3 + LBÖ + LBl + LB2 + L&T + LB2 "+ LB3

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If, for example, the first bit of a 4-bit word part is in position 1000 or 8 and the last bit of such a word part is in position 1011 or 11, then the table above shows that the output signals MK08 are MKIl preparation signals, while the MKOO - MK07 and MK12 - MK15 are blocking signals. The signals MKOO te MKl5 appear on the output wires tnkOO - mkl5j which control the AND circuits G6OO - G615.

The BOOLE punctures mentioned above are MKOO - MK15 while looking at the following table

0 0 0 0 0

1 0 0 0 1

2 0 0 10

3 0 0 11

4 0 10 0

5 0 10 1

6 0 110

7 0 111

8 ίο 00

9 10 0 1

10 10 1 0-1 1 1 1 0 0 1 1 0 1 1 1 1 0 ι ι ι ι and obtained by writing the condition that should be fulfilled for each bit position so that this bit outside of the word partjd.h. either on the left side of the position of the first bit of a word part or on the right side of the position of the last bit of this word part.

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For example, a bit in position 5 (0101) is placed outside a word part if it is on the left side of a word part which has 6, 1, ... or 15 as the position of the first bit; this is the case when FBO + FBl * FB2 = 1. This bit can also be on the right-hand side of a word part which has 0, 1, ... or 4 as the position of the last bit; this is the case when LBOr (LB1 + LB2) = 1.

This means that a bit in position 5 is outside a part of a word set if the signal MK05 = FBO + FBl? FB2 + FB2 + LBO (LB1 + LB2) = 1. Therefore MK05 = 1 if there is a bit in the Position 5 is within a part of a word.

During the second time pulse FT02 of the fetch cycle, envelopes are finally placed in cells 00-08 of register Y. intervened, and those in cells O9-I5 of register M stored bits YBO9-YBI5 become cells 09-15 of this register Y via the AND circuits G4O9 - G4l5, by an output signal cc4 of the control circuit CD controlled. The address formed in this way in register Y is called YB.

- During the 3rd time pulse FTO3 of the pick-up cycle, the Counter P counted down and reading of the memory MEM started. Here, the memory word is stored in the register Y stored address YB read out.

During the 4th time pulse FT04 of the fetch cycle, the bistable circuit BTCY brought into its 1 state while the register M is cleared by the control circuit CEJ.

In response to the setting of the bistable circuit BICY, a cycle for what is known as indirect addressing is sharpened, with the control circuit during this cycle. ^v CD 4 successive time pulses ITOL - IT04 generated

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will.

During the first time pulse ITOl, the 16-bit word, which is stored in the memory MEM by means of the in the Y register Address YB had been addressed in register M received. The read out Woct YCOO - YC15 is an address and is in particular the base or the first address of a memory table from words which are each formed by adjacent non-overlapping word parts, which are formed by the bits M07 and M08 identified in the above command word LSX Have length L. This base address YCOO - YC15 forms the first part of the effective address of the word in of the above table, which contains the desired word part, while the second part of this effective address is the additional address, which is saved by the bits XO - XIl, XO - X12; i XO - X13 or XO - Xl4 is formed. As has already been mentioned, the number of bits of the additional address depends on the length of the address to be determined Part of the word.

During the second time pulse IT02 of the cycle for the indirect addressing becomes the effective address mentioned above by adding the numberι which by the one on the left bits XO - XIl, XO - X12, XO - XlJ or XO - X14 is formed to the bits of the address stored in cells 00 - 15 of the M register. When adding the procedure is such that for the Pall L = I or XE12 «1 the Bit XO to bit YCOO, bit XO to? Bit YCOl, bit XO to Bit YC02, the bit XO to the bit YCOJ and the bits XO - XIl to the bits YC04 - YCI5 are added, and that for the Pall L = 8 or XEI5 s 1 the bit XO to the bit YCOO and the Bits XO - Xl4 are added to bits YCOl - YC15.

It should be noted that the bits XO - XIl, XO - X12, XO - XI3 or XO - Xl4 Number formed by XO values

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is added so as not to change the designation of the number must, where this denotation is given by XO - ι.

The above-mentioned editing operation is performed in the adding circuit AD, to which the bits YCOO - YC15 and XOO ■ - ■ Xl4 from the registers M and X via the AND circuit GOOO - GO15 and GlOO - Gl14 are transmitted, which through Output signals ccO and ccl of the control circuit CD controlled will. The bits YGOO - YCI5 are the addition inputs AGOO - AGI5 of this adder circuit AD or, more precisely / their adder AC- supplied. The ones at the entrances' QOO-Q14 of the adder circuit AD occurring bits XO-X14 of the register X are the corresponding addition inputs the adder circuit AC is supplied through a logic circuit GA. This logic circuit provides the following output signals, which are shown in BOOLO form, and the addition inputs ADOO - ADI5 of the addition circuit AC are fed:

ADOO = X0-.XE12 + XOrXElJ + X0'XEl4 + XO-XEI5 ADOl = Χ0 · ΧΕ12 + XOfXElJ + ■ Χ0. ΧΕΐ4 + X0XE15 AD02 = X0-XE12 + XO'XEIJ + X0XE14 + XIXEI5 ADS) J = X0-XE12 + XOiXElJ + XlrXEl4 + X2XE15 AD04 = Χ0 · ΧΕ12> XO'XEIJ + X2-XE14 + XJXE15 ADO5 = Χ1 · ΧΕ12 + Χ2 · ΧΕ1 ^ + .Χ ^ .- XElfS + .Χ4ιΧΕΪ5 ADOe = Χ2ίΧΕ12 + X3 * XE1J "+ Χ4 · ΧΕΐ4 * X5? XE15 ADO? = XJtXE12 + X4? XE1J + X5iXEl4 + X6; XE15 ADO8 = X #! XE12 + X5 # XE1J + X6 * XEl4 + X7 * XS15 ADO9 = X5 «XE12 + X6fXElJ + X7.-XE14 + X8-XE15 ADlO = X6? XE12 + X7-XE13 + X8 * XEl4 + X9 * XE15 ADIl = X7 »XE12 + X8-XE13 + X9? XEl4 + X10'XE15 AD12 = X8? XE12 + X9? XE13 + X10? XEl4 + XII-XEI5 ADI3 = X9-XE12 + -XlOrXElJ + Xllr, XEl4 + X12 * XE15 AD14 = X10VXE12 + XIl? XElJ + X12 · ΧΕΐ4 -f X13 * XE15 ADI5 »X11> XE12 + X12.0CE13 + XlJ * XEl4 + X14-XE15

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After the addition operation is performed, the resulting effective address YD becomes the register Y via the AND circuits G200-G215 transmitted, which are controlled by an output pulse cc2 of the control circuit CD.

During the 3rd time pulse IT03 of the cycle for indirect Addressing starts reading the memory MEM. The word at the effective address YD is read out here.

During the 4th time pulse IT04 of the cycle for indirect Addressing the bistable circuit BACY is brought to its 1 state, while the register M is cleared. The bistable circuit BACY indicates in its 1 state, ' that a Α cycle must be started by the control circuit CD.

During the first time pulse ACOl of the Α cycle, the 16-bit word of the above table, which is stored in the memory MEM was addressed by means of the address YD stored in register Y, received in register M. This word is through a number of consecutive, non-overlapping word parts, for example SLO-SL3, are formed.

During the second time pulse AT02 of the Α cycle, a special word part of the last mentioned, in register M stored word to the word part register S via AND circuits GCOO - GC15 and under control of the above, Mask signals mkO-mkl5 present at the outputs of the mask generator MGC and one at an output of the Control circuit CD transmitted output signal cc6 occurring. During the 3rd time pulse AT03 of the Α cycle the operation for shifting the word part stored in register S into the rightmost position of this register is started and possibly continued during the 4th time pulse ATQ4. At the end of this time pulse AT04 becomes the

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bistable circuit BBCY set to allow the so-called Start B cycle. During this cycle, four successive timing pulses are provided by the control circuit CD BTOl - BT04 generated.

During the first time pulse BTO1 and the second time pulse BT02, the above-mentioned shifting operation is possibly carried out continued, and at the end of the time pulse BT02, the address stored in the program counter P becomes Transfer register Y.

During the 3rd time pulse BT03, the content of register S is transferred to register M in a manner not shown but is obvious / and then the reading of the memory MEM started. The word is read out at the address stored in register Y.

Finally, during the last time pulse BT04, the Transfer the content of the register M to the accumulator A. The bistable circuit BPCY is set, and the register M and F are deleted.

As mentioned above, the content of the Register X which is formed by an additional address and a subsequent word part location information, also as Number of a word part in a table, which by the same length that is specified in the command, having word parts is formed. This makes programming easier because a programmer has to designate a predetermined word part of a predetermined length only an instruction for storing the number of the desired word part in the index register and a subsequent command (for example LSX) for specifying the length of this desired word part needs to write. For example, if in a table the part of the word with the number 13, i.e. the 14th part of the word,

V- 109884/164 5

and the longer one is to be determined, is stored in the index register X the following number is stored:

0000000 0 0000 1101.

At the same time, the length 8 is specified in the LSX command. Since the word part length is 8, the content of the register X can be divided into an additional address

0-0 0 00 000 0 000110,

{dit identifies the table with the word with the number 12 (13th word) of the word parts with the length 8, and in the display of the word part with the number 1 (2nd word part) in the last word.

If the word part with the number 13 and the length 2 is to be determined, the same information as in the previous example is stored in the above-mentioned index register, while the length 2 is identified in the LSX instruction. Since the length is 2, the content of the register X can be divided into the additional address ooooooo-oo QO Oi / _d / _fc

the word with the number 1 (2nd word) the * word parts with the Length 2 table, and in

101,

the part of the word with the number 5 (6th part of the word) in the latter Word indicating.

Likewise, the successive determination or the successive one becomes Reading out the word parts of a table is made easier because it is sufficient to read the content of the index register X count down by 1 each time a word part has been determined.

109884/1645

Claims (20)

- 20 J. Janssens 2-23-1 ο 1 ο η ο η -ι Claims /! ^ Data processing system with a memory for storing a number of data words and a number of command words, at least one of which has an address for finding a data word and a first piece of information and second information of a specific word part can be found, characterized in that the second information (X12-X15) is entered in a second data word (XOO - X15) and that means (MGC) are provided which convert the word part by means of the first (P) and extract second information from the first data word. 2.Data processing system according to claim 1, characterized in that the first information angi-fct the length of the word part and the second information the position of the word part in the first data word. ^ .Data processing system according to claim 2, characterized in that for a given length of the word part the information characterizing the position of the word part determines the position of the word part in a series of non-overlapping word parts (SL0-SL3) contained in the first data word " are. 4.Data processing system according to claim 3j, characterized in that the information identifying the position of the word part comprises a number of NM bits which N-I N greater than 2 and therefore about 2 and that the word- M.
part has 2 bits, where the word part length is represented by P bits PI P
and P is determined by 2 <N * C2. 5.Data processing system according to claim 4, characterized in that the position of the first bit of the word part in the first data word is given by a first number of N bits 109884/1645 - 21 - J.Janssens 2-2J-1 is the first function of the word sub-position in the first Data word is. 6.Data processing system according to claim 4, characterized in that the position of the last bit of the word part in the first data word is given by a second number of N bits, which is a second puncture of the word part position in the first data word. 7.Data processing system according to claim 5 *, characterized in that each of the first and second punctures includes a multiplication of that number by 2, which characterizes the position of the word part consisting of NM bits, and a first or second constant of N bits connected to it, resulting in derives said first and second numbers from N bits. Data processing system according to Claims 5 and 7 *, characterized in that the first constant is a puncture of the position of the first bit of the first word part with respect to the beginning of the first data word. 9. Data processing system according to claims 6 and 7 » characterized in that the second constant is a puncture of the position of the first bit of the first word part in relation to the beginning of the first data word and the length of the word part. ^ .Data processing system according to claim 7 or 8, characterized in that the first number of N bits is formed by that number which indicates the position of the word part consisting of NM bits, and by M following zeros. 11. Data processing system according to claim 7 or 9> characterized in that the second number of N bits is formed by that number which indicates the position of the word part consisting of NM bits, and by M following ones. 109884/16 45 '/ - - 22 years Janssens 2-23-1 12. Data processing system according to claim 5 and 6, characterized in that means (SDEC) are provided, which consist of the word part length information consisting of P bits and the word part position information consisting of NM bits on the N resulting bits (FBO-FBU ₃ LB0- LB3) Calculate each of the first and second numbers, each consisting of N bits. 13. Data processing system according to claim 12, characterized in that the means (SDEC) have a first gate circuit which, after receiving P bits (MO7-M08) at its inputs, generates signals (XE12-XEl5) characterizing the word part length, which together with the NM hits are fed to the inputs of a second gate circuit, which generates the mentioned resulting bits of the first and second number at its ZN outputs (fbO-fb3, IbO-Ib3). 14.Data processing system according to claim 12, characterized in that the means (MGC) extracting the word part from the first data word derive signals (MKOO-MKI5) from the resulting bits of the first and second number for extracting the word part from the first data word. 15.Data processing system according to one of claims 3 to 14, characterized in that tables formed from first data words are provided in the memory in which the word parts of the data words have the same length. 16.Data processing system according to one of claims 1 to 15, characterized in that the second data word contains additional address information for locating the first data word. ^: -A 109 8 84/16 45 - 23 J. Janssens 2-2 ^ -1 17. Data processing system according to claim 15 and 16, characterized in that the address contained in the command word is used to find the table which is provided for the word parts identified in length in this command word, while the additional address of a first word is in this table. 18.Datenververarbeitunganlage according to claim 17, characterized in that the address contained in the command word is used to find another address of N bits, which forms the start address of the table, and that to find the address of the first word in the table, this other address and the additional address can be assembled by adding the same digit bits after converting the additional address into an N-bit address by completing with bits up to the character bit at the highest digit. 19.Datenververarbeitunganlage according to claim 4 and 17 , characterized in that the second data word is formed by an additional address, which consists of a binary number and a subsequent word part length information from NM bits, this total information represents a location address of the word part in one of the tables. 20.Datenververarbeitunganlage according to claim 19 * characterized in that the second data word is stored in a register before the processing of the command word and that for successive reading of the word parts of the table the content of the second data word is reduced by one if a word part has been determined. is. 2. Data processing system according to Claim 20, characterized in that the register is a computer index register. 109884/1645