DE1774943C3 - Data entry device. Eliminated from: 1474025 - Google Patents

Description

connected to the second memory (3867) 30 The object on which the invention is based is

is that the information collected in the third memory (3845) is data from a low bit rate.

th groups of bits in the second memory to convert into a high bit rate,

(3867) for complete data sets and full data, for example the bit rate of the ma-

Storage tracks are compiled. machine corresponds. In a typical example, you want

2. Data input device according to claim 1, 35 the data from an external clock in the clock, characterized in that the third memory of the machine or the main part of the machine to (3845) via a read head (3847 e) of a switch are set, wherein the frequency of the machine and control arrangement (3856 and 3858) with timing is always higher than the frequency of the outer write heads (3859) of a fourth memory timing.

(3857) is connected in such a way that the sectors 40. According to the invention, this object is achieved

of the third memory transferred groups of solved that at a data input device of the

Bit strings are put together to form data records of the type specified in the identifier of the

the, and that a read head (3863) of the fourth claim 1 listed measures taken

Memory via switch and control arrangements.

(3864, 3865) with a writing head (3866) of the 45 Further useful embodiments of the invention

second memory (3867) is connected in such a way, are specified in the subclaims,

that the data records to full memory tracks in the case of a system according to the invention

the second memory are assembled. Data that are fed to the switching arrangement,

3. Data input device according to claim 1, its own clock cycle in itself. That is, in the Dada through it characterized in that a bit counter (3861) is 50 th for both the 1-bits and the O-bits available in the signal depending on the length of the bit sequences. If the data is received at the third memory (3845) enter the transmission of the bit switching arrangement, it is assumed that the follow from the sectors of the third in the two-time cycle of the incoming data signals already praying Controls memory (3857). is correct and available

55 The bits are initially saved individually. This is done so that they can lead to the desired consequences.

that can be put together faster

Than the supply of the single bits.

The counting device achieves. that the

60 groups of memories or records each

The invention relates to a data input device containing a certain number of bits,
device with a data transmission arrangement for embodiments of the invention are in the

Transferred from various input means to drawings shown.

F i g fed to a first memory at any time. 1 is a block diagram of a transmission

Data in a second dynamic memory for arrangement with several inputs and a complete rotation Compilation of the individual memories;

Bits supplied to input means in memory. FIG. 2 is a block diagram of an execution location of the second memory. form of a transmission arrangement with which one can

3 4

ormation is transferred to a rotating memory, in which the corresponding sector, which corresponds to the data can; is assigned to this particular input,

FIG. 3 is another embodiment of one passing under a writing head 3679 . This input stage according to the invention; Pulse is output via line 3682 from the

F i g. Figure 4 is another embodiment of a 5 AND gate 3675 transmitted to a flip-flop 3681 , multi-channel input circuit in accordance with the invention; to sense the value of at least the last bit,

F i g. 5 shows an embodiment of a switch which is stored in this flip-flop.
for the input heads of FIG. 4; Simultaneously with rubbing in or feeding

6a to 6f show, in an example, how the transfer of the bits of the data record into the track 3673 b computer from several keypads from data records io through the signal head 3679 is the pulse that can be fed from; the signal head 3674 a has been read over

7 shows an embodiment of a multi-line 3676, an AND element 3683, via a nal input stage, which unlocks an unlocked keypad and holds line 3684, a delay line 3685. an amplifier 3686 to an erase head 3687

In Fig. 1 a switching arrangement for the inputs «5 is transferred so that the bit signal that would have just been read from one input on eight individual tracks is deleted. The delay line of a rotating accumulator in broken lines 3685 provides a delay time that is shown by the 3671 timer . duration that a signal needs to get from the

During operation, the bits of a Da signal head 3674λ are transferred to the signal head 3687 to form sets which are fed to the input terminal.

are pre-stored in a bit memory with instead of the already read and erased

Preferably has a flip-flop. The bits become impulses, a new one from the bit memory is then stored in the track 3673 α in a rotating memory impulse. This new bit pulse is transmitted earlier, the rotating memory itself shifting the bit spacing and therefore shows the position that determines the time of transmission. A 25 of the next following bit. The recording of the uniform distribution of the bits of information bit signals is controlled by the output signals of the is controlled in accordance with the times of the AND gate 3683 , which reaches input of these bits via a line. When a group of 3689, via a delay line 3691, a character preceding a word or sentence, OR gate 3692 and an amplifier 3693 is complete, it will be transmitted from the rotating memory to a write head 3688 . This is always transferred to other memories, for example, the process only takes place when a flow flows into another rotating memory or into a flop 3694 from the corresponding input-to-magnetic storage tape. The data of each data connection has received a signal. In the other case, the AND gate 3683 is successively compressed or the flip-flop 3694 blocks the AND gate 3683 in sequence or the line 3695 is transmitted in advance, so that the bit pulse is saved and transmitted to certain areas of the memory. Since that remains.

manual input only with a low speed. The input bit received from the input port

speed can be carried out, is supplied, can temporally with the pulse a number of revolutions of 120 revolutions per semenfall, which the flip-flop 3681 signals via the line of the rotating memory during each 4 ° 3682 and an AND gate 3696 senses. Since only a single bit is written in one revolution, in such a case the signal does not after the delay per input terminal, so that several input terminals need to be output in the flip-flop 3681 , the bit pulse from the input terminal can operate during the same rotation could be. The signals are not intended to be fed from one track, to be superimposed on a bypass path over one to another track. If there is more line 3Λ97 and the AND gate 3698 transmitted than one track in the memory, each connection that is opened by the sense pulse can be multiplied in order to insert bits . In order to now write how it will be described below to avoid the doubling of impulses, we will. the output of AND gate 3698 via the

It is assumed that one track and eight one-50 AND gate 3701 are regulated, which is blocked when there are output connections and that the rotating line 3699 has a signal. This will have four storage tracks via rende memory 3672. an inversion stage 3702 is carried out, which always outputs a track 3673 a as a track for displaying an output signal when it does not emit any one of the bit spaces. A track 3673 b works as a receiving data output signal.

memory track. A 3673 c track operates as a sector pulse track. A track 3673 d works as a sign for the signal transmission are in an OR pulse track. The storage tracks of the rotating storage element 3703 are connected to one another. The signal that chers are divided into eight sectors and can come from the OR gate 3703 is stored via a data of eight data records, of which the OR gate 3704 has eight input tracks or each has a maximum length of 128 characters. 60 channels transmitted with the write head 3679

If one bit work together in a sector of track 3673 a. The flip-flop 3681 is to be saved by the bit space in which the one sensing pulse is switched back to zero when this bit is to be saved, for which it was previously switched to the 1 state. Sector read out by a read head 3674 a. The Control of signal input channels occurs for pulse which is output from the head 3674 a, 65, the different input ports through the selectively via lines 3676 and 3677 to an AND sector counter 3678, the transfer of the Sektorzeitge gate 3675th The AND gate 3675 is overpulsed in the track 3673 c is controlled. The sector timer pulses measured by a sector counter 3678 for a period of time are read from a read head

3674 c is sensed and read via a line 3707 at the lowest valence of the field first or Sector counter 3678 transferred. stored so that arithmetic opera-

The sector impulses can also be implemented as anions. This is in contrast to the catch condition of a new data record used, the order of the data in which the first bit of a data record is entered in correspondence by the Tasta-URi (not shown),
The character delay lines passed by the

to arrange them correctly in such a sector. The AND gates 3724 α to 3724 d are controlled, control signal head 3674 6 therefore continuously senses the delay period and the bit timer data record each and every time and determines whether the stored unit of a flip-flop 3725 controls the field delay part of the data record a signal contains the ending io tion. At the end of this recording operation, the record is displayed. The signal for the end of a sector pulse from the track 3673 c a flip-flop of a data record can be the signal El when the 3726 returns to zero. An AND gate 3727 is carried out on the entire data record in one order - this way is opened via the line 3728 so that the input of characters in the subsector can be stored again, the counter 3721 can count again or advance. However, it can also be the signal 15 with respect to the different lengths of the words, which means the end of a word. the number of characters with the help of the character time

If one of these signals is to control a signal recognition over pulse in track 3673 d. This circuit 3708 is fed, a signal via control depends on the end-of-word signal, which is stored in the line 3709 to the AND element 3711 transferred to the track 3673d and on the gene. Between the line 3709 and the AND - ao head 3674 d can be sensed. This signal element 3711 is a delay line 3712 is then switched to the AND element via line 3729. The next one. Sector pulse is applied to 3727.

through the OR gate 3692 and the amplifier It is not necessary, however, to use the characters of a

3693 transferred to the write head 3683. to reverse every word when the signs of the

The delay line has a delay set in a reverse order in time, which are stored for a little less than the duration of one revolution of track 3673 b. The signals are, ie slightly shorter than 8 milliseconds, since they are all shifted backwards by one bit, in the present example the number of revolutions as soon as a new bit is to be stored. The new 120 revolutions per second lies. Via a bit to be stored, a flip-flop 3713 is always sent to the beginning of the device 3714 with a pulse train- 30 sector. In this case, the signals are also carried after each digit in delay line 3715 has been reversed in order to delay each storage. This delay line of a bit towards a direct reversal of the signal is controlled by a signal that will hold the end of the.

Means information or the end of the word. The matrix responds to a first control signal

From this signal on, the flip-flop 3713 remains at 35, which is caused by the normal or first sequence is determined from the beginning of the sector to the end of the same of the characters. Besides, she speaks Sector in the 1 state, which still responds to a second set of control signals with the selected matrix, Input connection, for example with the fifth resulting from the second or the desired sequence Input port, cooperates. The character flip-flop determines. The matrix then gives the 3713 opens the AND gate 3716 for the period 40 AND gate control signals, so that the characters in a sector time in order to transfer the data set to the memory in the desired order to enable another memory. can be carried.

Since the characters are presented in their usual order, the F i g. 2 is a block diagram of an embodiment

are arranged, in which they enter a form of transmission via a keyboard with which they were continuously (not shown), they can be arranged, for example, to transmit data to a rotating memory so that the highest digit can be used at the beginning. In the arrangement of Fig. 2, the Dalenwert are arranged. However, in order to be able to carry out arithmetic data records without stationary intermediate storage processes, these must be switched to the rotating memory, the sequence must be reversed. If this is required, with a bit rate of zero recording the tofu "" can of bits of the DA from the up data sets to Synchronisierungsbitgeschwindigkeit 5 °, the b in the track 3673 of the processing of the rotating memory is sufficient Bits of the data memory 3672 are to be stored, only one word of a data record is done via the line 3736. In this case the AND is fed to a set input of a 3737 flip-flop. Member 3717 is blocked at the moment in which the flip-flop 3737 is sensed by the bit pulse in a word end signal of the signal detection circuit 3708 55 line 3738, to which this flip-flop is fed via a. The signal detection circuit 3708 OR gate 3739 and an AND gate 3742 results in a signal via lines 3709 and 3718, is sufficient. When the input of a data bit of a Dada goes through an inversion stage 3719 and blocks the set in line 3736 and a query bit in AND gate 3717. line 3738 occur at the same time, a ne-

A counter 3721 counts the character pulses produced by the 60 flow path to prevent the Beginning to the end of the data set and indicates the data bit is lost.

Length of the saved data. A counter 3722 The time pulse for the query bit of the AND element

therefore displays the characters that are generated during the transmission. 3742 is only set by the bit memory flip-flop 3737 period are read out. Both counters 3721 back if there is no data on line 3736 and 3722 jointly determine 65 bits of a data record are present via a matrix. The default ER-3723 the delays required for the tracked in such a way that a pulse falling on the different characters, all characters of the field are present on line 3736, via a line 3743 and reverse in such a way that the positions of an inverter 3744 to the AND gate 3742 gc-

(ο

will lead. The AND gate 3742 is at the time. The output signal of the counter 3763 indicates when the blocks so that the interrogation pulse does not return the number of bits used to represent a character record input of the flip-flop 3737 can reach. That are required, i. H. so, including eight bits is due to the fact that the negation element 3744 is always complete with the distances, so that the character is not Emits a signal when a Si- 5 circular memory 3758 stores exactly one character at its input, great. The output of the counter 3763 is via a

A pulse on line 3738 reaches line 3772 and is fed to an AND gate 3771. The OR gate 3739 at the same time as the bit request AND gate 3771 is controlled by the character timer impulse, which is controlled via line 3745 and a pulse in line 3773,
delay line 3746 is supplied. The delayed io when eight bits are supplied, ie after the bit pulse on line 3747 corresponds to the seventh bit and after the space for the time clock pulse. Since the information pulse is small, the flip-flop 3774 is able to switch the bit memory pulse 3737 into the set state in the line 3736, the information is switched over so that the AND gate 3775 opens the memory pulse -Flipflop simultaneously with is The AND gate 3776 simultaneously blocks the return query pulse. The query or bit pulse guide line 3777 of the circulating memory 3758. The is carried over the line 3738 in order to use the data stored in the character circulating memory 3758 delayed bit query pulse via the line, are then through the AND gate 3745, the Delay line 3746, the OR 3775 and the line 3778 to another storage element 3739 and the AND element 3742 the flip-flop 20 rather 3779. The AND gate 3781 is switched back to zero for 3737. the resetting of the flip-flop 3774 by a Si

The output of the bit memory flip-flop gnal on line 3782 prepared by the 3737 is in any case precisely timed in the machine set output of flip-flop 3774 originates. the arranged in a timed manner, provided that the switching arrangement flip-flop 3774 is activated by the next time viewlet, which is linked back to the 0 output of this bit memory 25 on the line 3773 is. The output signal of the bit memory switches.

Flip-flops 3737 is used in a monostable multivi- The switching arrangement 3783, which is broken through

brator3748 converted into a pulse. The signal lines shown is once again in broken lines lines from the multivibrator 3748 are repeated as a switching arrangement 3779 to an AND element. Both 3749 is fed via line 3751 when the 30 switching arrangements are used for caching Bit memory flip-flop 3737 used by a pre-interrogation in accordance with the AB method. The switching pulse has been queried from line 3738, the order 3779, indicated by broken lines the AND gate 3749 controls. The Ausgat.gssi- is set up in the same way as the switching arrangement is also from the AND gate 3749 via voltage 3783, only has in the memory 3779 of the Um-delay devices 3753, which runs the machine memory with a capacity of eight characters. The Shift the time cycle on an output line corresponds to the usual number of characters 3752 submitted. Also, the outs of a group used for such purposes output signal to the OR gate 3754. If that is.

Bitspcichcr-Flipilop 3737 received from a pulse The output of the word circulating memory 3759 can

asks, which are fed to it by the delay device 40 to another memory circuit, 3746 is supplied, the output signal of the MuI- der is constructed in the same way as in the switchgear vibrator 3748 over line 3755 and voltage 3783. This other memory circuit can AND gate 3756 and the line 3757 which are used for four (or eight) OR gate 3754 supplied. The AND gate summarize 3756 words. The circulating storage one 45 such switching arrangement can have four read heads and controlled by 3747. have a write head. At the exit of this

The signal that is fed to line 3752, the last-mentioned switching arrangement, can therefore be connected in any case to the machine time - further switching arrangement that has a tcLkt and creates a character, since it has eight heads over the entire signal track AND- Members 3759a to 3759 / i to a circulation 50 can, the mutual spacing of which is 32 characters (or memory 3758 is guided, the capacity of which is eight bits and 64 characters). This makes the operation as amounts. The AND gates are possible from the Maschi circular memory by a simple rotation of the nenzeittakt and a time counter 3761 controlled track, provided that this track has a scope of ert. The AND gates 3759 a to 3759 h are from 200 points and 265 characters has.
the counter 3761 is controlled in such a way that the 55 By the switching arrangement of FIG. 2 it is possible for incoming bits in the character circulation memory to arrange an asynchronous input signal in such a way that 3758 are stored in chronological order. NEN that it is within the memory space of a nor- Simultaneously a signal through line 3762 times data salt of normal length can be stored in the correct counter 3763 and through line 3764 memory locations. The switches are fed to a 3765 flip-flop. The task of the flip-60 arrangement uses similar building blocks. Out-of-hops 3765 consists in advancing the speed of the display memory used for the transmission of the full character time count in the counter 3761, which is used for each incoming pulse from the time - e.g. 120,000 characters per second the line 3766 and the AND element can carry. Moving up several signal heads to the 3767 by one step. The flip-flop 65 subdivision of the circular memory or the tracks 3765 is used by the line encoder pulse on the line and if these heads are reset via the 3765, and that via a delay AND gate, it is possible to use a simple approximation device 3768 and a line 3769. That way the bits to characters, fields and groups

9 10

from fields to compose the transmission 3811, which by the AND gates 3812 a to 3812 / i

of the tracks between asynchronous working are dynamically loaded, are via a simple diode

controlled by a counter 3819 in any controllable manner, matrix 3821. the

perform. Counter 3819 is on lines 3801 and 3822

Fig. 3 shows an embodiment of an input 5 supplied with machine clock pulses and via gear stage according to the invention. The data is fed to an AND gate 3823, an 8 microsecond delay switch arrangement according to FIG. 3 via the line 3824 and a line 3825. The AND gate 3789 and once in positive pulses on 3823 is in turn reset by the Ausder line 3791 that opened the "1" in the corridor of the 3798 flip-flop. The counter 3819 represent binary code, and on the other hand in negative io is always supplied with pulses when pulses on the line 3792, each of which means a binary information bit from the delay line "0". The timing is fed to the circuit arrangement 3811 through the AND gates 3812 a to 3812 Ii voltage via the line 3793 and has been transmitted controls. The information is stored in the AND gates 3789 and a circulating memory 3826 for a character via the line 3794. The information signals can chert a flip-flop 15 which has eight multiplex channels. As soon as a field has been combined in the circulating memory 3826 and reset to the “O” state for a binary “0”, it is switched via a variable delay . That is, the bit clock opens the tion 3827 in one of two field circular memories AND gates 3794 and 3796, and a positive input 3828 a and 3828 /? transmitted, the arformationsimpuls in AB technology runs through the AND gate 3796 ao work.

through, a negative information pulse, however, the counter 3819 controls the AND gates 3812 a

happens the AND gate 3794, so that the "O" state to 3812 Λ in such a way that the information bit

of the flip-flop 3797 a "0" and the "1" status in the correct position of the bit sequence in the circular memory

this flip-flop corresponds to a "1". 3826 is classified. The variable delay

The 3797 flip-flop works as a bit memory. The 25 can change the information by up to eight character times

Bit timing is fed to a 3798 flip-flop and delayed in order to make it within a field in the correct

switches this to the set state. To classify against place. The circulating memory 3828a

set output of the flip-flop 3798 opens the AND and 3828 b for the fields have a capacity of

Link 3799 for the machine clock on the line eight characters, so that they together have a fully

processing 3801. As soon as the flip-flop 3798 can save 30 gen data record. The circulating storage

3828 a and 3828 6 for the fields set the fields

has been switched, the next machine is combined into a complete data record, the

ncnzeittaktimpuls on the line 3801 by the via the OR gate 3829, the transmission control

AND gate 3799, an OR gate 3802 and a 3831 and via one of several writing

Line 3803 passed so that it was a 35 circuits 3832 a to 3832 d in a 3833 track

»AND gate 3805 can open. So if a positive is convicted. Each of the write circuits 3832a

liver pulse is fed to the flip-flop 37 ^ 7, so that up to 3832 d has a write amplifier 3834 a to

it has switched to the "1" state, the po- 3834d, which is connected to the transmission control

sitive pulse through the AND gate 3805 and the 3831 is connected. as well as a print head

OR gate 3806 to the "1" input of the flip-flop 4 ° 3835 a to 3835 a ¹ , which is connected to the output of the corresponding

3807 forwarded. the relevant write insurer is connected and the A delayed machine clock pulse from track 3833 in the working position is opposite. In the

Line 3803 opens via a delay line delay arrangement 3827 and into the circulation

3808 stores the AND gate 3809 and stores the pulses 3828a and 38286 can either have two sets of 45 data records in eight multiplex channels during the "1" state of the flip-flop 3807 or four data records of a tapped delay line 3811. The approaches can be present in four mulliplex channels,
tapped delay line 3811 has a length of 8 microseconds, the task of the asynchronous input stage and has eight taps, which are shown in FIG. So 3 consists in this. Combine data bit for bit to form a complete data set controlled by AND gates 3812 a to 3812/1. 50 under the conditions of the machine clock

The flip-flop 3807 can be processed by a machine time. The machine clock pulse on the line 3803 via a delay pulse is a pulse that switches 3813 back to zero in the partial bit times 1, 2, 3. The bit time or 4 can occur. The data are therefore dei takt-FIipflop 3798 is fed from a machine time switching arrangement at any time to clock pulse on lines 3801 and 3815 via 55 and from these switching arrangements in a delay 3814 reset to zero. Partial bit times 1, 2, 3 or 4 retrieved.
When the machine clock pulse, the bit time act- Fig. 4 is an embodiment of a multi-channel pulse and the information bit pulse at the same time input circuit according to the invention. When the flip-flop 3798 occurs and its zero assignment according to FIG. 4, there are several inputs, but if it remains, the machine clock pulse 60 is only provided with a single output. Of the dei via the lines 3801, 3815 and 3816, via the sixteen inputs 3841 α to 3841 ρ, only five are shown in the AND element 3817, the OR element 3802 and FIG. These are the input lines 3803 to the AND gate 3818 and the 3841 b, 3841 e, 3841 ft, 3841 k and 3841 π.
OR gate 3806 past the flip-flop 3797- each input is fed to a memory which conducts and switches the flip-flop 3807 into the one-to-one capacity, which is just one bit. This spoke stood around. Otherwise the data bit signal could have a similar structure to the bit memory, which is lost in de. Arrangement according to Fig.3 are used. The Eir

The taps of the tapped delay line gang 3841 b is the bit memory 3843 6, the input

11 12

3841 c the bit memory 3843 e, which generates input 3841 k , which means the end of a data record,

the bit memory 3843 k and the input 3841 η dem This character must be in the first character division

Bit memory 3843 η supplied. remain behind the sector pulse. An information

The bit memories 3843 α to 3843 /;, of which only lion, which carries a signal that indicates the end of a data

the bit memory 3843 b, 3843 e, 3843 / i, 3843A: and 5 sentence means, the read head 3847 e in

3843 η are shown, are transmitted via the lines 3842 to the fourth memory 3857. This over-

3843 «are shown via the lines 3842a until the transmission path runs via the signal recognition

Input magnetic heads connected. The bits become circuit 3856, a transfer control circuit

by the switch for the heads 3844 together 3858 and one of the write heads 3859 α bis

represents and recorded in a third memory 3845 io 3859 d. The transmission pilot circuit 3858 becomes

net. This third memory 3845 has four write via a matrix 3862 by the record counter

heads 3846 α to 3846 d and five Lescköpfc 3847 a 3861 are controlled. Once sixteen records are in the

to 3847 e . Lane 3857 are composed, they are over

A sector of the third memory has the Iings the read head 3863, the AND gate 2864, the overcines of a data record. In order to now arrange all the bits in the sector 15 transfer control circuit 3865 as well as the write head after the sector start pulse, the information is 3866 transferred to a second memory 3867, formation that is already in the third memory 3845. The signal detection circuit 3856 is a bit time delayed before being recorded in the same flip-flop, which is an input from the read of the third memory. The last head 3847 e receives, while the other bit supplied to the input is always behind the sector pulse an- to size comes from a signal generator that is ordered in the. F i g. 4 is not shown, however. In the third

The F i g. 5 shows in which by dashed lines there are rather 3845 four multiplex sub-bit time positions

framed part an embodiment of the scarf present. The signal detection circuit 3856

arrangement 3844 for the input heads of Fig. 4. If the end of the data record is determined, reads this Si

Each bit memory 3843 b, 3843 e, 3843/1, 3843 k and as gnal again from, and the transfer control circuit

3843/1 has access to the AND gates 3848 and 3858 transfers this signal to the fourth memory

3849. Four inputs 3842a to 3842d are via the 3857. A test is then carried out,

Circuit according to Fig. 5 with a pair of read and to determine whether the signal is really the end

Print heads connected. The input variables to a data record means. If this test is positive

These four inputs come out at different 30 tiv, a pulse is fed to the counter 3861,

Clock pulses on. The circuit of FIG. 5 to the transfer control circuit for the next

must prepare four times available data record setting for sixteen inputs. The selected domestic

scin. formation in the third memory 3845 is over

Assume the information that a portion of the 3868 line is deleted.

Data set is already in the third memory 35 The transfer control circuit 3858 has rnrh-

3845 (Figure 4). Each input has rere AND gates that go once over the counter an information bit memory and a flip-3861 as well as flipped by the sector timer pulses. which are used as a memory for a timer bit from a controls. Drain the capacity of the 3861 counter Timer generator is used. When the flip-flop speaks of the number of storage locations in the fourth a signal for a positive and a negative 4 ° memory 3857. When the fourth memory 3857 is full Emits bit, if the corresponding previous one is, the counter 3861 ends its counting and opening part of the data record that already stores the AND element 3864 in the third.

rather 3845 is recorded, due to a delay Since the information on the sixteen input

stage 3851 passed through, which a delay lines of the circuit arrangement 3844 with sub-

tion caused by one bit, as well as arriving at 45 different speeds, becomes a

OR gate 3852, and when it reaches the write head, the bit group is first used to record the data.

3846 o, so that the new bit can fill the first bit space behind, and then the combined sector pulse can occupy. If no new set data record is used to present the fourth data bit, it is recorded and filled up. In the information that is supplied to the Schalnete part of the data set, for example from the 5 ° processing arrangement 3844, there are no read head 3847 c, through the AND element 3849 and sector pulses, but only signals via the OR element 3852 to the write head 3846 c to the end of a data record. Every input line led. The new information bits are assigned to a sub-bit time, so that four different-after-OR elements 3852 can be present via line 3853. The third sub-bit times. For each track AND element 3848, there are sixteen data records in four multiplex channels via the line 3854 from the 55 “one” output of the flip-flop 3798 from FIG. 3 available and 128 characters per data record. If, while the AND gate 3849 controls the signal via the end device 3855 from the reset output of this flip of a data record via the line on the line 3842 d, it is controlled in the subbit flops. Time 4 standing data record the fourth memory 3857

Transferred by the operation of the circuit arrangement 60. The moment the fourth

3844 for the input headers requires that the memory 3857 is full, the content on the two

Information in the third memory 3845 is transferred to the th memory 3867. It is possible that

to use the correct order bit for bit after the sector data record group in AB technology, and

impulse is arranged. The information that was initially provided for the sub-picture times 1 and 2 and others

third memory 3845 is recorded, is followed by 65 for the subbit times 3 and 4, so that to

read a signal detection circuit 3856, which transmit half a track at each point in time

each of the known signals is matched with the incoming one. This makes it easier to control. Signal compares and an indication for a character Figures 6a, 6b, 6c, 6d, 6c, 6f, collectively as

13 14

6 are designated, deal with how that are subdivided, once a one and once a computer from several keypads from new data zero. The one bits are fed to the multiplex sets. It is assumed that the input stage is supplied via line 3875 , men. that the bits from the keypads come with them, while the zero bits are fed via line 3876 to the multiplex input stage, which is fed at a bit frequency of 60 bits per second. To anybody. The bit frequency can also be 120 bits per any point in time, there is always only one bit, which is kunae, but then the number of rotations of the rotated memories can be either a one bit or a zero bit. The one bit can be stored in the F! Ipflop3877 circuits work for both frequencies, the zero bit, however, can be in the flip in the same way. The characters that are keyed io flop 3878 are stored. The lines 3875 and 3876 den, have the order of a normal writing with the set input of the flip-flop 3879 via a writing. The bit sequence within a character starts with OR gate 3881 connected. When the flip-flop with the most significant bit. If the operating 3879 is in its set state, the display staff starts each word with the "end of word" signal that a new information bit has been supplied and ends each word with 15 den.

a similar signal drawn as "EW". The multiplex input stage is for eight keypads - the EW signal is only designed for the transmission of the 4020 . The circuit according to FIG. 6, which uses words to the memory when the words are separated by the broken lines 3882 , is intended to form data records with a fixed field length, but only for the sixth keypad. Which should be set. The input shown therefore corresponds to the sixth input stage. The task of the multiplex input stage consists of the assembling sector of the memory 3883 , the sequence of bits within the words and of bits. The point in time at which to change a bit in the Speider character and to assemble the bits in the appropriate rather 3883 for assembling bits stored bit density. Since the bits will be with a 3884 is indicated by a counter. The low bit rate are supplied, 25 counters 3884 is driven by sector pulses from a multiple keypad memory 3885 to the same multiplication stages M. This is done via a connected. The multiplex input stage has a Kopi 3SS6, which the impulses that it senses, the counter or several storage tracks in order to combine the bits from 3884 via an amplifier 3887 and a power supply. Each track is divided into sectors. 3888 feeds. The sector pulses are except- Each sector corresponds to a keypad. When the 30 is fed to an AND gate. As soon as the counting length of a field is determined and eight characters ler 3884 reaches its sixth state, that is, a track can have 32 sectors. AND gate 3889 for the next sector in the -If the length of the field is variable, the pulse is prepared.

entire information unit is arranged in the track, so if during a previous revolution that only two sectors two keypads equal to 35 of the memory 3883 come in for assembling bits. However, since a multiplexing system uses the flip-flop 3877 or one bit in the flip-flop 3878 , it is possible to store four data sets in each sector, the flip-flop 3879 goes to assemble into one. First of all, we shall now describe about. In the one state, the flip-flop 3879 opens the AND gate 3889 for the corresponding sector menu, like data records with fixed field lengths, and then the pulse is generated. This impulse first opens an AND element act of variable fields described. 3891 and then switches the flip-flop 3879 to zero. Each bit supplied is first returned to a bit memory. The pulse, which is stored by the AND gate 3891 until the sector that is correspondingly transmitted, corresponds to the input of a flip-flop corresponding keypad, has reached the writing order 3892 , via the line 3893 and has reached position. A new bit is always an OR gate 3894 in the 45. If the flip-flop 3892 is stored in the first bit position of the sector. The one state is, it closes the AND gate 3895 and bits that are already stored in the sector, r.iüs- opens the AND gate 3896. This happens immediately, therefore, are shifted by one bit position. Before the information stored in sector 6 of the memory is passed, it is possible to always insert each new bit at chcrs 3883 for the assembly of bits at the same time in the memory. The bit sequence changes 50 chert is fed to the read head 3897. The in during this process. The keypad generated formation is read from the head 3897 and is therefore a bit sequence which is highly unusual. the AND gate 3895 via the amplifier 3898 so-

At the end of each word there is an EJ-F signal before the AND gate 3896 via the delay stage

seen. It is detected when it is fed in lane 3899. Since the flip-flop 3892 is set

is saved. The EW signal is the initial 55 state signal, the information read out can pass through

for the transmission of the word for the track to the AND gate 3896 are transmitted after

putting words together. Two of these have passed through the 3899 delay stage.

Traces for composing words before ^ '.

hen. One track is for the first four inputs. If the information read out is intended for the delay and the second track is fed to the next four 60 signal inputs, the flip-flop changes inputs. Each channel of the tracks corresponds to a 3789 returned to the zero state, making it the input of a keypad. The transmission to the AND gate 3901 opens and the AND gate 3902 Bclegspeichcr can therefore be prepared channel by channel. When the 3877 flip-flop will be in the one state. Then one is for each key pad input, one channel is provided by the one output of this flip-flop. 6 ₅ amplifier 3903 via AND gate 3901

Fig. 6 a is part of an embodiment AND gate 3904 and an OR gate 3905 a po-

A multiplexing stage. It is assumed that a silive signal is supplied. When the 3878 flip-flop is in

The amplifier 3903

the AND gate 3902 an AND gate 3907 from the gear stage nacJ di Flifl i itives S.gna, zu ^ e the W

DGl

this flip-flop a positive S.gna, too-

'^ Amplifiers 3903 serve, in addition, to the positive si- den them

OR gate 3908 at the same time pulls the from the

to be led. The delay stage 3899 delays

ris res γα T

and 3902 a " _S , yours ,. If that can auitriu

no output signal "bgiW" cnn, the reversible mare 3917 is fed. d, c too

Spe, * rs3 ₈ 83 jur Zn.

WD member 3895. The information of the ^ nachk, gen-

E3äSHi3S

should the connections to the other seven corridors represent the multiplicx input stage.

D ⁸ ie Fig. 6b is a block diagram cmesjdc ™, part of the embodiment of a Multiplcxun

* ⁶

In Fig. 6b is shown
°? J _{rf hU} are arranged

_one

Record throw

,., ",! ,," j _f hate. on

S "

_en

_irf about

- {■

™ _{by Bjts is therefore} , “the sub-

^ 7e? 2 of the second track to be assembled

b J ^ Jj ^ _{üc Dic} switching arrangement

from _Λ ης Α9Α / 82

3932 can be divided into three parts. In the first part, the word is either in the subbit time 3 or transmitted in the subbit time4. In the second part, the word is made up of sectors 1, 2, 5 and 6 in subbit time I or subbit time 2 transmitted. In the third part, the word moves from sectors 1 to 4 to the first ipur for composing data sets Transmitted and also the word from sectors 5 to 8 is put into the second track for assembly of records transferred.

The first part of the switching arrangement 34) 32 has OR gates 3934a and 3934 6, AND gates 3935, 3936 and 3937 and a flip-flop 3938. The OR element 3934 leads to the AND element 3935 via the lines 3939 a, 3939 b, 3939 c and 3939 d with the / iy time pulses 1, 3, 5 and 7. The AND gate 3935 is opened by the / 6 'timer pulses for the timer pulses of subbit time3. The OR element 3934 b leads the II / -Zeitimr> ulsc2, 4, 6 and 8 via the lines 3939 e, 3939 /, 3939 g and 3939 / (to the AND element 393 (5. The AND element 3936 is of these / L 'timing pulses are opened for the timing pulses of subbit time 4. In this way, the line gating pulses of subbit time 3 or subbit time 4 are supplied to flip-flop 3938 and AND gate 3937. Flip-flop 3938 and the AND Element 3937 together form a circuit for subbit time transfer, which is constructed in a known manner and works as already described. The second part of the switching arrangement 3932 has the OR elements 3941 σ and 3941 b as well as the AND elements 3'M2 3943 and 3944 and a flip-flop 3945.. the flip-flop 3945 and aND gate 3944 together act as a circuit for a sub bit-time transfer. the OR gate 3941 summarizes the α / L'timing pulses of Subbit- Zeitcn 1, 2,5 and 6 together to control the AND gate 3943 for those words that are in the subbit time 1 or the subbit time 1 are to be transmitted. The OR element 3941 b combines the / CZ timer pulses of the sub-bit times 3.4, 7 and 8 in order to control the AND element 3942 for the words that are to be transmitted in the sub-bit time 3 or 4. The words by the AND gate

3943 are transmitted to the circuit for a sub-bit time conversion, which is derived from the Flip-flop 3945 and the AND gate 3944 consists. In the OR gate 3946 a and 3946 6 are the / L'-Zcitgeberimpulsc 1 and 5 and 2 and 6 combined, which are then fed to the AND gate 3947 and the t'ND gate 3948 to generate the subbit time pulses 1 and 2 to control. The subbit time pulses are the new pulses for words passing through the flip-flop 3945 and the AND gate 3944 are transmitted. The outputs of the AND gates 3942 and

3944 are combined in an OR element 3949. The third part of the switching arrangement 3932 has the ODi U links 3951 α and 3951 ft and the T'ND links 3952 and 3953. The ODF.R element 3951 α combines the /(./ timer pulses of the Siibbit Zeiton 1 Ins 4 to the AND element 3953 an- / ■ tisu-; i.jr-n. IV ₁ S OR element 3951 /> summarizes the /i'-/.uit,;ebc;i;i|nilse the sub bit times 5 to 8 together and the AND gate to control _m 3952 the absorbent cotton t -., m head 3931! have been read out, this way can also be distributed over the four sub-bit times of the two tracks for assembling data records.

Each key field input of the multiplexing input stage has a field counter 3954 (FIG. 6 cj, the a pulse is always supplied when a word from the corresponding keypad is complete. This pulse is taken from the 1 output of the flip-flop 3928 and is sent to the AND gate 3955 keyed "and the counter 3954 via a line

ίο 3956 supplied. The control signals for the AND gate 3955 indicating that the words should be placed in a fixed length field issued by the reset output of a flip-flop 3957 and fed to the AND gate 3955 via the line 3958. This control signal from the zero output of flip-flop 3957 also opens the AND gates 3959 and 3961. In the present example, therefore, a word from the keypad ft is entered via the AND gates 3952 and 3961 and entered via an amplifier 3963 in a circulating memory 3962. The word remains in the circular memory 3962 until the AND gate 3964 from the field counter 3954 is opened.

The field counter 3954 is with the AND element 3964

as connected via a 3965 matrix. The matrix 3965 contains several AND elements 3966 a to 3966 p. The task of the matrix 3965 is to coordinate the subbit time pulses on the line 3967, the actual field time pulses on the lines 3968 to 3968 p and the status of the counter 3954. The control signal is the corresponding sub-bit time pulse at the correct transmission time. The words, which then have a fixed length, are scanned in the AND element 3964 and taken from the switching arrangement via an OR element 3971 and a line 3972. These words are then fed to the second track for composing the data records. The fields for the first track to compose records are stored in a circular memory 3973 after going through AND gates 3953 and 3959. An AND element 3974 controls the transmission of the fields for the first data record via an OR element 3975 and a line 3976. This AND element works in the same way as the AND element 3964.

The / ^ / signal is fed together with the last word of a data record and in the comparison circuit 3919 detected. At the end of the drawing time for this signal, a pulse of the AND gate 3977 transmitted, which originates from the zero output of a flip-flop 3978 and on the input of a 3979 flip-flop arrives. When the 3979 flip-flop is set, it also switches so that a flip-flop 3981 changes to the 1 state. The next following character timer pulse on the line 3926 switches the flip-flops 3979 and 3981 back to the O state. The downshift of the flip-flop 3979 is controlled via an AND gate 3982, which is connected to the 1 output of the flip-flop 3979 connected is. The switch-back pulse is fed to the flip-hop 3981 via the line 3983. Every time then, when the flip-flop 3981 is in the set state, the state of a flip-flop 3984 becomes changed by a pulse that is taken from the! output of the flip-flop and the flip-flop 3984 is supplied via line 3985. The data records of a keypad are in this way in

divided into two groups, and the corresponding output signals El-I and El-I appear on output lines 3986 and 3987.

If the words read from track 3883 are treated as fields of variable length should, the entire data records are summarized in this S-nir. The 3957 flip-flop is located ■, I in the set or 1 state and blocked the Transmission of the generated EH 'sign by the

supplied ".ircl, controls

AND gates 4002

the line jvi * uuci -....- .. -_ .,

a head 4004 further. The AND-Ghed 4003i emits the fields from the line 3972 via e.ncn amplifier 4007 to a head 4006.

The AND gates 3999 «to 3999 /, become ^ on the flip-flops 3995 «to 3995 rf are controlled, and they are also given Kanalr.e.timpulse_

gn im «- .., V ₁₁ -, _r ■, · ι _r

AND gate 3988 is fed through to the comparison circuit / (7 time pulses. The LNU-unecie

- - up to 3999 / 'control the AND gates 4011 401-.

di Sil on the ue -

tiii.g 3923. The flip-flop 3957 closes the AND gate 3955, so that the field counter 3954 switched off to 3999 / control the AND

4013 and 4014, through which the signals on the ue -

, "" ^ J -, no-r / tr: "ή M ίΐη A \ C AND-Ulie-

3986 and 3987 (Fig. 6b) to the AND

te! and also closes AND gates 3959

Task, the channel time imp

4015 «to 4015 rf the data record time impulses

fldl aar

the 3989 and 3991 are open, the together can wu u un. ^ «> ~ ..-. ,

converted data sets either via line 4016 and the input keypad signals to OR gate 3975 to output line 3976 ueland lines 3997a to 3997 /) to überemsiim. -en or to output line 3972 via the 20. The signals on the line 11 OR gate 3971. 3986 and 3987 are indicated by the ^IN V ^> " ^U1 !" ¹ ^

6c is another part of the embodiment 4011, 4012, 4013 and 4014 loaded, which the uiniJ- • onn of a multiplex output stage from the F i g. Control 6 a links 4002 and 4003 to activate the heroes from ■ jiid 6 b. In FIG. 6 c it is shown how fields spring the line 3972 to be transferred into the correct position. Most length, either from the circular memory 25 whenever a channel memory is filled with two υ 3973 or the circular memory 3962 via the Austen records, both data records inuangsleitung 3976 or the output line 3972 are transferred within one revolution to the corresponding Betransfer Combined data sets are transferred in a leg memory. The transfer times are. This representation applies to fields that have been keyed in via the is keyed in by a signal on the -yBv angc keypad 6. The position of FIG. 30 shows that the AND gates 4Ul ("elder, which are controlled either by the output line 3976 and 4013. The transmission from or from the output line 3972 is supplied, two data records are carried out via a readout means already determined by the field counter 3954. Those of a head 4017 (Fig. fif). The data records which are therefore read out by the head 4017 according to the switching arrangement are already in the correct chronological order in Fig. 6c -. 35 amplifies an amplifier 4018 and supplied into a voltage, as has already been mentioned, aND gate 4019 is keyed for the keypad 6 of a particular keypad is, the aND gate 4019 via line ⁴ ^ ²¹ ™ 'always for the information. a subbit time is available which supplies line clock pulses as memory. The AND element 4Ul * for combining in the first and second is used by a flip-flop 4022 for the duration of a track this way 40 turns open. This flip-flop is composed of the channel by channel. The supplied field is /: / - 2-Signa! controlled on line 3987. The Dadaher either in the first or in the second
Half of a subbit time. That will go through
the circuit arrangement 3994 is controlled.

For each keypad 4020 of keypads 5 through 8, 45 has been written.

their information in the memory 3996 together. The I / 2 pulses on the line 3987 control

is set, a flip-flop 3995 α to 3995 rf is provided shift register 4025 is on. The shift register 4025 hen. The flip-flops 3995 "to 3995 rf show the assignment of four HipHops 4026" to 4026 rf, which stood! of the first half of the channel, since they correspond to their four sub-bil times in which the data status can be stored in the memory twice per cycle of the 3996 memory, which a sub-bit time can be disabled if The flip-flops 4026 "to 4026 rf control the AND gates 4027" to 4027 rf, which are also supplied with subbit time pulses and / iZ timer pulses. The data records are transferred to this Wcsie by a 55 AND element 4028 in the next unused subbit time of a track in the document memory 4029.

/: 72 signal on the g g

trnätze "are in the subbit time 4 by the known Transfer combination of a flip-flop 4023 and an AND gate 4024, as it has already been

the corresponding input signal of the keypad is supplied via lines 3997 a and 3997 /). The input signals open the corresponding AND gates 3998 α to 3998 rf.

A signal is received via lines 3986 and 3987 (FIG. 6 b) which indicates whether the supplied field is to be stored in the first or second half of the memory 3996. The matrix, the AND elements 3999 «to 3999 /; provides a signal that designates the head that is to write the field in the correct place in the channel. The AND gates 3999 ″ to 3999 Ii are supplied with rf timer pulses via AND gates 4001 ″ to 4001 rf. The AND gates 4001, 1 to 4001 rf are nested by the input keypad signals which were connected to lines 3997 to 39 'for 7 hours .

The head control signal received from the ·. Switchgear

carry, through an amplifier 4031 and a head 4032. Data sets with fields variable 1 items are treated in the same way.

The F i g. 7 is an embodiment of a multi-channel unit style, which contains an unlocked keypad, in Fig. 7 each fastener on a keypad is 4038 over several Leituniien with a matrix 4039 connected. The matrix 4039 has several low-frequency diodes on and eight outputs, and two outputs for each hit of a character. The eight outputs are keyed by fast AND gates, which are

21 22

because they are opened once for each character. This opens an AND gate 4053

to put the bits in the correct order. net. A power supply 4054 gives pulses mil

The bits are stored in a circulating memory 4041 with a frequency of 120Hz, and these pulses,

at a bit rate of 1 MHz. A flip-flop 4055 via the AND gate 4053

are fed with a very slow clock bit for 5, bring this flip-flop into the

Bit transferred to an output via a line. Einszusland. The next subsequent bit that is out

The circuit arrangement of FIG. 7 the Vcr- the circulating memory 4044 on the line 4047

The use of unlocked keyboards is possible, an AND element 4056 opens and can also

chen. In previously known systems, sixteen would open an AND gate 4057 for the duration of one bit.

Used keyboards that were all locked. Since io a bit that comes from the circular memory 4041,

A low-frequency telephone line is then used for the transmission from the switching arrangement via the

device is used, more than 120Hz non-AND gate 4057 and an output line 4058 can be

be transmitted. It can also be used in well-known.

t systems a currently locked key of the keyboard

door cannot be pushed down. So if there are 15 4041, usually via an AND gate 4059

is necessary to down the same key twice and the OR gate 4051 revolves, runs for one

press, the second press will not result in a character period via an AND gate 4061, a

Output signal generated. The circuit of FIG. 7 delay stage 4062 of one microsecond and

allows, however, the use of unlocked OR gate 4051 around. Be that way

Keyboards and thereby a continuous transfer of all remaining bits of the character to the next

bearing. shifted the bit location so that on the next

The circuit arrangement of FIG. 7 is one of six times at which the bit of the circular memory 4044

ten similar switching arrangements, that is, the AND gate 4057 via the AND gate 4056 opens-

Switching arrangement according to FIG. 7 is 16 times net in operation, the next bit in such a position

present. If there is a key on the keyboard 4038 in which it can be transmitted,

is suppressed, the matrix 4039 is on as long as always when at the output of the circulation storage

controls how the button is depressed. The chers 4043 a bit appears, the control pulse changes

suitable outputs, which the matrix emits, set up the AND gate 4057 via the line 4063

look for the code that is desired for the character loop back the memory for the time of a

is. The pressed key also brings 30 characters. This feedback loop is then not

a flip-flop 4042 in the fin state. If the more without delay, but points out the reverse

Flipfiop 4042 is in the one state, it prepares the routing loops 4061 and 4062 a delay

AND gate 4043 . from 1 microsecond. The same control impulse

A bit circulates in a circulating memory 4044 , brings the flip-flop 4055 via the line 4064 into the AND gates 4045 α to 4045 h via the eight 35 and opens a counter outputs 4046 α to 4046/1 one after the other . 4065 supplied via a line 4066.
At the moment in which the Π; ρΠορ 4042 the After eight bits from the circular memory AND element "4043 for a sound," prepared and 4041 via the AND element 4057 to the output of the circular memory, the bit is sent to the line 4047 processing 4058 have been exceeded, the counter gives, a flip-flop 4048 goes into the one state via 40 4065 an output signal which resets the flip-flop 4052 and thereby opens the AND gate 4049. When it returns to zero 4044 the drain of the switching arrangement of FIG. 7 ends, a Tasle the Tasiakunden the row α in aND gates 4045-4045 block / 1 within 8 Mikrosc- which a character is generated by, and the output signal is the depressed door and in which the key signal matrix is the aND gate 4049 and is transmitted 45 via a circulating memory at the Ausgangsspeichcr ODF.R gate 4051 to the circulating memory 4041 züge-. the time beführt for this operation. the Bi t. that the circulating memory 4044 is required in is about 80 microseconds. Leaving line 4047 resets flip-flops 4048 and time duration for this operation therefore allows a Zci- 4042 to zero. The working cycle of this line speed of twelve characters per second. Switching arrangement takes less than 50 16Mikrosekun- The circulating memory 4044 is a circulating memory in the claim, and since one can assume that a sign of exactly. It saves at least one bit over one point at a time on the keypad and generates eight bits, which is pressed down for eight different periods of time if different outputs are required. Not to be locked in any micro-keypad. Second opens an output bit of one of the AND-GHe

When the flip-flop 4048 is in the set state, the 4045 a to 4045 / i, these are the

a flip-flop 4052 is also opened in the set state according to sequence.

For this purpose 4 sheets of drawings

Claims (1)

1 2 Since a computer very often with memories or claims: input keyboards must be connected, which are arranged outside the memory, a 1. Data input device with a data connection arrangement used to connect the transmission arrangement to enter information carried out from 5 to transmit. It is very different Input means at any time clearly seldom that external memory or external th data fed to a first memory in input devices has the same timing as the a second dynamic memory for the complete computer, which processes the data, in particular Compilation of the information from each of the others when the information is via telephone input means supplied bits in memory lines or similar connections over wide delaminations of the second memory, as a result of which distances can be transferred. In such a case indicates that the single bit memory is very long the bit rate of the data supplied- (3843) of the first memory via a selection sample, provided that it is synchronized with the computer switch and a circuit arrangement (3844 in compares. The data must therefore be transmitted in this way Fig. 5), each with a read and write head 15, can be converted into characters bit by bit (3847 or 3846) of a sector, a third to fields and field-to-field to a complete memory (3845) are connected, in which the gene data set is composed. Bits from the various individual bit memories It is also possible to operate several inputs to (3843) in groups in the sectors at the same time as they are put together in connection with gen, in such a way that the multiplex input is still described. In three cases in the sectors of the third memory (3845) it is assumed that in the time of a reloaded bit sequences from the read head (3847) rotation of the rotating memory per input and the write head (3846) only one data bit is fed to one end . Since the rotary switch arrangement (3848, 3849) can be divided into several sectors depending on the memory, each sector can be electrically connected to one of the direct or single-bit delay inputs . Assuming that array (3851) are supplied and that the number of sectors is 8 or 16, eight can be transferred to the third memory (3845 ) can be operated with.