DE1499178A1 - Controllable data memory with delay line - Google Patents

Description

Patent attorney 1AQQ17R I LjT

te-tar. Wilhelm ReioHsl ^{1AS31 / 8} | J - / *.

Fiankfiiri / Maixi-1

Parksiraße 13 4333

Dr. Gerhard Dirks, Los Altos Hills, Calif., U.S./.·

Controllable data memory with "delay line elimination from patent ... (patent application D 45 148 IXc / 42m)

There are data processing systems known that with Work with direct access disk storage. The main advantage of these systems is that they can be used by everyone in the Discs stored information a 'prompt access possible is. It must be regarded as a disadvantage that access to information sequences is difficult because for A special access operation is necessary to find each individual piece of information in the sequence. Hence are Miseh sorting operations are also difficult, since such access operations consume most of the machine time will. Mixed sorting processes are used in such systems with disk storage is carried out in such a way that the order of the addresses is determined in which the individual information units for the purpose of compilation a sequence of information can be called.

Furthermore, data processing systems are received that have Magnetic tape stores are equipped. In such systems, the information units are in a well-ordered order stored in the magnetic tapes. However, there is no direct access to individual information units possible, "on the contrary, a magnetic tape must be searched through completely until the desired information units are found. Such data processing can only be used economically if the majority of the stored Data are required for processing purposes. In

BADORIQINAL ÖÖ9839 / 1607

in this case, mixing-sorting processes are highly efficient feasible.

In order to combine the advantages of these two known Datenverarbei processing systems, it has been proposed to store the individual information units in systems with Il ttenspepeicher, so with memories with direct access, sorted according to a certain generic term in this memory with direct access. In addition to the advantage of direct access to the individual information units is then obtained the advantage that all of the known Mangebandeinheiten forth M-sorting method ic-can be performed. D s is also possible in those cases with a high utilization of the machine time, in which only a few information sequences have to be mixed or sorted, thus • also in all those cases in which the mixed-sorting processes with magnetic tape units because of insufficient information n ^ " economical, are not to be represented.

It is in all known data processing systems necessary to provide additional circuits and buffers, the individual information units for the Bear processing and transfer from one memory to another. For these tasks it is known Provide intermediate registers made up of active bistable circuits such as flip-flop chains passive bistable circuits such as ferrite cores or delay lines can. ·

The invention is now concerned with such transmission circuits and latches using delay lines work and for use in such proposed data processing systems are determined in which the individual

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Information in well-ordered order in storage with are stored with direct access.

It is particularly favorable if the transmission circuit does not can only take over information units for intermediate storage, but if it is also able to carry out at the same time of mixed sorting processes the information units of a certain sector of a disk drive to another Sector of another disk storage to be transferred, or if an interlaced information record known per se is used, the information units from a time channel to convict.

Since the main advantages of this proposed data processing system require that the data be stored in the disk memory in sequence, i.e. one behind the other without gaps, such a circuit should also be able to "compress ¹ " information units at the same time, provided they are not stored consecutively are.

All of these requirements are met by a circuit arrangement for fulfills a delay line working as a memory, which is characterized according to the invention in that the delay time of the delay line is shorter than the duration of the information to be stored, that the connection of the output of the Delay line with its input over several parallel connected Branches take place »each of which has a delay element with a different delay time, and that the passage the information units through the parallel branches can be controlled by program and / or timing pulses.

Further properties of this circuit arrangement that are relevant to the invention are now based on an embodiment in connection with the Pig. 122, which is a block diagram represents an embodiment of the circuit arrangement according to the invention *

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U99178

so that at the moment there is the field of information seijihj happens under the read head, the previous sum odea Difference from a register with this field information in can be combined with an arithmetic process in order to to create a new sum or difference.

For each field eats a number of dynamic arithmetic. Registers are provided in the memory track in which each the register remains separate from the other registers, i.e. what remains is the various information such as the group total for subgroups and main groups separated from each other and pass through the reading head one after the other

The data stored in the dynamic store information units included Spnlüsaelfelddaten, which are identified by the format information "The _# key fields * used as Grupiensteueafelder to the arrangement of sub-groups to determine JSxuppen, ÜbergTuppen and main group data, while Ver ^ facilitated arrangement, the Schlüeeelfeider dead / one behind the other related information units and compares Having determined that the relevant parts of these maps habenbi verifiable changes in their content, the ^ character BITS is correctly timed to each other randomly a.

Ο «The controllable delay line ·"

The FIG. 122 is a schematic block diagram of an arrangement of a universal delay line used in the data processing system of FIG. 104 can be used. The arrangement "of the S ¹ ICf. 122 is particularly suitable for systems with nested information BITS, - and can be used for delaying information over the length of the delay line uria multiples thereof" The arrangement can just as well be used with the turret the multiple delay line length are used ϊΑβ parallel turret bzwe ation with cer length of the actual delay time for a plurality of Inform. "This is made possible in that the delay line is used in a system with nested arranged information"

., .00 * 1-34 * 1 * 6Q7 .--- ■

In the delay line arrangement ier I ¹ IGr. 122 it is assumed that a SUBi-BIT-TIME is equal to 3 microseconds and that the delay unit is a field time _{or the like}

If the delay line is used as a revolver with several parallel and independent channels, the information on the input line 3044 is first transferred to a Karialüberfülirungsanordnung 3045. The SET and RESET conditions of the trigger of this channel transfer arrangement 3045 are determined by the channel pulses on line 3046. The channel pulses 1 to X are sent to the channel transfer device depending on the program control. ZSIT-IMPULSEN 'works, the trigger of the channel transfer arrangement is called BIT memory ₃ Dae, during the time between the incoming BIT of information and the next BIT, the channel pulse sequence causes the Kanalüberführungungsanordnung 3045 to work as a BIT memory ^ This results from the control dee ΐΓΝΒ-gate of the channel transfer arrangement 3045 through, the channel pulses as, this has already been described · ·; ., "\. '· -'"'

The Iiifortaationen; Laaai ^ eift from the channel transfer assembly 3045 via the line JO ^^ and the ÖDEH gate 5051 to the delay line 5ö48,. The delay line 3048 can be of any usable type, for example a device which works in such a way that it transmits an impulse by induction on a wire, this transmission is carried out mechanically or auoli by pressure excercise ₀

The information that run through ά ± β delay line 3048 will be delayed by a .Feldzeit less a SUB-BIT TIME information "Since the real Feldseit has 256 microseconds occurs an actual delay of 255 Mikrosekunaen on _β to" closing passes a Delay path 3052 of the length of one microsecond, so that the total delay is again 256 microseconds and that no change in the channel is admitted; If the information arises <> The microsecond delay is carried out through line 3053, line 3054, TOD-Tj ^ $ ^ _s / f ^ <f ru »| ^ l ^ _fcÄ 2, line

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3056 and the OR gate 3051 carried out the information comes from the OR gate 5051 back to the Mni> ng of the delay line 3048. The / erzößarunfepleitung works in in this case because of the four interleaved channels how much? parallel turrets .; Any information that comes from the channel transfer · -. fübrungsanordnung 5045 .. eye leads, remains in the channel » which you by the arrangement 30 ** !; was given.·

The I) u: «- chla ¥» .f eier information through the delay 3052 of a microsecond is indicated by a signal on the line

3057 controlled, which arrives at the TJND ~ 'gate 3055. The additional delay of one microsecond in the delay element 3052 is provided because the delay line 3048 is one microsecond shorter in its delay time than the total turret required for the delay of information without shifting the information. The turret can store as much independent and different information as it has nested channels. If one or more pieces of information are required, a signal on the line is used to send the complete message;

3058 d & to make this available "The output. · ■ -such Information is provided via lines 3053 »30591 delay line 3061, AND gate 3062 and output · line 3063 »

When information from the delay line to the · '■ line 3064 is given, this information is of. 7 " delay line a $ input offered in another channel"; ν For example, information in channel 2 is transferred to the. Channel 1 transferred. If information passes the delay 3065, which has a delay time of 2 microseconds, exe is transferred to the next following channel, since the total delay time is now 256 microseconds minus one microsecond plus 2 microseconds, i.e. a total of 257 microseconds, ₀ Me iCanal transfer is dussh the 'program control on the AND gates 3065, 3055 and 306? determined ₀

Information passing through delay line 3048, are fed to the delay; line 3061 j which the . . 009839/1607

- ⁽ i7?> - SAD

Information back to its original channel position reset »The AND ~ gates 2066, 3055 and 3067 are then closed. The output information passes the VND gate 3082, which by programmed channel pulses for channel Y is controlled *

The channel pulses Y also become an inverter 3068 supplied »which in turn via the line 3071 the AND gate 3069 controlled. Since the channel pulses Y via the inverter 3068 run, the AND gate becomes 3069 and thus also the AND gates 3066, 3055 and 3067 blocked »

I,

As long as the channel pulses Y are not present, no signal is fed to the inverter 3068, it generates an output signal and opens the AND gate 3069, so that all channel pulses of the channels 1 to X, which are formed by a program, are sent to the AND- Gates 3066, 3055 and 5067 succeeded and this opens. A channel pulse Y on line 3050, which is fed to the inverter 3068, causes this to generate no output signal, whereby the AND gate 3069 is disabled. In this way, the AND gate 3055 is closed again via the line 3072 and the channel pulses on line 3073 have no effect "This Opera Lions, ^N, all information that is fed to the turret at any time at your disposal"

The delay line of the PIG. 122 can also be used as Shift registers are used. For this purpose γ / becomes the Information not from the output of delay line 3048 via line 30531 line 3054, AND gate 3055, delay line 3052, line 3056 and OR gate 3051 returned on the input of delay line 3048. the Rather, information is provided via line 3053, line 3074 * AND gate 3067, delay 306p, line 3075, and OR gate 3051 returned on delay line 3048. The Irogramiaeignale close the AND gate 3055 and open the AND gate 3067 via the lines 3057 and 3076 "Information, which are to be delayed via lines 3053 and 3077 given to the AND gate 3066 "

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ORIGINAL

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-flute delay arrangement & the f3G- ₀ 122 can be used fulls EiIa stepwise switchable delay line, If the arrangement is to be used in this white, the output Uim gate 3062 with then channel pulses the highest channels "? geoteue: rt. The AND gate 30699 which AND gates 3066 _f 3055 and 5067 * 3072 and 3079 controls via lines 3078, rtie receives pulses of all the channels through the line 3073rd In diesel · viewing ^ Y iet greater than 1 but less than y . _e AND gate 3066 is also controlled by the * program control via line 3081 «

Information which / · "delay line by twice the time of Vep * is delayed su, will guidance arrangement of the Kanalüher · in 3045 in the channel X-1 transferred" After '\\ simple Versögerun ^ .szeit the delay line is · "'the information in channel X-2, the information happens di« "; Delay 3065 with a time of 2 microseconds and succeeded: thus in the channel X * compartment dom the second pass through the delay line 3O4S accumulates the information in the channel Χ-Ί ·, the total delay is now 2 lengths of the delay ^ / · aeit of the communication , minus one microsecond ₀ After the information has passed the delay 3061 of the length of one, i microsecond, it is found in channel X and can thus be used for the delay arrangement of the PIG. Λ22 can be taken via the AND gate 3062 _& '*

The delay of information thus depends on the channel · '' from ugehörigkeit which her through the Kanalüberführunge-; order 3045 was given. It is possible to load the arrangement with information that was taken from the output line 3063 in the order of the channels. The remainder of the information about the delay 3065 or via the line 3064, depending on the direction of the sequence, is taken. If no change is desired in the content of the arrangement, all information passes through the delay 3052 and thus remains 'in. ">. by & ra channel,

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Should .the Vexzä & ezun & smoxdnung as Revolve * ar foe it «feitest © ''" the information is kept about the delay 3052 _o The arrangement · lean «contain as much information as channels are available» The maximum length of information is equal to the length of the delay line-- ', 3048 plus a MJÜcrösekimde. "Alle'Informationen leaded _β in their "channels

If the delay arrangement works as a controllable delay for an item of information, the circuit consists of the delay line 304-8 ₁ the ÜiTD-Toi * 3067 »the two microsecond delay line 3065 and the OR gate 3051 · The output of the arrangement is through the AND -Tor 3062 controlled with signals in channel Y * - ■ «.

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The delay position of the information unit is determined by the channel in which the information unit is located when it is entered be taken from channel X-4 "Verzögerimg 5065 wn two Kikrosekunden transferred the information in AEEN channel X ~ 2, when the information leaves the delay line 3048 ias .zweite time eo they böfindet himself in the channel X-3 · DI® delay 3065 then transfers the information to channel Xr-L. The information leaves delay line 3048 for the third time in channel X-2. Through delay 3065, it arrives in channel X. After the fourth pass through delay line 3048, the information is in Channel X-1. The delay 3061 of the length of one NükroBekttnde transfers the information to the channel X and the information can be taken from the overall arrangement via the AND gate 3063 _β The total delay time is then three times the length of the Umlaufas ®hn <§. Kimalüberführung plus *? dicroseconds; The information at the exit of the overall arrangement is always in channel X. If @@ göwünseht is _? the same operation- with a canal h & her- 'BeavsgenuoiSi ©? ·. to "start and end the information in a low? 3®sugSKUinme" channel, then the information about? das üH3) "! i? or 3066 and dia line 3064, instead of the DÜTD gate 3067 and the delay 3065."

The delay arrangement for the PIG · » 122 can also be used to close spaces between the information parts. Such an arrangement "then all compressor works") The length of the delay line 3048 is one character time minus one. Mi-cro-se'kun-de, "Each character is the delay line in the channel one fed * v / 'hen getting a new sign of the delay line is supplied werdsn ^y the advance lsufenden characters in the next higher channel Convicted i This takes place via the UlfD gate 3067 and the. Delay 3065 ^ on 2 microseconds »

As long as KEIC new dikes arrives _f "run" ti © slnga. ". Spaiciierten characters with the USÖ gate 3055 and the delay of a 3052 Mikroeekunäe"& o that the "55eicheii in

BATH

Channels remain,

As soon as the stored information from the delay arrangement is transmitted to another circle via the HKB gate 3062 βοΙΛ-ΐΏ- · laiifan dices® Irtforatat & Oh-ert via the AND gate 3067 and the 7 € »rGßg'i - =? Ung 3065 ₅ -so that all times of delay, arrangement in their sequence of stages can be omitted. This is achieved by »that the" JND-Sior 3062 is controlled in channel Y "

· A

A * ijechenachaltungj first Mssf

The arithmetic circuit works in binary decimal in the input, aag and output; \ The adding function of the arithmetic unit works with binary characters up to a total of 16 ». This makes it possible to keep the structure of the adding circuit simple. On the other hand, "processing the data becomes a bit more complicated" All input information is in channel 1, all output information in channel 4.

During the addition, the information 1 BIT-white is added to the information 2. The final ^ result ordered from a corrected and uncorrected ßtellenresultat "Dae uncorrected result WIW as a result one called" The corrected © result bears the Beseiekaimg result 2 "Uncorrected-results pushbutton 10 and Corrected results About 9 _r are the final result Nteett -Xtat 3 summarized _o The corrected Kl is 6 «renn Xk. a decimal system is calculated. "In a non-aezinii2! Ven system, K1 is equal to the difference between the highest possible place value ur.d 15 as the highest * v" rV in the tellfenresuj

In the subtraction operation, the pubtrahent compliment su 15 and * dc \ nn on the addiei-t werdon _c with siner ^ ubtraktioii; n with positive mea, rt 1 addieT-t- ^ e

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Claims (4)

Claims Circuit arrangement for a new delay line working as a memory, whose output is connected to its input, in particular for use as a buffer and for Transfer of information units from a memory, with direct access to another., characterized that the delay time of the delay line is shorter than the duration of the. information is that the connection of the output of the delay line with its input is made via several parallel branches, each of which has a delay element of different delay has, un da.;, the passage of the information; .tion units by the parallel branches and by analog and / or clock pulses sxe ^ exbar is. 2. Circuit arrangement n-.ch claim 1 for storing an information length of N routing units, thereby geke η η-z eich η et, aaa .ie /.rzögerungSuHU.r of the delay line (N-1) time units that aer the output of the delay line Is connected to your input via three: <parallel-connected branches, and that the delay. Un ₆ -s ^ songs in these branches have a delay time of 0, of 1 and of k. Have time units. 3. Circuit arrangement according to claim 2, characterized in that -, .ω 0.Lt- output of -Informationein-Initiate übez a delay element of a unit of time takes place. 4. Schaltu.ng.-anoränun ^ according to claim 1 .der 2, thereby ge k e η η ζ e i c b η e t, the entry of the information units is allowed by a bistable. Circuit done by den Inforz-ations'-itE in £. / instantaneous impulses _n. s- .r.er. .ir; outer state can be monitored. 009839/1607 ΪΑΟ ORIGINAL