DE3716554C1 - Method and circuit arrangement to secure digital memories - Google Patents

Abstract

A method and circuit arrangement to secure digital memories is specified. Using a generator polynomial, a single "target" check word to secure the whole memory is generated. For testing, an "actual" check word is formed over the whole memory using the same generator polynomial, and compared with the "target" check word. Inequality of the two check words then shows that an error has occurred (error recognition). Then, if the generator polynomial is suitable, correction of this error can be initiated (error correction). According to the invention, when a new memory word is written to the memory, arrangements are made to adapt the "target" check word to the changed memory contents, without having to read the whole memory.

Description

The present invention relates to a method and a circuit arrangement for securing digital memories according to the preambles of claims 1 and 12.

Various methods are known for making writable and re-readable digital memories to be provided with redundancy (test words) so that error detection, e.g. B. by word-by-word parity check, or error correction, e.g. B. SEC-DED code, single error correction, Double Error Detection (R. W. Hamming: Error Detecting and Error Correcting Codes, Bell Syst. Techn. J. 29, p. 147-160, April 1950) is made possible.

For memories that are made up of word-organized memory modules in which the Failure of a single memory chip causes so many errors per stored information, that SEC-DED codes are no longer sufficient for security purposes have been secured developed techniques that enable character-by-character correction, e.g. B. SBC-DBD- Codes, single byte correction, double byte detection (Shigeo Kaneda: single byte error Correction - Double Byte Error Detecting Code for Memory Systems, IEEE Transactions of Computers, vol. C-31, no. 7, p. 596-602, July 1982). All of these backup procedures has in common that a suitable test word is generated for each memory word and must be saved with. This leads to the fact that - depending on the respective Backup method and the memory word width - on average 10-100% additional Storage space is required to record the test words.

With only readable memories, e.g. B. PROM, EPROM, various methods are known, that secure the memory as a whole with a single check word for error detection, e.g. B. the column parity formation, in which a column by column over all words of the memory Parity formation is carried out and this test word is then also filed, checksum Methods in which algebraic summation is carried out over all memory words or a signature formation over all memory words with the help of CRC  Polynomials (H. Hölscher, J. Rader: Microcomputers in security technology, Verlag TÜV Rheinland, pp. 7.27-7.63, Cologne 1984, as well as D- Leisengang: classification and use of Signature registers for error detection in digital circuits, especially p. 97-104, Dissertation, Technical University of Munich 1983).

One advantage of the last-mentioned security techniques is the low memory requirement for the test information (one test word per saved memory area). It has a disadvantageous effect from that these backup techniques for read / write memory are not due to runtime reasons are practical since the entire memory is read out again after each write operation would have to be recalculated in order to recalculate the test word, which always saves the total memory.

The object of the present invention is a method and a circuit arrangement to provide writable and readable digital storage with a to save and / or test a single test word in such a way that an error detection or correction is made possible, the time required to generate the total check word after a write operation should be kept so low that a practical use of the overall storage backup procedure is made possible.

This backup is done with the help of a suitably chosen generator polynomial g (x) . Depending on the nature of the generator polynomial g (x) , error detection or correction is made possible (for more information, see FJ Furrer: Error-correcting block coding for data transmission, Birkhäuser Verlag, Basel, 1981, pp. 49-236; or also Shu Lin, Daniel J. Costello: Error Control Coding: Fundamentals and Applications, Prentice Hall, Englewood Cliffs NJ, 1983, pp. 111-121, 257-282).

The invention, as claimed in claims 1 and 12, achieves the object in that when a new memory word is written into the memory, the difference between the new and old memory word is formed and a change check word is generated using this difference which is added to the old total memory check word, so the total update memory check word, d. H. to those by writing adapt changed memory content.

A test word extraction after a write operation for a memory with n memory words would have a total thickness O (n) if all words had to be read. According to the embodiment of the invention according to claims 2 and 13, this effort is reduced to O (log₂ ( n )). For example, with n = 1000 words, the temporal ratio would be approximately 1000 to 10, which would be an improvement by a factor of 100.

The teaching of the invention according to claims 1 and 12, or the configuration the invention according to claims 2 and 13, allow any generator polynomials to be used for overall storage backup.

According to claim 3, a limitation of the generator polynomials g (x) to those which obey the condition x ^m = 1 mod g (x) leads to considerable speed improvements, since the change check word δ r (x) thereby becomes independent of the position in the memory and thus the successive calculation part according to equations (4) - (13) is omitted.

A further speed improvement is achieved according to claim 4 or 15 in that the generator polynomials obey the additional condition degree [g (x)] = m , where m represents the memory word length. In this case, there is a single generator polynomial according to the formula g (x) = x ^m + 1 for a given memory arrangement

δ r (x) = δ w (x) = w _old (x) + w _new (x) .

This highest possible simplification of the general generator polynomial, in which the modulo g (x) operation has not been carried out, represents in its technical implementation a column parity formation over all memory words, similar to that described in DE-OS 25 15 099.

A test procedure as claimed in claims 5 to 14 enables hidden from the user to detect errors in the total memory and to initiate a possible error correction.

An initialization of the target check word at the beginning of a memory backup period must be made once, can be carried out according to claims 6 or 7 will.

The method according to claim 6 is characterized in that it is very can be carried out easily and quickly since the memory and the target check word are only included must be pre-assigned with the value 0.

The method according to claim 7, however, does not clear the memory, but generates a Sollprüfwort r _to (x), which is suitably generated at the current memory contents. This method is particularly advantageous when the memory area to be protected also contains memory modules which can only be accessed by reading (e.g. EPROM), since these memory areas are then also protected by the test process.

In the claims 8 and 9, a self-test is claimed, each before Actual start of backup is activated and the correct functioning of the Test device displays. This happens because the test process is due to a If the target test word has not yet been initialized, errors are detected with a high probability, which are then regarded as an indication of the correct functioning of the memory.

In most cases, the backup obtained in this way is sufficient for the memory be. In the event that the permanent test procedure for diagnosis required, it should be excluded that incorrect data is reused by the processor can be supported by additional word-by-word parity protection Measure according to claim 10 early error detection can be achieved, already when reading an incorrect word this error due to the parity violation with is detected with a high probability.

The runtime-optimized reduced generator polynomial according to claim 4 can in particular advantageously with the help of an additional word-by-word parity protection for 1-bit Error correction according to claim 11 can be expanded. This shows one that occurred in the event of an error Parity violation of word parity indicates the incorrect word. The bit position of the Error is caused by the column parity violation due to the difference of the target check word and actual check word received. This error can therefore be corrected since its position determines is. With an additional parity control over the column and word parities 2-bit errors can be detected.

Formulas (1) to (20) are used to describe the method according to the invention. suitable, which are shown together with the most important terms in the appendix.

1 to 8 serve to describe the circuit arrangement according to the invention . It shows

Fig. 1 shows a data backup unit DE between processor and memory, which is composed of a difference calculation unit word DW, a Sollprüfwortberechnungseinheit SPW, and a sequence controller AS

Fig. 2, the difference word calculation unit DW in more detail

Fig. 3 shows the detailed representation in Sollprüfwortberechnungseinheit SPW together with a Teilprüfwortberechnungseinheit TPW

Fig. 4, the Teilprüfwortberechnungseinheit TPW with a selection circuit AW and partial multiplication circuits M _i

Fig. 5 shows the basic diagram of a multiplying circuit part M _i

FIG. 6 shows the data backup unit DE from FIG. 1 expanded to a data backup and test unit DTE , together with an address generator AG , a test word calculation and test unit PTE and a sequence control AS

Fig. 7, the test unit Prüfwortberechnungs- and PTE in detailed representation with the already known Teilprüfwortberechnungseinheit TPW

Fig. 8 is a simplified Prüfwortberechnungs- and test unit VPTE.

A simplified calculation example is developed in parallel with the description of the process and shows all required in the process as well as in the circuit arrangements Calculation steps.

To describe the method, a read / write memory consisting of n words w _{n -1} (x) is to be used below. . . w ₀ (x) of m bits are assumed. The total memory therefore has a capacity of n · m bits and is to be secured by a single test word, generated by a generator polynomial g (x) of degree r . For this purpose, the individual memory words are viewed in a row, and the resulting bit string is represented as a total memory polynomial in the form

The factor x ^im indicates the position of the memory word polynomial within the overall memory polynomial; for i = 1 the first word is shifted by one word width to the left of the zero memory word.

Example 1 Total memory polynomial

A memory arrangement consisting of n = 4 memory words each with m = 3 bits and with the memory allocation

can be represented as the total memory polynomial S (x) in the following way:

A distinction must be made between three phases for operations with the memory:

a) Initialization phase

It is used to bring the memory into a defined initial state, in which the target check word r _soll (x ) is calculated for the current memory content (which can also have previously been assigned any words). From this point in time, memory changes that have arisen due to errors can be detected by a subsequent redefinition of the actual test word r _ist (x) and comparison with the target test word r _should (x) .

b) Reading phase

Since a memory read has no influence on the target check word, and there When reading, no error check can be carried out either additional actions required.

c) Writing phase

Since the memory content is changed when a word is written into the memory, the target check word must also be adapted to this new memory content. Instead of a complete recalculation of the target test word by reading out the entire memory content (which is not feasible for time reasons and would also conceal any errors), the differential change contribution of the new memory word δ w (x) is converted into a differential change test word δ r ( x) , which - added to the target check word - makes the necessary adjustment to the changed memory content. For this purpose, according to formula (1), the difference between the old memory content w _old (x) and the new memory word w _new (x) to be written is formed by modulo-2 addition (in the polynomial calculations, all additions and subtractions correspond to a modulo-2 additive in places) . The change test word δ r (x) is calculated from this difference word δ w (x) according to formula (2), the factor x ^p indicating the position of the word to be newly written (with m bit word length and i th word, p = m results · I ). The mod g (x) operation corresponds to a residual formation by polynomial division.
Eg can

r (x) = a (x) mod g (x)

are formed by the following polynomial division

The Änderungsprüfwort δ r (x) thus formed is in accordance with formula (3) to the old Sollprüfwort r _to (x) mod-2 added, forming the new, adapted to the modified memory contents _to Sollprüfwort r (x).

Example 2 Initialization phase

A target check word initialization is now to be carried out for the memory arrangement from example 1. A generator polynomial g (x) = x ³ + x + 1 is assumed. For initialization, the memory should not be deleted here, but a target check word r _to match the memory content from example 1 _{should be} (x) calculated according to the formula r _should (x) = S (x) mod g (x) . The polynomial division is carried out by hand:

The Sollprüfwort results from the division remainder to r _to (x) = x ² + x +. 1

Example 3 Writing phase

Now the value 001 should be written in word i = 2 of the memory.

The calculation of the new target test word r target (x), which is adapted to the changed memory content _, is carried out according to formulas (1) to (3) in the following way:

(1) w w (x) = w _old (x) + w _new (x) = x + 1 010 + 001 = 011 (2) δ r (x) = ( δ w (x) x ^im ) mod g (x) = ( x + 1) x ^{2 · 3} mod ( x ³ + x + 1) = (x ⁷ + x ⁶ ) mod (x ³ + x + 1 )

Residual formation by division by hand:

δ r (x) = x ² 100

(3) r _target (x) = r _target (x) + δ r (x) = ( x ² + x + 1) + (x ² ) = x + 1 011

The entire new memory content by the generator polynomial should now be checked again be divided:

A comparison of this remainder of the division with r _soll (x) shows that the method according to formulas (1) to (3) has correctly adjusted the target check word to the memory content changed by writing word 2.

The calculation according to formula (2) can be too time-consuming for some applications with a large storage capacity. This can be remedied by a method, which leads from an effort that increases linearly with the storage capacity to an effort that increases with log₂ to the capacity. This happens because the multiplication with x ^p is composed of suitable partial multiplications with x ^{2 i} according to formula (5), the factor p being broken down into powers of two according to formula (4). For example, x 13 can be represented as follows

x ¹³ = x ^{. . .0 · 2⁴ + 1 · 2³ + 1 · 2² + 0 · 2¹ + 1 · 2⁰} = 1 · x ^{1 · 2³} · x ^{1 · 2²} · 1 · x ^{1 · 2⁰} .

Formula (6) then shows how δ r (x) is formed from δ w (x) using this transformation. In formula (8) the same situation is shown again in somewhat compressed form by substitution (7). The formulas (9) to (12) show how the final difference test word δ r (x) is obtained by successive partial multiplications with the corresponding factors P _i . The individual factors P _i have, depending on the power of two decomposition of p, either the value x ⁰ or x ^{2 i} . These partial multiplications are carried out very quickly in corresponding multiplication circuits, since the product of the respective partial multiplication is available as an exclusive-OR combination rule for the corresponding generator polynomial and the respective power of x .

This linking rule can be used in simple cases (such as the one specified below Example) can be done by hand; in the generator polynomials relevant in practice For reasons of complexity, this must be done using suitable computer calculations respectively.

Formula (13) shows how the multiplication with the factor x ^{2 i} from formula (11) can be carried out very quickly with the help of modulo-2 additions (exclusive-OR combination).

The coefficients r _k ^{(i -1)} make this the polynomial coefficients of the multiplicand δ r ^{(i -1)} represent the coefficients t _{j, k} ⁽ⁱ⁾ represent the combination rule for a multiplication by a factor x ^{2 i} and subsequent modulo g (x) operation.

These coefficients t _{j, k} ⁽ⁱ⁾ must therefore be calculated in advance for the determined and fixed generator polynomial g (x) and the respective multiplicands x ^{2 i} .

Example 4 Determination of the linking rule

For the generator polynomial g (x) = x ³ + x + 1 used in the examples, the combination _coefficients t _{j, k} should now be used for multiplications with the factors

P ₀ = x ^2⁰ = x, P ₁ = x ^2¹ = x ², P ₂ = x ^2² = x ⁴ and P ₃ = x ^2³ = x ⁸

be determined. For this purpose, a general polynomial r (x) , which represents the first multiplicand, is multiplied by the corresponding power of x and reduced modulog (x) . The coefficients of this remainder of the division then correspond to the combination coefficients t _{j, k} .
Multiplication with P ₀ = x ^2⁰ = x:

(r (x) x) mod g (x) = [(r ₂ x ² + r ₁ x ² + r ₁ x + r ₀ ) · x] mod g (x) = (r ₂ x ³ + r ₁ x ² + r ₀ x) mod g (x)

Residual formation by division:

Multiplication by P ₁ = x ^2¹ = x ²:

(r (x) · x ² ) mod g (x) = ( ₂ x ⁴ + r ₁ x ³ + r ₀ x ² ) mod g (x)

Residual formation by division:

analogously to this then arise

In summary, the advantage of this method can be illustrated as follows:
The formation of the expression

δ r (x) = ( δ w (x) x ^p ) mod g (x)

from formula (2) is reduced to a maximum of log₂ (p) partial multiplication, the result coefficients of such a partial multiplication being a modulo-2 sum with a maximum of r summands.

Example 5 Fast calculation of the change check word

In example 3, the change check word δ r (x) was calculated after the write operation by an explicit division by hand according to formula (2). The fast algorithm according to formulas (4) to (13) should now be used for the same example:

δ w (x) = w _old (x) + w _new (x) = x + 1 and p = i · m = 2 · 3 = 6,

since the 2nd memory word was written.  

According to formula (4), p is broken down into

p = 0 · 2⁰ + 1 · 2¹ + 1 · 2² + 0 · 2³,
With
t = [log₂ ( p _max )] = [log₂ (9)] = [3.17] = 3
k ₀ = 0, k ₁ = 1, k ₂ = 1, k ₃ = 0

this gives formula (5) for x ⁶ = x ² · x ⁴.

In this example, only two partial multiplications with the factors P ₁ = x ² and P ₂ = x ⁴ have to be carried out, since a multiplication with the factors P ₀ = 1 and P ₃ = 1 does not change the result. The formulas (9) - (12) thus result in

δ r ⁽⁰⁾ (x) = [ δ w (x) · 1] mod g (x) = δ w (x) δ r ⁽¹⁾ (x) = [ δ r ⁽⁰⁾ (x) · P ₁ ] mod g (x) = [ δ w (x) · P ₁] mod g (x) δ r ⁽²⁾ (x) = [ δ r ⁽¹⁾ (x) · P ₂] mod g (x) δ r (x) = [ δ r ⁽²⁾ (x) · 1] mod g (x) = δ r ⁽²⁾ (x)

Using the linking matrices T ⁽¹⁾ and T ⁽²⁾ determined in Example 4, the following results from formula (13):

δ r ⁽¹⁾ (x) = [ δ w (x) · P ₁] mod g (x) = ( t _0.0 ⁽¹⁾ · r ₀ + t _0.1 ⁽¹⁾ · r ₁ + t _{0 , 2} ⁽¹⁾ · r ₂) · x ⁰
+ ( t _1.0 ⁽¹⁾ · r ₀ + t _1.1 ⁽¹⁾ · r ₁ + t _1.2 ⁽¹⁾ · r ₂) · x ¹
+ ( t _2.0 ⁽¹⁾ · r ₀ + t _2.1 ⁽¹⁾ · r ₁ + t _2.2 ⁽¹⁾ · r ₂) · x ²
= (0 · 1 + 1 · 1 + 0 · 0) x ⁰
+ (0 · 1 + 1 · 1 + 1 · 0) x ¹
+ (1 · 1 + 0 · 1 + 1 · 0) x ²
= x ² + x + 1

w r (x) = ( δ r ⁽¹⁾ (x) · P ₂) mod g (x) = (0 · 1 + 1 · 1 + 1 · 1) x ⁰
+ (1 x 1 + 1 x 1 + 0 x 1) x 1
+ (1 · 1 + 1 · 1 + 1 · 1) x ²
= x ²

This change check word δ r (x) obtained in this way is of course identical to that from example 3. The advantage of this method, however, only becomes apparent when the values of p are larger. For example, for p = 1000 in Example 3 a division with a thousand-digit dividend would have to be carried out, while for the accelerated method only 6 partial multiplications with the factors P ₉, P ₈, P ₇, P ₆, P ₅ and P ₃ would be required.

This accelerated method can generally be implemented for any memory and any generator polynomial. Process simplifications can be achieved for restrictions in the choice of the generator polynomial. The restriction according to formula (14) means that the generator polynomial g (x) is contained as a factor in the polynomial x ^m + 1 and leads to the fact that formula (2) is simplified to formula (15); the change check word δ r (x) thus only depends on the difference word δ w (x) , but no longer on the position in the memory, which saves the need to carry out the partial multiplications (formulas 4-13). Restrictions in the choice of the generator polynomial therefore lead to acceleration of the algorithm, but are purchased with limited performance. These generator polynomials, which are restricted in this way, can then - if they are implemented as the only security measure - only be used for error detection and no longer for error correction.

An even stronger restriction of the generator polynomial is represented by formula (16) in conjunction with formula (14). Here only one generator polynomial is possible, namely g (x) = x ^m + 1. Using this strongly restricted generator polynomial simplifies the formation of δ r (x) according to formula (17). The change test word is identical to the difference word δ w (x) and can therefore be added directly to the target test word according to formula (3). A 1-bit error correction is also possible for this generator polynomial if an additional word-wise parity protection is implemented.

The circuit arrangements according to the figure drawings 1-5 completely reproduce the general method for any generator polynomials g (x) . Fig. 1 shows on the left side of the backup unit EN the interface to the processor, and on the right side of the interface to memory; Inserted between them is a difference word calculation unit DW in the bidirectional data bus. The result δ w (x) of this difference word calculation unit, together with the address information p, which is provided by the address bus, arrives at a target test word calculation unit SPW . A sequence control AS ensures the time coordination.

The difference word calculation unit DW is shown in more detail in FIG. 2. It enables unhindered reading of the memory via a register R 1 during the reading phase. During a write phase, the new memory word w _new (x) is temporarily stored in registers R 1 and R 2 ; at the same time, the old memory content w _old (x) is stored in a register R 3 . As soon as this has happened, the difference word according to formula (1) is formed via the adder A 1 and, in parallel, the new memory word is written into the memory from register R 1 (read-modify-write cycle).

In Fig. 3 is shown how by means of a Teilprüfwortberechnungseinheit TPW of δ w (x) and p generated Änderungsprüfwort δ r (x) by means of the adder A 2 to Sollprüfwort r _ref (x) is added into register RS of the formula ( 3). The partial check word calculation unit TPW is shown in more detail in FIGS. 4 and 5. A selection circuit AW generates the corresponding selection signals Sel _i from the address information p . An active selection signal causes a corresponding partial multiplication to be carried out in a partial multiplication circuit M _i ; an inactive selection signal leads to the switching through of the data path in the partial multiplication circuit M _i without multiplicative linkage. The difference word δ w (x) thus runs through all the partial multiplication circuits M _i and experiences a partial multiplication according to formula (11) when the selection signal is active.

An exemplary embodiment of such a partial multiplication circuit M _i is shown in FIG. 5. The link part on the right-hand side represents the route control depending on the selection signal, the multiple exclusive-OR links represent the mod-2 additions for the individual polynomial coefficients according to formula (13), the exact linkage of the inputs of the exclusive Or gate with the circuit inputs R _{r -1} ^{( i -1)} . . . R ₀ ^{( i -1) is} given by the pre-calculated coefficients t _{j, k} ⁽ⁱ⁾ according to formula (13).

Example 6 Partial multiplication circuits

In this example, the partial multiplication circuits are also to be specified for the already known memory arrangement. For the change test word calculation, the circuits M ₀, M ₁, M ₂ and M ₃ are required for the partial multiplications with the corresponding factors x ^2⁰ , x ^2¹ , x ^2² and x ^2³ (see example 5). The exact wiring is to be given here using the designations from FIG. 5.

A partial multiplication circuit M _i has 3 input data lines r ₀ ^{( i -1)} for this example. . . r ₂ ^{( i -1)} , and 3 output data lines r ₀ ⁽ⁱ⁾ . . . r ₂ ⁽ⁱ⁾ .

The multiple exclusive-OR gates are wired according to the coefficients t _{j, k} (see example 4, matrices T ⁽⁰⁾ ... T ⁽³⁾ .

As a Boolean equation, they result here in the following way:

M ₀: h ₀ ⁽⁰⁾ = r ₂ ^(-1)
h ₁ ⁽⁰⁾ = r ₀ ^(-1) ⊕ r ₂ ^(-1)
h ₂ ⁽⁰⁾ = r ₁ ^(-1)

M ₁: h ₀ ⁽¹⁾ = r ¹ ⁽⁰⁾
h ₁ ⁽¹⁾ = r ¹ ⁽⁰⁾ ⊕ r ₂ ⁽⁰⁾
h ₂ ⁽¹⁾ = r ₀ ⁽⁰⁾ ⊕ r ₂ ⁽⁰⁾

M ₂: h ₀ ⁽²⁾ = r ₁ ⁽¹⁾ ⊕ r ₂ ⁽¹⁾
h ₁ ⁽²⁾ = r ₀ ⁽¹⁾ ⊕ r ₁ ⁽¹⁾
h ₂ ⁽²⁾ = r ₀ ⁽¹⁾ ⊕ r ₁ ⁽¹⁾ ⊕ r ₂ ⁽¹⁾

M ₀: h ₀ ⁽³⁾ = r ₂ ⁽²⁾
h ₁ ⁽³⁾ = r ₀ ⁽²⁾ ⊕ r ₂ ⁽²⁾
h ₂ ⁽³⁾ = r ₁ ⁽²⁾

where the symbol ⊕ represents an exclusive-OR link.

Fig. 6 shows the extension of the backup unit to the backup and DE test unit DTE. In this case, the entire memory is read out in an interruptible test cycle and an actual test word valid at the current time is generated, which is then compared in the test word calculation and test unit PTE with the target test word. If the two test words are not identical, an error signal is generated. The address generator AG runs through all memory addresses, and the address generated in each case reaches the memory via the multiplexer MX on the address bus. The memory word read thereby arrives z. B. via register R 4 bypassing the difference word calculation unit directly to the test word calculation and test unit PTE . This is a possible embodiment in order to ensure that the read memory word and not a difference of two words reaches the inputs of the test word calculation and test unit. Another possibility would be to go through the difference word calculation unit DW without register R 4 , the data path coming from the processor being set to zero; according to formula (1) or Fig. 2 would then be δ w = 0 - w _read = w _read (since addition and subtraction are identical in the polynomial operations!).

For further monitoring of the signal flow, Fig. 7 should now be considered. The partial test word calculation unit TPW , already known from FIG. 4, forms during a test cycle from δ w = w _read and the corresponding address p a change test word δ r (x) which is transferred via the data switch and the adder A 2 to the register RI, which has the size r _is (x) , modulo 2 is added.

When the actual test word is formed, δ w (x) does not represent a difference value, but the memory word just read; Thus, the change check word δ r (x) does not contain a differential change amount, but rather the check word portion of this read word. The term change check word w r (x) has been retained because this circuit part is identical to that which calculates the change check word.

This register RI, which has to be cleared at the beginning of a test cycle, contains after completion of a complete test cycle, that is, when all of the memory addresses have been read out once by the address generator, the valid at the current time Istprüfwort which then r by the comparator V 2 with the Sollprüfwort _to (x) is compared in register RS and leads to the generation of an error signal in the event of an error. This error signal can then be used to initiate an error correction, the difference between r _ist (x) and r _soll (x) representing the error syndrome required for the correction and well known in the coding theory.

Example 7 Test process

For this example, the original memory content from example 3 is assumed.

An actual test word r _ist (x) is now formed from the current memory content by the test procedure.

The following table shows in column AG the memory word currently addressed by the address generator, column p the associated memory position, column w w contains this memory word and δ r contains the test word portion belonging to this memory word ( δ r = [ δ w · x ^p ] mod g (x )), which is then added to the old content of r _ist . The actual check word is initially set to 0.

First of all, the actual check word is now to be formed using the memory content which has not yet been falsified will.

From r _ist = 111 = r _should be seen that no error has been detected.

Now the actual check word should be formed after the error situation has occurred:

Now r _ist = 010 ≠ r _soll = 111. From this inequality of the test words it can be concluded with certainty that an error has occurred.

This test procedure is because it covers the entire memory and therefore takes some time designed interruptible according to the invention. When the processor is reading or screaming want to run on the memory, the test cycle can be interrupted, e.g. B. after completion of a memory read and partial check word calculation step. By the precautions described below ensure that the test cycle must continue after the interruption can be done without a wrong one by a previous processor write operation Actual check word has arisen.

As described initially, a processor write operation will result in customization of the Target test word by adding up a suitably calculated differential test word. If now a write operation to an address is carried out by the test process in the currently running test cycle has already been recorded, would be at the end of the test process carried out comparison of target and actual test word result in a difference and display a nonexistent error, since the target check word is due to the write operation was adapted to the new memory content, but the actual check word via the unchanged memory content was formed.

To prevent this case, the comparator V 1 ( FIG. 6) is provided according to the invention. It compares the address pending on the address bus with a processor write request with the address of the address generator AG currently used by the test process. In the case described above, that is, when a memory location detected by the test process is rewritten, the change test word δ r (x) ( FIG. 7) calculated by the partial test word calculation unit is transmitted via the data switch DAW both for the target test word in RS and for the actual test word in RI added up. This then leads to the fact that the change that has occurred as a result of the write operation is also taken into account in the actual check word, so that in the error-free case — that is to say if no errors have occurred in the memory — the target and actual check words match.

Example 8 Interruption of the test process

For this example, the memory allocation from Example 3 is again assumed; it  no error occurs.

now the formation of the actual test word should be considered in the event that the test Operation has already processed word 0 to word 2, but before processing Word 3 is interrupted by the write operation:

Interrupt by writing operation, δ r = 100 (see Example 3) at r _soll on added: r _soll: = 111 + 100 = 011. As word 2 has already been processed by the testing operation, is δ r on r _is added: _R = 001 + 100 = 101:

After processing the third value, r _is = 011 and r _target = 011 are identical, no error was detected.

The initialization of a memory that has just been switched on, which may then be random values can be done in different ways. An easy way consists of zeroing the total memory. . . 0 to describe. The target check word needs then not to be calculated, it is also directly with 0. . . 0 described. The The memory and the target check word are now in a precisely defined initial state. From now the memory is secured; subsequent write operations become the target check word  errors and errors that have occurred in the memory can be detected by the test process will.

Another option for initializing the memory is to accept the "random" memory content as correct and to generate a matching check word and store it in register RS . This also ensures that the target and actual test words match in the error-free state. The advantage of this method is that the memory content does not have to be deleted, ie the address space of the memory can also contain 'only readable' memories (e.g. EPROM), which are then also saved (see Example 2).

An exemplary configuration of the self-test characteristic can be carried out that after switching on the memory the mostly random content of the memory in not yet initialized state is detected by the test process, with high probability the actual check word thus generated with the randomly generated by switching on Target check word does not match. This "error message" can then be used as an indication of a correct functioning of the test process.

Another way of generating an "error message" for self-test purposes is to define the memory, e.g. B. to pre-assign zero, and to prevent the generation and addition of the corresponding change check word w r (x) during this pre-assignment phase. As a result, memory situations are generated with a probability bordering on certainty which lead to the test words being inequality during the test cycle.

In FIG. 8 is a simplified Prüfwortberechnungs- and test unit VPTE is shown that uses the restricted generator polynomial g (x) = x ^m +1. In terms of circuitry, this corresponds to column parity formation across all memory words.

A particularly advantageous embodiment of the method is that in addition to a simplified parity check of the memory was carried out in simplified test word calculation becomes. This makes it easy to get a 1-bit error in memory correct, because in the event of a simple 1-bit error, the exact location can be and column parity is known.

Another possible application of such an additional word-by-word parity lock  is given in early error detection. This is useful if prevented should read the faulty word from the processor after a memory error occurs and further processed before the error is recognized after the end of the test cycle and reported. In this case, the simple word-by-word parity assurance early error detection when reading the corresponding incorrect word enabled by a new parity check when reading.  

attachment Designations

n Number of memory words in memory m Number of bits per memory word w _i (x) memory word i in polynomial representation S (x) Total memory in polynomial representation

w _old (x) old memory information in the memory w _new (x) new memory information to be written δ w (x) difference between new and old memory word, corresponds in places to modulo 2 addition g (x) generator polynomial for security measure, degree of polynomial r g (x) = g _r x ^r + g _{r -1} x ^{r -1} + · · · + g ₁ x + g ₀, the polynomial coefficients g _i can have the values 0 or 1 mod g (x) residual formation with respect to the polynomial g (x)
The representations r (x) = a (x) mod g (x) , as well The quotient q (x) has no meaning needed is only the remainder r (x) r _to (x) Sollprüfwort, emerged at the time of the begin,

r _is (x) actual test word, generated by a memory test,

δ r (x) change check word, generated due to previous write operation p position of memory information within the memory, p = i · m AG address generator AS sequence control AW selection circuit DAW data switch DE data backup unit DTE data backup and test unit DW difference word calculation unit M _i partial multiplication circuit (i) MX multiplexer PTE Test word calculation and test unit RI Register for actual test word RS Register for target test word SPW Target test word calculation unit TPW Partial test word calculation unit VPTE Simplified test word calculation and test unit

Formulas

Claims (15)

1. A method for securing digital memories, wherein r _{is to} when initializing security information in the form of a single Sollprüfwortes (x) added is that g (x) is generated from the memory contents using a predetermined generator polynomial, and r _is when testing a Istprüfwort ( x) is formed with the same generator polynomial and, in the event of an error, depending on the nature of the two test words, an error detection or an error correction is carried out, characterized in that the new memory information w _new (x) with when information is written into the memory to form the new desired test word the old memory information w _alt (x) modulo 2 at this point is added and the result δ w (x) (difference word) is multiplied by the factor x ^p , where p indicates the position of the relevant memory information within the memory, and that from Result, a residual formation modulo g (x) is carried out and the resulting result δ r (x) ( Change test word) with the old target test word r _should (x) modulo 2 is added. 2. The method according to claim 1, characterized in that the difference word δ w (x) to form the change test word δ r (x) is multiplied in successive partial multiplication steps depending on the address information p by corresponding powers of x obtained according to a dual number decomposition of p , the result of each multiplication depending on the respective input value for a fixed generator polynomial g (x) and each required power of x is predicted. 3. The method according to claim 1, characterized in that the generator polynomial g (x) is chosen so that it satisfies the equation 0 = x ^m + 1 mod g (x) , where m is the number of bits per memory word. 4. The method according to claim 3, characterized in that the generator polynomial is chosen so that it corresponds to the additional condition degree [g (x)] = m . 5. The method according to claim 1, 2, 3 or 4, characterized in that an actual test word r _is cyclic (x) is formed from the current memory content, this is compared with the stored target test word r _should (x) and if the two test words do not match detected error is reported or an error correction is initiated, the formation of this actual check word can be interrupted at certain times, so that reading or writing of the memory is made possible if necessary, and that this test procedure in the event of an interruption by a memory write operation in the case That the memory access takes place in a memory area already processed by the test process, is modified so that the change test word is added to both the actual test word and the target test word, so that the test process can be continued after the write operation, and not again from the beginning must start at. 6. The method according to claim 1, characterized in that for initializing a valid target check word the entire memory including the target check word with zero is described. 7. The method according to claim 1, characterized in that for the initialization of a valid target check word this is initially set to zero, that each memory word w (x) is successively read and multiplied by the corresponding factor x ^p , where p is the position of the corresponding memory information within of the memory indicates that the result is a residual formation modulo g (x) and the resulting value δ r (x) is added to the old actual test word r _ist (x) modulo 2. 8. The method according to claim 5, 6 or 7, characterized in that after switching on the memory of the test process a predetermined time with a not yet initialized Debit check word works. 9. The method according to claim 5, 6 or 7, characterized in that after switching on of the memory during the initialization generating a change check word is prevented.   10. The method according to claim 5, characterized in that a during the test process additional word-by-word parity check is performed, and that by interacting the test process with the parity check prevents a memory word, which has been identified as faulty by the parity check after reading is used before the test process detects this error and then could correct. 11. The method according to claims 4 and 5, characterized in that during the test process an additional word-by-word parity check is performed, and that by the Interaction of the test process with the parity check a correction of a 1-bit Error and the detection of a 2-bit error at any point in the memory is carried out. 12. Circuit arrangement for the selective writing of memory information to a specific, freely selectable memory location in a digital memory which has been secured during initialization by a single target test word r _should (x) with the aid of a predetermined generator polynomial g (x) , characterized in that a difference word calculation unit ( DW) is provided which, when writing to the memory, stores the new memory information w _new (x) in register R 2 with the old memory information w _old (x) in this position in register R 3 by an adder ( A 1 ) modulo 2 into one Difference value δ w (x) added, and a target check word calculation unit (SPW), in which the difference word δ w (x) together with the associated address information p in a partial check word calculation unit (TPW) converted to a change check word δ r (x) and that this change check word δ r (x) r with the old Sollprüfwort _to (x) in register RS for new Sollprüfwort r (x) _should by e an adder ( A 2 ) modulo 2 is added. 13. Circuit arrangement according to claim 12, characterized in that in the partial test word calculation unit (TPW) the difference word δ w (x) to form the change test word δ r (x ) passes through successive multiplication circuits (M _i ) , the inputs of which depend on the generator polynomial g ( x) are precalculated, exclusively - or - linked and then linked with a selection line (Sel _i ) , which is activated based on the address information p by a selection circuit (AW) . 14. Circuit arrangement according to claim 12 or 13, characterized in that in a data backup and test unit (DTE) during a test cycle with the help of an address generator (AG) all memory words are cyclically addressed via a multiplexer (MX) and a read value via a register (R 4) together with the address p within a Prüfwortberechnungs- and test unit (PTE) using the Teilprüfwort calculation unit (TPW) to a Änderungsprüfwort δ r (x) is linked which r after passing through a data switch (DAW) with the Sollprüfwort _to (x) in register RS by an adder ( A 3 ) is exclusive - or linked, and that at the end of each test cycle, that is to say after all addresses have been run through, the target and actual test words are compared using a comparator ( V 2 ) , wherein if the two check words do not match, an error signal is generated and that each test cycle is interrupted by a read or write operation can, wherein the Änderungsprüfwort generated by a write operation δ r (x) always r via the data switch (DAW) with the Sollprüfwort _to (x) exclusive - or is linked, and in that upon an interruption by a memory write operation in the event that the memory access in a memory area already processed by the test process, the change test word is linked exclusively with the actual test word in register RI by the adder A 2 , and also with the target test word - or -, so that the test process can be continued after the write operation, and not again must start again from the beginning. 15. Circuit arrangement according to claim 14, characterized in that in a simplified test word calculation and test unit (VPTE) the difference word δ w (x) is linked directly or exclusively via the data switch (DAW) to the target test word or the actual test word.