CH503376A - Verfahren zum Zusammenstellen von Maskensätzen, insbesondere für die Herstellung von Halbleitervorrichtungen - Google Patents

Verfahren zum Zusammenstellen von Maskensätzen, insbesondere für die Herstellung von Halbleitervorrichtungen

Info

Publication number
CH503376A
CH503376A CH1672769A CH1672769A CH503376A CH 503376 A CH503376 A CH 503376A CH 1672769 A CH1672769 A CH 1672769A CH 1672769 A CH1672769 A CH 1672769A CH 503376 A CH503376 A CH 503376A
Authority
CH
Switzerland
Prior art keywords
manufacture
semiconductor devices
mask sets
assembling mask
assembling
Prior art date
Application number
CH1672769A
Other languages
English (en)
Inventor
Agusta Benjamin
Norman Kuschel William
Harry Depuy Arthur
Jit Sahni Ravinder
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH503376A publication Critical patent/CH503376A/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • D—TEXTILES; PAPER
    • D06—TREATMENT OF TEXTILES OR THE LIKE; LAUNDERING; FLEXIBLE MATERIALS NOT OTHERWISE PROVIDED FOR
    • D06F—LAUNDERING, DRYING, IRONING, PRESSING OR FOLDING TEXTILE ARTICLES
    • D06F15/00—Washing machines having beating, rubbing or squeezing means in receptacles stationary for washing purposes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Textile Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
CH1672769A 1968-11-19 1969-11-11 Verfahren zum Zusammenstellen von Maskensätzen, insbesondere für die Herstellung von Halbleitervorrichtungen CH503376A (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US77701268A 1968-11-19 1968-11-19
US77701168A 1968-11-19 1968-11-19
US77701468A 1968-11-19 1968-11-19
US77701368A 1968-11-19 1968-11-19

Publications (1)

Publication Number Publication Date
CH503376A true CH503376A (de) 1971-02-15

Family

ID=27505744

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1672769A CH503376A (de) 1968-11-19 1969-11-11 Verfahren zum Zusammenstellen von Maskensätzen, insbesondere für die Herstellung von Halbleitervorrichtungen

Country Status (7)

Country Link
US (4) US3615464A (de)
CH (1) CH503376A (de)
DE (1) DE1957788B2 (de)
FR (4) FR2024109A1 (de)
GB (1) GB1281933A (de)
NL (1) NL6917425A (de)
SE (1) SE362538B (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3950170A (en) * 1969-12-02 1976-04-13 Licentia Patent-Verwaltungs-G.M.B.H. Method of photographic transfer using partial exposures to negate mask defects
US3698072A (en) * 1970-11-23 1972-10-17 Ibm Validation technique for integrated circuit manufacture
US3751647A (en) * 1971-09-22 1973-08-07 Ibm Semiconductor and integrated circuit device yield modeling
US3795975A (en) * 1971-12-17 1974-03-12 Hughes Aircraft Co Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns
US4309811A (en) * 1971-12-23 1982-01-12 Hughes Aircraft Company Means and method of reducing the number of masks utilized in fabricating complex multilevel integrated circuits
US3803562A (en) * 1972-11-21 1974-04-09 Honeywell Inf Systems Semiconductor mass memory
US4131472A (en) * 1976-09-15 1978-12-26 Align-Rite Corporation Method for increasing the yield of batch processed microcircuit semiconductor devices
US4394437A (en) * 1981-09-24 1983-07-19 International Business Machines Corporation Process for increasing resolution of photolithographic images
EP0126786B1 (de) * 1983-05-25 1987-04-01 Ibm Deutschland Gmbh Verfahren zum Übertragen eines Musters in eine strahlungsempfindliche Schicht
US4608649A (en) * 1983-06-27 1986-08-26 International Business Machines Corporation Differential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical design
US4607339A (en) * 1983-06-27 1986-08-19 International Business Machines Corporation Differential cascode current switch (DCCS) master slice for high efficiency/custom density physical design
US4615010A (en) * 1983-06-27 1986-09-30 International Business Machines Corporation Field effect transistor (FET) cascode current switch (FCCS)
JPH073865B2 (ja) * 1984-08-07 1995-01-18 富士通株式会社 半導体集積回路及び半導体集積回路の試験方法
US4796194A (en) * 1986-08-20 1989-01-03 Atherton Robert W Real world modeling and control process
US4952522A (en) * 1987-06-30 1990-08-28 Mitsubishi Denki Kabushiki Kaisha Method of fabricating complementary semiconductor integrated circuits devices having an increased immunity to latch-up
US4880754A (en) * 1987-07-06 1989-11-14 International Business Machines Corp. Method for providing engineering changes to LSI PLAs
US4847183A (en) * 1987-09-09 1989-07-11 Hewlett-Packard Company High contrast optical marking method for polished surfaces
JPH03139821A (ja) * 1989-10-25 1991-06-14 Toshiba Corp 微細パターンの形成方法
TW248612B (de) * 1993-03-31 1995-06-01 Siemens Ag
KR0128828B1 (ko) * 1993-12-23 1998-04-07 김주용 반도체 장치의 콘택홀 제조방법
GB2295031A (en) * 1994-11-08 1996-05-15 Hyundai Electronics Ind Projection printing using 2 masks
KR0156316B1 (ko) * 1995-09-13 1998-12-01 김광호 반도체장치의 패턴 형성방법
US5793650A (en) * 1995-10-19 1998-08-11 Analog Devices, Inc. System and method of identifying the number of chip failures on a wafer attributed to cluster failures
US5871889A (en) * 1996-06-14 1999-02-16 Taiwan Semiconductor Manufacting Company, Ltd. Method for elimination of alignment field gap
JPH10229174A (ja) * 1997-02-18 1998-08-25 Mitsubishi Electric Corp 半導体記憶装置の製造方法
DE19956250C1 (de) * 1999-11-23 2001-05-17 Wacker Siltronic Halbleitermat Kostengünstiges Verfahren zur Herstellung einer Vielzahl von Halbleiterscheiben
US6274883B1 (en) * 1999-12-13 2001-08-14 Orient Semiconductor Electronics Ltd. Structure of a ball grid array substrate with charts for indicating position of defective chips
US7346470B2 (en) * 2003-06-10 2008-03-18 International Business Machines Corporation System for identification of defects on circuits or other arrayed products
US7752581B2 (en) * 2003-06-10 2010-07-06 International Business Machines Corporation Design structure and system for identification of defects on circuits or other arrayed products
US7260442B2 (en) * 2004-03-03 2007-08-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system for mask fabrication process control
TW200746259A (en) * 2006-04-27 2007-12-16 Nikon Corp Measuring and/or inspecting method, measuring and/or inspecting apparatus, exposure method, device manufacturing method, and device manufacturing apparatus
US8023102B2 (en) * 2008-04-18 2011-09-20 International Business Machines Corporation Test method for determining reticle transmission stability
US8222090B2 (en) * 2009-08-04 2012-07-17 Fairchild Semiconductor Corporation Modular die and mask for semiconductor processing
US20150146179A1 (en) * 2013-11-25 2015-05-28 Takao Utsumi Low energy electron beam lithography
JP6027150B2 (ja) 2014-06-24 2016-11-16 内海　孝雄 低エネルギー電子ビームリソグラフィ

Also Published As

Publication number Publication date
US3615464A (en) 1971-10-26
US3598604A (en) 1971-08-10
FR2024891B2 (de) 1974-08-09
DE1957788B2 (de) 1971-04-08
NL6917425A (de) 1970-05-21
FR2024892B2 (de) 1974-08-09
US3615463A (en) 1971-10-26
FR2024890B2 (de) 1973-03-16
SE362538B (de) 1973-12-10
US3615466A (en) 1971-10-26
DE1957788A1 (de) 1970-05-27
FR2024890A2 (de) 1970-09-04
FR2024109A1 (de) 1970-08-28
FR2024892A2 (de) 1970-09-04
FR2024891A2 (de) 1970-09-04
GB1281933A (en) 1972-07-19

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Legal Events

Date Code Title Description
PL Patent ceased