US3698072A - Validation technique for integrated circuit manufacture - Google Patents

Validation technique for integrated circuit manufacture Download PDF

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Publication number
US3698072A
US3698072A US3698072DA US3698072A US 3698072 A US3698072 A US 3698072A US 3698072D A US3698072D A US 3698072DA US 3698072 A US3698072 A US 3698072A
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Prior art keywords
integrated circuit
formats
information
format
making
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Jeffrey G Koens
Robert D Merillat
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International Business Machines Corp
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International Business Machines Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49004Electrical device making including measuring or testing of device or component part
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing

Abstract

A method of making an integrated circuit involves first placing the digital information characterizing the circuit into two separate and different formats. The latter are then transmitted to the manufacturing plant where they are compared. The two formats are then used to form respective artworks depicting a mask for making the integrated circuit. The artworks are then compared. The integrated circuit is then built from the information of one of said formats and is compared with the information in the other format.

Description

United States Patent Koens et al.

[ VALIDATION TECHNIQUE FOR 8/1971 De Puy ..29/576 INTEGRATED CIRCUIT MANUFACTURE Primary Examiner-J. Spencer Overholser Assistant Examiner-Norman E. Lehrer [72] Inventors: Jeffrey G. Koens, Wappmgers Falls;

Robert D. Meriuat Hopewell Junc Attorney-Hamfin and Jancm and Martin G. Reiffin tron, both of NY. ABSTRACT [73] Asslgnee: 22::2323' f sx i i YMachmeS A method of making an integrated circuit involves p0 first placing the digital information characterizing the [22] Filed: Nov. 23, 1970 circuit into two separate and different formats. The latter are then transmitted to the manufacturing plant [2H Appl' 91372 where they are compared. The two formats are then used to form respective artworks depicting a mask for [52] US. Cl. ..29/574, 29/593, 29/625 making the integrated circuit. The artworks are then [51] Int. Cl. ..H0ll 19/00 compared. The integrated circuit is then built from the [58] Field of Search ..29/625, 624, 626, 574,593 information of one of said formats and is compared with the information in the other format. [56] References Cited 11 Claims, 1 Drawing Flgure UNITED STATES PATENTS A 3,46l,547 8/1969 Di Curcio ..29/574 FORMAT FORMAT 1 2 EBCDIC REPRESENTATION EBCDIC REPRESENTATION L @BK 9 W"M i" L MANUFACTURER AUTOMATIC TEST SYSTEM PLT TBM 1627 POST m5 POST i. PR ODUCT I PROCESSOR PROCESSOR 14 L EXTENDED PLOTTER ,6 IBM 1627 c005 PLOTTER INPUT PROGRAMMABLE LIGHT #7 TABLE 11\ BM 1627 PLOTTER CONTINUE 'aooxss BLOW-UP PRODUCT MANUFACTURE -PATENTEDBBT 11 I972 BLOW-UP PRODUCT MANUFACTURE FORMAT FORMAT 1 2 EBCDIC REPRESENTATION EBCDIC REPRESENTATION 0F BINARY CODE OF HEXADECIMAL CODE CUSTOMER L/// \\\J 4 MANUFACTURER COMPARE A ORDER TO RETRANsMn' 3 V l AuToMAnc TEST COMPARE SYSTEM 7 PLT WE PRODUCT POST --5 POST PROCESSOR PROCESSOR M EXTENDED PLOTTER ,,s IBM 1627 CODE m PLOTTER y T INPUT PROGRAMMABLE UGHT TABLE H-\JBMl627 PLOTTER CONHNUE Bww 00x55 TWEMOM JEFFREY G KOENS ROBERT D. MERILLAT Al IOHNLY VALIDATION TECHNIQUE FOR INTEGRATED CIRCUIT MANUFACTURE FIELD OF THE INVENTION In the present state of the art of manufacturing integrated circuits it is common practicefor the customer to transmit to the manufacturing plant the data characterizing the circuit to be built by the manufacturer for the customer. Even a single error in the data utilized by the manufacturer will result in a defective product and the loss of time and money. Therefore it is extremely important to assure that the final integrated circuit product conforms to the original data, and in particular to determine that no errors occurred during the transmission of the data to the manufacturer or during the mask-making process.

DESCRIPTION OF THE PRIOR ART In the prior art an attempt was made to eliminate errors by presenting the data in two different formats: a chip schematic and a digitized layout. These formats were converted to the same language and then compared. See A Computer-Aided Method for Checking and Making Monolithic Integrated Circuit Masks by D. M. Sheppard, W. T. James, M. E. Harris, and A. M. Barone presented at the Western Electronic Show and Convention, Aug. 23-26, 1966. However there was no assurance that either of the two formats was in accordance with the original design data characterizing the integrated circuit chip. Furthermore, data transmission from one location to another was not involved.

SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a method of making an integrated circuit which is virtually foolproof and which will assure that the final product conforms to the original chip design.

Another object is to provide a plurality of checks and comparisons during the circuit manufacturing process so as to detect any errors before manufacture of a defective product.

These objects are achieved by a novel'arrangement for repeatedly checking the received data, the masks and the final product against the data originally transmitted from the customer to the manufacturer.

Other objects and advantages of the present invention are either inherent in the structure and method disclosed herein or will become apparent to those skilled in the art as the detailed description proceeds in connection with the accompanying drawing. DESCRIP- TION OF THE DRAWING The drawing shows a flow diagram depicting the successive steps of the method in accordance with the subject invention.

DESCRIPTION OF THEPREF ERRED EMBODIMENT The method of making an integrated circuit in accordance with the present invention commences when the customer sends to the manufacturer an order for a so-called part number, that is, a particular circuit design. The integrated circuit isspecified by a truth table designating a bit pattern which defines the functional logic of the required circuit as an array of, say, 512 1 and bits.

The manufacturer maintains a stock pile of integrated circuit wafers which have all circuits active, corresponding to an array where all the transistors are connected and designating in each instance the 1 bits. When the bit pattern array is received from the customer, a mask is made with a tab, that is, a 2 x 4 mil. rectangle, appearing on the mask wherever a 0" bit appears in the bit pattern array. This mask is superimposed on a photoresist layer on the master-slice wafer, the photoresist is exposed to light through the mask, the unexposed portions of the photoresist are removed, and the circuit portions under the tabs are etched away, leaving a circuit corresponding to the users functional requirement.

Since the customers order consists of a simple bit pattern, it is vulnerable to accidental error such as the loss or interposition of one or more bits. In order to obviate this possibility, each order is transmitted from the customer to the manufacturer in two separate and distinct formats. For example, the first format may consist of a binary bit pattern encoded in EBCDIC (Extended Binary Coded Decimal Interchange Code). A pattern such as 1011001111000 110... would then be expressed as FlFOFlFlFOFOFlFlFlFlFOFOFOFlFl F0.... The second format may consist of the hexadecimal representation of the bit pattern encoded in EBCDIC. For example, the hexadecimal representation of the above pattern would be B3C6... EBCDIC it would be C2F3C3F6...

Both formats contain the same information but in different and distinct forms which act as a check against accidental error. For instance, to interpose the second and third bits of the proceeding pattern without detection, the first format would have to read F 1F 1 F0 F 1.... and the second format would have to become C4F3.... Such an alteration is almost impossible over lines that are safe-guarded by parity and check-sum protection.

Referring to the drawing, the two formats comprising the customer's order at 1 and 2 are received by the manufacturer and are immediately compared at 3 to be certain the information content of each is identical. The comparison consists of decoding each pattern to a bit string an comparing corresponding 'bits oneat a time. If the comparison fails to indicate identity at any and encoded in point, the order is rejected at 4 and the customer is required to retransmit the order. If the two valid formats are accepted by the manufacturer, one format is used to build a product and the other format is used as a constant reference to assure integrity of all subsequent manufacturing hardware and software operations.

The data in the first format is processed at 5 with a program called a programmable light table postprocessor to generate a program card deck designated an extended plotter code at 6. The latter specifies a series of signals for driving a programmable light table designated at 7. The light table 7 generates onto a photographic plate the array of tabs corresponding to the mask which is tobe used to manufacture the integrated circuit. The image is ten times life size and the mask is made from the plate by a standard photographic reduction step-and-repeat technique. The plate exposed by the programmable light table is then magnified to a hundred times life size at 8.

The second format has been processed by a program referred to at 9 as the IBM 1627 post-processor which converts the second format into plotter input signals to drive an IBM 1627 plotter indicated at 11. The latter then generates a 100 times life size enlargement of the array of tabs designated by the second format. This enlargement is on translucent mylar and is indicated at 12. The two artworks generated at 8 and 12 are then compared at 13 by superimposing the mylar artwork over the other artwork to see that the tabs correspond in each case. If no discrepancy is indicated, the integrated circuit is manufactured from the plate generated by the programmable light table at 7 to provide a product at 14. This product is then checked by an automated test system indicated at 15 by comparing at 16 the product with the second format originally specified. The identity between the specified design and the finished product is thus assured.

It is to be understood that the specific embodiment disclosed herein is merely illustrative of one of the many forms which the invention may take in practice without departing from the scope of the invention delineated in the appended claims, and that the claims are to be construed as broadly as permitted by the prior art.

We claim:

1. A method of processing information for making an integrated circuit comprising the steps of transmitting from a customers location to a manufacturing plant two separate and different formats of digital information each defining the integrated circuit to be made,

comparing said two formats at the manufacturers location, forming from a first of said formats a first enlarged artwork depicting a mask for making said integrated circuit,

forming from the second of said formats a second enlarged artwork depicting said mask for making said integrated circuit, and

comparing said artworks to determine whether they correspond.

2. A method as recited in claim 1 and comprising the steps of building an integrated circuit in accordance with the information of said first format, and

comparing said built integrated circuit with the information of said second format.

3. A method of processing information for making an integrated circuit comprising the steps of transmitting from one location to another location two separate and different formats of digital information each defining the integrated circuit to be made,

comparing said two formats,

forming from a first of said formats a first artwork depicting a mask for making said integrated circuit, forming from the second of said formats a second artwork depicting said mask for making said inte grated circuit, and comparing said artworks to determine whether they correspond.

4. A method as recited in claim 3 and comprising the steps of building an integrated circuit in accordance with the information of said first format, and

comparing said built integrated circuit with the information of said second format. 5. A method of processing information for making an integrated circuit comprising the steps of transmitting from a customers location to a manufacturing plant two separate and different formats of digital information each defining the integrated circuit to be made, forming from a first of said formats a first enlarged artwork, forming from the second of said formats a second enlarged artwork, and comparing said artworks to determine whether they correspond. 6. A method as recited in claim 5 and comprising the steps of building an integrated circuit in accordance with the information of said first format, and comparing said built integrated circuit with the information of said second format. 7. A method of making an integrated circuit comprising the steps of transmitting from one location to another location two separate and different formats of digital infor mation each defining the integrated circuit to be made, forming from a first of said formats a first artwork, forming from the second of said formats a second artwork, comparing said artworks to determine whether they correspond, building an integrated circuit in accordance with the information of said first format, and comparing said built integrated circuit with the information of said second format. 8. A method of processing information for making an integrated circuit comprising the steps of transmitting from a customers location to a manufacturing plant two separate and different formats of digital information each defining the integrated circuit to be made, forming from a first of said formats a first enlarged artwork depicting a mask for making said integrated circuit, forming from the second of said formats a second enlarged artwork depicting said mask for making said integrated circuit, and comparing said artworks to determine whether they correspond. 9. A method as recited in claim 8 and comprising the steps of building an integrated circuit in accordance with the information of said first format, and comparing said built integrated circuit with the information of said second format. 10. A method of processing information for making an integrated circuit comprising the steps of transmitting from one location to another location two separate and different formats of digital information each defining the integrated circuit to be made,

forming from a first of said formats a first enlarged artwork depicting a mask for making said in tegrated circuit, forming from the second of said formats a second enlarged artwork, and

comparing said artworks to determine whether they correspond.

11. A method as recited in claim and comprising the steps of building an integrated circuit in accordance with the 5 information of said first format, and comparing said built integrated circuit with the information of said second format.

Claims (11)

1. A method of processing information for making an integrated circuit comprising the steps of transmitting from a customer''s location to a manufacturing plant two separate and different formats of digital information each defining the integrated circuit to be made, comparing said two formats at the manufacturer''s location, forming from a first of said formats a first enlarged artwork depicting a mask for making said integrated circuit, forming from the second of said formats a second enlarged artwork depicting said mask for making said integrated circuit, and comparing said artworks to determine whether they correspond.
2. A method as recited in claim 1 and comprising the steps of building an integrated circuit in accordance with the information of said first format, and comparing said built integrated circuit with the information of said second format.
3. A method of processing information for making an integrated circuit comprising the steps of transmitting from one location to another location two separate and different formats of digital information each defining the integrated circuit to be made, comparing said two formats, forming from a first of said formats a first artwork depicting a mask for making said integrated circuit, forming from the second of said formats a second artwork depicting said mask for making said integrated circuit, and comparing said artworks to determine whether they correspond.
4. A method as recited in claim 3 and comprising the steps of building an integrated circuit in accordance with the information of said first format, and comparing said built integrated circuit with the information of said second format.
5. A method of processing information for making an integrated circuit comprising the steps of transmitting from a customer''s location to a manufacturing plant two separate and different formats of digital information each defining the integrated circuit to be made, forming from a first of said formats a first enlarged artwork, forming from the second of said formats a second enlarged artwork, and comparing said artworks to determine whether they correspond.
6. A method as recited in claim 5 and comprising the steps of building an integrated circuit in accordance with the information of said first format, and comparing said built integrated circuit with the information of said second format.
7. A method of making an integrated circuit comprising the steps of transmitting from one location to another location two separate and different formats of digital information each defining the integrated circuit to be made, forming from a first of said formats a first artwork, forming from the second of said formats a second artwork, comparing said artworks to determine whether they correspond, building an integrated circuit in accordance with the information of said first format, and comparing said built integrated circuit with the information of said second format.
8. A meThod of processing information for making an integrated circuit comprising the steps of transmitting from a customer''s location to a manufacturing plant two separate and different formats of digital information each defining the integrated circuit to be made, forming from a first of said formats a first enlarged artwork depicting a mask for making said integrated circuit, forming from the second of said formats a second enlarged artwork depicting said mask for making said integrated circuit, and comparing said artworks to determine whether they correspond.
9. A method as recited in claim 8 and comprising the steps of building an integrated circuit in accordance with the information of said first format, and comparing said built integrated circuit with the information of said second format.
10. A method of processing information for making an integrated circuit comprising the steps of transmitting from one location to another location two separate and different formats of digital information each defining the integrated circuit to be made, forming from a first of said formats a first enlarged artwork depicting a mask for making said integrated circuit, forming from the second of said formats a second enlarged artwork, and comparing said artworks to determine whether they correspond.
11. A method as recited in claim 10 and comprising the steps of building an integrated circuit in accordance with the information of said first format, and comparing said built integrated circuit with the information of said second format.
US3698072A 1970-11-23 1970-11-23 Validation technique for integrated circuit manufacture Expired - Lifetime US3698072A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5465217A (en) * 1993-08-16 1995-11-07 Motorola, Inc. Method for automatic tab artwork building
US20040025137A1 (en) * 2002-07-30 2004-02-05 Croke Charles E. Rule based system and method for automatically generating photomask orders in a specified order format
US20040214097A1 (en) * 2002-03-14 2004-10-28 Suttile Edward J. Automated manufacturing system and method for processing photomasks
US20050055659A1 (en) * 2002-07-30 2005-03-10 Croke Charles E. Rule based system and method for automatically generating photomask orders by conditioning information from a customer's computer system
US20050144088A1 (en) * 2002-07-30 2005-06-30 Croke Charles E. User-friendly rule-based system and method for automatically generating photomask orders
US20060122724A1 (en) * 2004-12-07 2006-06-08 Photoronics, Inc. 15 Secor Road P.O. Box 5226 Brookfield, Connecticut 06804 System and method for automatically generating a tooling specification using a logical operations utility that can be used to generate a photomask order

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3461547A (en) * 1965-07-13 1969-08-19 United Aircraft Corp Process for making and testing semiconductive devices
US3598604A (en) * 1968-11-19 1971-08-10 Ibm Process of producing an array of integrated circuits on semiconductor substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3461547A (en) * 1965-07-13 1969-08-19 United Aircraft Corp Process for making and testing semiconductive devices
US3598604A (en) * 1968-11-19 1971-08-10 Ibm Process of producing an array of integrated circuits on semiconductor substrate

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5465217A (en) * 1993-08-16 1995-11-07 Motorola, Inc. Method for automatic tab artwork building
US7480539B2 (en) 2002-03-14 2009-01-20 Photronics, Inc. Automated manufacturing system and method for processing photomasks
US20040214097A1 (en) * 2002-03-14 2004-10-28 Suttile Edward J. Automated manufacturing system and method for processing photomasks
US6996450B2 (en) 2002-03-14 2006-02-07 Photronics, Inc. Automated manufacturing system and method for processing photomasks
US20050246049A1 (en) * 2002-03-14 2005-11-03 Suttile Edward J Automated manufacturing system and method for processing photomasks
US20050144088A1 (en) * 2002-07-30 2005-06-30 Croke Charles E. User-friendly rule-based system and method for automatically generating photomask orders
US20050060680A1 (en) * 2002-07-30 2005-03-17 Photronics, Inc. Rule based system and method for automatically generating photomask orders in a specified order format
US20050055659A1 (en) * 2002-07-30 2005-03-10 Croke Charles E. Rule based system and method for automatically generating photomask orders by conditioning information from a customer's computer system
US6842881B2 (en) * 2002-07-30 2005-01-11 Photronics, Inc. Rule based system and method for automatically generating photomask orders in a specified order format
US7640529B2 (en) 2002-07-30 2009-12-29 Photronics, Inc. User-friendly rule-based system and method for automatically generating photomask orders
US20040025137A1 (en) * 2002-07-30 2004-02-05 Croke Charles E. Rule based system and method for automatically generating photomask orders in a specified order format
US7669167B2 (en) 2002-07-30 2010-02-23 Photronics, Inc. Rule based system and method for automatically generating photomask orders by conditioning information from a customer's computer system
US20060122724A1 (en) * 2004-12-07 2006-06-08 Photoronics, Inc. 15 Secor Road P.O. Box 5226 Brookfield, Connecticut 06804 System and method for automatically generating a tooling specification using a logical operations utility that can be used to generate a photomask order

Also Published As

Publication number Publication date Type
DE2155803A1 (en) 1972-05-25 application
GB1302630A (en) 1973-01-10 application
DE2155803C3 (en) 1980-07-17 grant
FR2115167B1 (en) 1976-06-04 grant
FR2115167A1 (en) 1972-07-07 application
JPS5135352B1 (en) 1976-10-01 grant
DE2155803B2 (en) 1979-09-27 application

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