JPS6327847B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a mask alignment method in a photolithography process for semiconductor ICs and LSIs, in which mask alignment in a specific process can be accurately matched to arbitrary multiple processes before the specific process. With the goal.

In the manufacturing process of semiconductor ICs and LSIs, the photoetching process is a process for creating device patterns, and occupies a very important weight in the entire manufacturing process. Particularly, the mask alignment process in the photo-etching process becomes an important process as the number of photomasks increases, since there are very important factors that lead to device failure, such as pattern alignment misalignment between photomasks and defective pattern dimensions.

Alignment accuracy, pattern dimensions, etc. may depend on the mask alignment exposure equipment, photoresist, etc. used, but it goes without saying that it also depends on the pattern design of the "register marks" and "alignment keys" in the photomask used for mask alignment. That's a good thing.

FIG. 1 shows a conventional example. To simplify the explanation, let's say that six photomasks are required to create a certain IC. It is assumed that the respective mask levels are A, B, C, D, E, and F, and that they are used in the order of A→B→C→D→E→F in the IC manufacturing process. In Figure 1 a, 1, 2, 3, 4, 5
are the parts where B, C, D, E, and F are written, and 6, 7, 8, 9, and 10 are the register marks corresponding to each process. These are arranged in the register mark area 11. This area 1
1 is patterned at an appropriate location on photomask A, and is patterned on the semiconductor substrate in a photoetch process using photomask A (this is referred to as a photoA process). Next, in the photo-B process, in order to align the mask with the A pattern created on the semiconductor substrate in the photo-A process, photomask B is placed at the same position as the designed position of region 11 of photomask A as shown in FIG. alignment area 1 of b
4 is pattern designed. The alignment key 12 is a mask alignment key for the A-pattern register mark 6. When the alignment key 12 is mask-aligned to the center of the register mark 6 in the photo-B process and patterned on the semiconductor substrate, the result is as shown in FIG. 1c. In addition, in Figure 1b, 13 is the part where the letter B is written, and in the photo-B process, the mask should not be aligned with register marks other than register mark 6 (for example, 7, 8) in Figure 1a. The mask is designed so that parts 1 and 13 are unified with the same letter B and patterned.

In FIG. 1c, the region 11 in FIG. 1d and the region 14 in FIG. 1b are overlapped (masked together on the semiconductor substrate) to form a region 15. That is 1
5 shows a mask alignment pattern of photomasks A and B on a semiconductor substrate. In the same manner, in the photo C process, mask alignment is performed using the character C of the part 2 and the register mark 7 as the register mark side, and the alignment key 20 and the character C of the part 16 as the alignment key side. -8-21-17, photo E step and F step are 4-9-22-18, 5-10-23-1 respectively
9 system, and when the final mask alignment step F process is completed, the first alignment area on the semiconductor substrate is
A pattern as shown in Figure d will be formed.

In the example described above, the alignment accuracy of patterns B, C, D, E, and F can only be determined with respect to the pattern of mask A. For example, the alignment accuracy of pattern C with respect to pattern B can be determined with respect to pattern A of pattern B. This cannot be determined unless the alignment accuracy trajectory is taken into consideration. This is because, if the mask alignment deviation of pattern B with respect to pattern A is 1 μm to the left, even if the mask alignment of pattern C is aligned with the center of the register mark for pattern C created with pattern A,
The pattern alignment deviation with respect to the pattern is to the left.
This is because it is 1 μm. Therefore, at present, register marks are designed between mask patterns that require alignment accuracy. For example, in the above example, when creating the B pattern, a register mark for matching the C pattern mask is created, and when creating the C pattern, a register mark for matching the D pattern mask is created. However, as the standard dimensions of patterns become smaller (2 to 3 μm) and high alignment accuracy is required for multiple patterns, this method will no longer be able to cope with the problem.

In order to solve the problems of the above-mentioned conventional example, the present invention
To provide a method by which mask alignment can be easily and precisely performed simultaneously for any plurality of previous steps even when the number of masks increases to four or more.

FIG. 2 shows a mask alignment method according to an embodiment of the present invention.

Now, to simplify the discussion, the mask level for IC manufacturing is 6, and they are A, B, C, D, E, and F.
Name it. Unlike the conventional example, the alignment area of each mask is divided into upper and lower two stages, and each mask alignment process uses two upper and lower stages, and two register marks and two alignment keys. In Figure 2a, 24, 25, 26, 27, 28 are the letters B, C, D, E, F, respectively, and 29,
Reference numerals 30, 31, 32, and 33 are register marks corresponding to 24 to 28, respectively, and are formed in a row in a single column direction, and marks 30 to 33 are mark rows used in C and subsequent mask alignment steps. 35 is the letter b, register mark 36
corresponds to 35. Here, the lower case letter b in 35 was intentionally used to distinguish between the upper and lower tiers (if no distinction is made, there is a high risk of misalignment of the mask).

In this way, the alignment area 34 is
In the process, the semiconductor substrate is patterned.
As an example, the pattern D (that is, the pattern corresponding to the third photomask from the first photomask) requires very high pattern alignment accuracy, and the pattern A, which corresponds to the first photomask, also requires the pattern Suppose that alignment accuracy is strictly required for pattern B corresponding to the first photomask from photomask 1 (usually ±0.5 μm or less).
In addition, pattern C is similar to pattern D, as well as A and B.
Assuming that accuracy is required according to the pattern of
The pattern design of the alignment region 45 of the pattern forming mask B in this case is shown in FIG. 2b. In other words, the alignment keys 37 and 41 are respectively A.
They correspond to the register marks 29 and 36 of the pattern, and the character 38 is B and the character 42 is b. Therefore, mask B is aligned with register marks 29 and 36 patterned on the semiconductor substrate. At the bottom of the alignment area 45 of the mask B, there are register marks 4 for aligning the C pattern and D pattern masks.
3, 44, letters c, d are patterned into 39, 40. The marks 43 and 44 are formed at different positions from C and the row of register marks 29 to 33 used for subsequent mask alignment. Therefore, the register mark for matching the D pattern mask that we are currently focusing on is the letter D in the photo A process with 26 and the register mark 31.
In the photo B process, the letter d was formed at 40 and the register mark was formed at 44 on the semiconductor substrate.

Therefore, the alignment region 54 for mask alignment of the D mask for forming the D pattern is shown, for example, in FIG. 2C. Here, the alignment key 46 and the letter D 47 are the upper register mark 31 and the letter D26.
alignment key 48 and letter d 4
9 is lower register mark 44 and letter d 40
It is for use. These two alignment keys 46, 4
8 in the center of the unused register marks 31 and 44 patterned on the semiconductor substrate, the D pattern is made into the A pattern and the B pattern.
Both patterns significantly improve alignment accuracy. Note that the C pattern can also be aligned with the A pattern with high precision using the register marks 30 and 43. Also, although the mark 44 is formed with mask B, this mark 44 is used with mask D, so if it is necessary to match mask D with pattern A and pattern C, mark 44 can be used with mask B.
Of course, it is sufficient to form the mask C using the mask C. The letters e and f 50 and 51 and register marks 52 and 53 are examples of cases where the E pattern and F pattern are used for highly accurate mask alignment with the A pattern and D pattern, similar to the D pattern. , marks 52, 53 are also formed at different positions from the row of marks 30-33.

As described above, the D, E, and F patterns, for example, are aligned with the A pattern and the register marks formed in each previous process with high precision by forming register marks in each previous process. Furthermore, the register marks used for positioning the D, E, and F patterns are all unused, so the mask alignment process is not complicated, and highly accurate mask alignment is possible using the same method. In this way, the present invention provides three steps from the predetermined step A.
This is particularly effective when matching the subsequent mask matching steps with a plurality of previous steps with high precision.

Note that if alignment accuracy is required for three patterns, three levels of alignment areas may be provided in the same manner.

According to the present invention, for two mask patterns,
It has been confirmed that as long as there is no problem with the pitch deviation of the photomask itself during mask manufacturing, it is possible to fully achieve within ±0.5 μm.

In this way, the present invention is designed to meet the needs of future high-precision, high-density
In LSI production, it can be said that this is extremely important from the viewpoint of pattern matching accuracy and pattern dimensional fidelity.

Furthermore, in the present invention, in step A, D
In order to form a row of register marks used in the process and subsequent steps, and to form another register mark different from the above mark and at a position other than the above column direction during mask alignment in the B or C process, in the mask alignment in the D process. Mask alignment can be performed using the two most adjacent register marks, reducing the possibility of mistakes in mask alignment and further improving accuracy. This also applies to steps E and F.

As described above, the present invention performs mask alignment in a specific mask alignment process from the third onward counting from a predetermined photomask to a photomask in any process from here to immediately before the specific photomask alignment process. It becomes possible to perform both simultaneously and easily with high precision, and exhibits an excellent effect in manufacturing high-density semiconductor integrated circuits.

[Brief explanation of the drawing]

Figures 1 a to d are layout diagrams of register marks and alignment keys used in conventional mask alignment, and Figures 2 a to c are register marks of the present invention.
FIG. 3 is a layout diagram of alignment keys. 1-5, 24-28...Photo process name, 6-1
0,29-33...Register mark, 12,2
0, 21, 22, 23, 41, 48... Alignment key.

Claims (1)

[Claims] 1 With a predetermined photomask, a first register mark and n (n≧3) from the predetermined photomask formed in a row with the first register mark.
A second register mark for alignment of the n-th photomask is formed on the semiconductor substrate, and a second register mark for alignment of the n-th photomask is formed in a process using the m-th (1≦m<n) photomask from the predetermined photomask. A register mark No. 3 is formed on the semiconductor substrate at a position different from the second register mark and in a position other than the column direction, and then an unused second register mark and an unused third register mark are formed on the semiconductor substrate. A mask alignment method characterized in that the n-th photomask is aligned using a register mark as a reference.