JP2002183236A - System for automatically detecting overlapping of copper foil solid pattern - Google Patents

System for automatically detecting overlapping of copper foil solid pattern

Info

Publication number
JP2002183236A
JP2002183236A JP2000379599A JP2000379599A JP2002183236A JP 2002183236 A JP2002183236 A JP 2002183236A JP 2000379599 A JP2000379599 A JP 2000379599A JP 2000379599 A JP2000379599 A JP 2000379599A JP 2002183236 A JP2002183236 A JP 2002183236A
Authority
JP
Japan
Prior art keywords
copper foil
solid pattern
foil solid
overlap
overlapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000379599A
Other languages
Japanese (ja)
Inventor
Hiroki Yokohama
宏紀 横浜
Katsuyuki Kiyono
克幸 清野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Communication Systems Ltd
Original Assignee
NEC Corp
NEC Communication Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Communication Systems Ltd filed Critical NEC Corp
Priority to JP2000379599A priority Critical patent/JP2002183236A/en
Publication of JP2002183236A publication Critical patent/JP2002183236A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a new system for automatically detecting the overlapping of copper foil solid patterns capable of automatically and quickly detecting the violation of overlapping constraint of the copper foil solid patterns in each layout layer of printed circuit board layout design composition of a plurality of layers. SOLUTION: An error file 133 defining the overlapping violation of the copper foil solid patterns is automatically outputted by using a detecting means 103 for detecting the violation of overlapping constraint of the copper foil solid patterns from the layout information 111 of a printed circuit board developed in a main storage device 110 and the information 112 of the overlapping constraint of a copper foil solid pattern.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、銅箔ベタパタン重
なり自動検出方式に関し、特に、プリント基板レイアウ
ト設計において、各レイアウト層における銅箔ベタパタ
ンの重なり制約違反を自動で検出できる銅箔ベタパタン
自動検出方式に関ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic copper foil solid pattern overlapping detection method, and more particularly, to an automatic copper foil solid pattern detecting method capable of automatically detecting an overlap constraint violation of a copper solid pattern in each layout layer in a printed circuit board layout design. Related to

【0002】即ち、本発明は更に詳しくは、図1におい
て、メモリ(主記憶装置)110に展開したプリント基
板のレイアウト情報(プリント基板レイアウトず情報)
111と銅箔ベタパタンの重なり制約の情報(銅箔ベタ
パタン重なり制約情報)112から銅箔ベタパタン重な
り制約違反を検出する検出手段(銅箔ベタパタン重なり
検出手段)103を用いて、銅箔ベタパタン重なり違反
を定義したファイル(銅箔ベタパタン重なりエラーファ
イル)133を自動出力することを可能にする銅箔ベタ
パタン重なり自動検出方式に関する。
More specifically, in the present invention, in FIG. 1, layout information of a printed circuit board developed in a memory (main storage device) 110 (information on a printed circuit board layout).
Using the detecting means (copper foil solid pattern overlap detecting means) 103 for detecting the copper foil solid pattern overlapping constraint violation from the overlapping constraint information (copper foil solid pattern overlapping constraint information) 112 with the copper foil solid pattern overlapping constraint 112, The present invention relates to a copper foil solid pattern overlapping automatic detection method which enables automatic output of a defined file (copper foil solid pattern overlapping error file) 133.

【0003】[0003]

【従来の技術】従来、複数層からなるプリント基板の製
造において、銅箔ベタパタンが同一箇所で重なると銅箔
の厚みの総和が大きくなる。
2. Description of the Related Art Conventionally, in the manufacture of a printed circuit board having a plurality of layers, if copper foil solid patterns overlap at the same position, the total thickness of the copper foil becomes large.

【0004】プリント基板製造のプレス工程において、
厚みの差が大きい場合には、プリント基板の素材がゆが
み層割れが発生する。この層割れを回避するためには、
銅箔ベタパタンの重なり具合を正確に検出する必要があ
る。
[0004] In the press process of manufacturing printed circuit boards,
If the difference in thickness is large, the material of the printed circuit board is distorted and cracks occur in the layer. To avoid this layer cracking,
It is necessary to accurately detect the degree of overlap of copper foil solid patterns.

【0005】また、レイアウトの変更と、重なり検出の
見直し作業を繰り返し行うためには、チェックを迅速に
行う必要がある。
In order to repeatedly change the layout and review the overlap detection, it is necessary to perform a check quickly.

【0006】[0006]

【発明が解決しようとする課題】本発明は従来の上記実
情に鑑みてなされたものであり、従って本発明の目的
は、複数層から成るプリント基板レイアウト設計におい
て、各レイアウト層における銅箔ベタパタンの重なり制
約違反を自動的にしかも迅速に検出することを可能とし
た新規な銅箔ベタパタン重なり自動検出方式を提供する
ことにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a printed circuit board layout design comprising a plurality of layers, the copper foil solid pattern in each layout layer. It is an object of the present invention to provide a novel copper foil solid pattern automatic detection method capable of automatically and quickly detecting an overlap constraint violation.

【0007】[0007]

【課題を解決するための手段】上記目的を達成する為
に、本発明に係る銅箔ベタパタン重なり自動検出方式
は、複数層からなるプリント基板のレイアウト設計にお
いて、主記憶装置に展開されたプリント基板のレイアウ
ト情報と銅箔ベタパタンの重なり制約の情報とに基づい
て前記銅箔ベタパタンの重なり制約違反を検出する銅箔
ベタパタン重なり制約違反検出手段を備えて構成され
る。
In order to achieve the above object, an automatic copper foil solid pattern overlapping detection method according to the present invention is applied to a printed circuit board developed in a main storage device in a layout design of a printed circuit board composed of a plurality of layers. And a copper foil solid pattern overlap constraint violation detecting means for detecting the copper foil solid pattern overlap constraint violation on the basis of the layout information and the copper foil solid pattern overlap constraint information.

【0008】本発明に係る銅箔ベタパタン重なり自動検
出方式はまた、複数層からなるプリント基板のレイアウ
ト設計において、プログラム制御により動作する中央処
理装置と、プリント基板のレイアウト情報を定義したプ
リント基板レイアウト図ファイルと銅箔ベタパタンの重
なり制約値を定義した銅箔ベタパタン重なり制約値ファ
イルと銅箔ベタパタン重なり違反を定義した銅箔ベタパ
タン重なりエラーファイルとを格納する外部記憶装置
と、プリント基板のレイアウト情報と銅箔ベタパタンの
重なり制約の情報と銅箔ベタパタンの重なりが違反して
いる情報である銅箔ベタパタン重なりエラー情報とをプ
ログラム制御により情報処理する主記憶装置と、前記各
情報の入出力処理をする入出力装置と、プリント基板の
レイアウト情報を定義した前記プリント基板レイアウト
図ファイルを入力処理するプリント基板レイアウト図入
力手段と、銅箔ベタパタンの重なり制約値を定義した前
記銅箔ベタパタン重なり制約値ファイルを入力処理する
銅箔ベタパタン重なり制約入力手段と、前記銅箔ベタパ
タン重なり制約値情報から銅箔ベタパタン重なり制約違
反を検出する銅箔ベタパタン重なり検出手段と、該銅箔
ベタパタン重なり検出手段による検出結果を銅箔ベタパ
タン重なり違反を定義した前記銅箔ベタパタン重なりエ
ラーファイルとして出力する銅箔ベタパタン重なり検出
結果出力手段とを備えて構成される。
The automatic copper foil solid pattern overlap detection method according to the present invention also includes a central processing unit that operates under program control and a printed circuit board layout diagram that defines printed circuit board layout information in the layout design of a printed circuit board composed of a plurality of layers. An external storage device that stores a file and a copper foil solid pattern overlap constraint value file defining copper foil solid pattern overlap constraint values and a copper foil solid pattern overlap error file that defines a copper foil solid pattern overlap violation, and printed circuit board layout information and copper A main storage device for performing information processing under the control of the foil solid pattern and information of the copper foil solid pattern overlapping error that is information that the overlap of the copper foil solid pattern is violated, and an input / output processing for input / output processing of each of the information. Output device and printed circuit board layout information A printed circuit board layout diagram input means for inputting the printed circuit board layout diagram file, and a copper foil solid pattern overlap constraint input means for input processing the copper solid pattern overlap constraint value file defining the copper solid pattern overlap constraint value, The copper foil solid pattern overlap detection means for detecting a copper foil solid pattern overlap constraint violation from the copper foil solid pattern overlap constraint value information, and the copper foil solid pattern overlap definition defining the copper foil solid pattern overlap violation as a result of detection by the copper foil solid pattern overlap detection means. And a means for outputting a copper foil solid pattern overlap detection result output as an error file.

【0009】前記銅箔ベタパタンの重なり制約値は任意
に指定可能である。
The overlapping constraint value of the copper foil solid pattern can be arbitrarily specified.

【0010】前記銅箔ベタパタンの重なり制約値は該銅
箔ベタパタンの大きさの制約値である。
The overlapping constraint value of the copper foil solid pattern is a constraint value of the size of the copper foil solid pattern.

【0011】前記銅箔ベタパタンの重なり制約値はま
た、該銅箔ベタパタンの重なり層数の制約値である。
The overlapping constraint value of the copper foil solid pattern is also a constraint value of the number of overlapping layers of the copper foil solid pattern.

【0012】前記銅箔ベタパタン重なり検出手段は、現
在検査対象のレイアウト層の銅箔ベタパタンの辺が重な
り制約長を超えているか否かを判断し、該判断の結果前
記重なり制約長の範囲内であれば、同一レイアウト層の
他の銅箔ベタパタンまたは他のレイアウト層の銅箔ベタ
パタンについて前記判断と同様の判断を実行し、前記判
断の結果前記重なり制約長の範囲外であるであるときに
はエラー信号を出力することを特徴としている。
The copper foil solid pattern overlap detecting means judges whether or not the side of the copper solid pattern of the layout layer to be inspected currently exceeds the overlap constraint length. As a result of the judgment, the copper foil solid pattern overlap within the overlap constraint length is determined. If so, the same determination as the above determination is performed for another copper foil solid pattern of the same layout layer or a copper foil solid pattern of another layout layer, and when the result of the determination is out of the range of the overlap constraint length, an error signal is output. Is output.

【0013】前記銅箔ベタパタン重なり検出手段はま
た、現在検査対象のレイアウト層の銅箔ベタパタンが他
のレイアウト層の銅箔ベタパタンと重なっているか否か
を判断し、該判断の結果両者の銅箔ベタパタンが重なっ
ていなければ更に他のレイアウト層の銅箔ベタパタンに
対して前記判断を繰り返し、前記判断の結果両者の銅箔
ベタパタンが重なっている場合には重なり信号を検出す
ると共に該重なり信号をカウントし、該重なりカウント
数が前記銅箔ベタパタン重なり制約値ファイルの重なり
制約数を超えたときにエラー信号を出力することを特徴
としている。
The copper foil solid pattern overlap detecting means also determines whether or not the copper foil solid pattern of the layout layer to be inspected currently overlaps the copper foil solid pattern of another layout layer. If the solid patterns do not overlap, the above determination is repeated for the copper foil solid patterns of the other layout layers. If both copper foil solid patterns overlap, as a result of the judgment, an overlap signal is detected and the overlap signal is counted. An error signal is output when the overlap count exceeds the overlap constraint number in the copper foil solid pattern overlap constraint value file.

【0014】[0014]

【発明の実施の形態】次に、本発明をその好ましい一実
施の形態について図面を参照しながら詳細に説明する。
Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

【0015】図1は本発明による一実施の形態を示すブ
ロック構成図である。
FIG. 1 is a block diagram showing an embodiment according to the present invention.

【0016】[0016]

【実施の形態の構成】図1を参照するに、本発明に係る
銅箔ベタパタン重なり自動検出方式の一実施の形態は、
プログラム制御により動作するコンピュータ(中央処理
装置)100と、プリント基板のレイアウト情報を定義
したファイル(プリント基板レイアウト図ファイル)1
31と銅箔ベタパタンの重なり制約値を定義したファイ
ル(銅箔ベタパタン重なり制約値ファイル)132と銅
箔ベタパタン重なり違反を定義したファイル(銅箔ベタ
パタン重なりエラーファイル)133とを格納するディ
スク(外部記憶装置)130と、プリント基板のレイア
ウト情報(プリント基板レイアウト図情報)111と銅
箔ベタパタンの重なり制約の情報(銅箔ベタパタン重な
り制約情報)112と銅箔ベタパタンの重なりが違反し
ている情報(銅箔ベタパタン重なりエラー情報)113
とをプログラム制御により情報処理するメモリ(主記憶
装置)110と、それらの情報111、112、113
の入出力処理をする装置(入出力装置)120と、プリ
ント基板のレイアウト情報を定義したファイル(プリン
ト基板レイアウト図ファイル)131を入力処理する入
力手段(プリント基板レイアウト図入力手段)101
と、銅箔ベタパタンの重なり制約値を定義したファイル
(銅箔ベタパタン重なり制約値ファイル)132を入力
処理する入力手段(銅箔ベタパタン重なり制約入力手
段)102と、それらの情報131、132から銅箔ベ
タパタン重なり制約違反を検出する検出手段(銅箔ベタ
パタン重なり検出手段)103と、その銅箔ベタパタン
重なり検出手段103の検出結果を銅箔ベタパタン重な
り違反を定義したファイル(銅箔ベタパタン重なりエラ
ーファイル)133として出力する出力手段(銅箔ベタ
パタン重なり検出結果出力手段)104とから構成され
ている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, one embodiment of an automatic copper foil solid pattern overlapping detection system according to the present invention is as follows.
A computer (central processing unit) 100 operated by program control, and a file (printed circuit board layout diagram file) 1 defining printed circuit board layout information
Disk (external storage) storing a file (copper foil solid pattern overlapping constraint value file) 132 defining an overlapping constraint value 31 and a copper foil solid pattern overlapping file and a file (copper foil solid pattern overlapping error file) 133 defining a copper foil solid pattern overlapping violation Device) 130, printed circuit board layout information (printed circuit board layout diagram information) 111, copper foil solid pattern overlap constraint information (copper foil solid pattern overlap constraint information) 112, and copper foil solid pattern overlap information (copper) Foil solid pattern overlapping error information) 113
(Main storage device) 110 for performing information processing by program control, and their information 111, 112, 113
(Input / output device) 120 for input / output processing of the input and input means (printed circuit board layout drawing input means) 101 for inputting a file (printed board layout drawing file) 131 defining layout information of the printed circuit board
Input means (copper foil solid pattern overlap constraint value input means) 102 for inputting a file (copper foil solid pattern overlap constraint value file) 132 defining copper foil solid pattern overlap constraint values, and copper foil Detecting means (copper foil solid pattern overlapping detecting means) 103 for detecting solid pattern overlapping constraint violation, and a file (copper foil solid pattern overlapping error file) 133 which defines the copper foil solid pattern overlapping violation detection result of the copper foil solid pattern overlapping detecting means 103 Output means (copper foil solid pattern overlap detection result output means) 104.

【0017】[0017]

【実施の形態の動作】次に、図1及び図2のフローチャ
ートを参照して本実施の形態の全体の動作について詳細
に説明する。
Next, the overall operation of this embodiment will be described in detail with reference to the flowcharts of FIGS.

【0018】まず、図2のステップA1において、主記
憶装置(メモリ)110は、外部記憶装置130からD
MAによりプリント基板のレイアウト情報を定義したフ
ァイル(プリント基板レイアウト図ファイル)131を
メモリ(主記憶装置)110に読み込む。
First, in step A1 of FIG. 2, the main storage device (memory) 110
A file (printed circuit board layout diagram file) 131 defining printed circuit board layout information is read into the memory (main storage device) 110 by the MA.

【0019】次に、銅箔ベタパタンの重なり制約値を定
義したファイル(銅箔ベタパタン重なり制約値ファイ
ル)132をメモリ(主記憶装置)110に読み込む
(図2のステップA2)。
Next, a file (copper foil solid pattern overlapping constraint value file) 132 defining copper foil solid pattern overlapping constraint values is read into the memory (main storage device) 110 (step A2 in FIG. 2).

【0020】次に、図2のステップA3でプリント基板
の各レイアウト層数分同様の処理をループする(繰り返
す)。
Next, in step A3 of FIG. 2, the same processing is looped (repeated) for each layout layer of the printed circuit board.

【0021】次に、1つのレイアウト層に存在する銅箔
ベタパタン数分処理をループする(図2のステップA
4)。
Next, the processing is looped for the number of solid copper foil patterns existing in one layout layer (step A in FIG. 2).
4).

【0022】次に、ステップA5において、銅箔ベタパ
タン重なり検出手段103によって、銅箔ベタパタンの
辺が重なり制約長を超えているか否かが判断される。
Next, in step A5, the copper foil solid pattern overlap detecting means 103 determines whether or not the side of the copper foil solid pattern exceeds the overlapping constraint length.

【0023】ステップA5の判断の結果、銅箔ベタパタ
ンの大きさが銅箔ベタパタンの重なり制約値を超えてい
なければ次の銅箔ベタパタンの処理に移る(即ち、ステ
ップA4に戻る)。
As a result of the determination in step A5, if the size of the copper foil solid pattern does not exceed the overlapping constraint value of the copper foil solid pattern, the process proceeds to the next copper foil solid pattern (ie, returns to step A4).

【0024】次に、現在検査対象のレイアウト層以外の
その他のレイアウト層数分処理をループする(図2のス
テップA6)。
Next, the process is looped for the number of layout layers other than the layout layer to be inspected (step A6 in FIG. 2).

【0025】次に、ステップA7において、銅箔ベタパ
タン重なり検出手段103によって、銅箔ベタパタンが
他のレイアウト層の銅箔ベタパタンと重なっているか否
かが判断される。
Next, in step A7, the copper foil solid pattern overlap detecting means 103 determines whether the copper solid pattern overlaps with the copper solid pattern of another layout layer.

【0026】ステップA7の判断の結果、銅箔ベタパタ
ンが他のレイアウト層の銅箔ベタパタンと重なっていな
ければ、次のその他のレイアウト層の処理に移る。
If the result of the determination in step A7 is that the copper foil solid pattern does not overlap the copper foil solid pattern of another layout layer, the process proceeds to the next other layout layer.

【0027】次に、ステップA8において、銅箔ベタパ
タンの重なりカウント数が重なり制約数を超えているか
否かが銅箔ベタパタン重なり検出手段103によって判
断される。
Next, in step A8, the copper foil solid pattern overlap detecting means 103 determines whether or not the overlap count of the copper foil solid pattern exceeds the overlap restriction number.

【0028】ステップA8の判断の結果、銅箔ベタパタ
ンの重なり数が制約値を超えていなければ、次のその他
のレイアウト層の処理に移る。
If the result of determination in step A8 is that the number of overlapping copper foil solid patterns does not exceed the constraint value, the process proceeds to the next other layout layer.

【0029】最後に、ステップA8の判断の結果、銅箔
ベタパタンの重なり数が制約値を超えていれば(Yes
の場合)、銅箔ベタパタン重なり検出結果出力手段10
4により銅箔ベタパタンの重なり制約エラー情報を銅箔
ベタパタン重なり違反を定義したファイル(銅箔ベタパ
タン重なりエラーファイル)133として出力する(図
2のステップA9)。
Finally, as a result of the determination in step A8, if the number of overlapping copper foil solid patterns exceeds the constraint value (Yes)
), Copper foil solid pattern overlap detection result output means 10
4, the overlap constraint error information of the copper foil solid pattern is output as a file (copper foil solid pattern overlap error file) 133 in which a copper foil solid pattern overlap violation is defined (step A9 in FIG. 2).

【0030】次に、本発明による一実施の形態について
具体例を用いて説明する。
Next, an embodiment of the present invention will be described using a specific example.

【0031】図3と図4及び図5に示すように、1番目
のレイアウト層の銅箔ベタパタンB1の大きさが銅箔ベ
タパタンの大きさ制約の25mm以上(図4のC1)で
ある場合には、他のレイアウト層の銅箔ベタパタンの重
なりを順番にチェックする。この例では2番目から5番
目までのレイアウト層の銅箔ベタパタンが全て重なって
いるために、重なり層数は5層である。
As shown in FIGS. 3, 4 and 5, when the size of the copper foil solid pattern B1 of the first layout layer is 25 mm or more (C1 in FIG. 4), which is the size restriction of the copper foil solid pattern. Check the overlapping of the copper foil solid patterns of the other layout layers in order. In this example, since the copper foil solid patterns of the second to fifth layout layers all overlap, the number of overlapping layers is five.

【0032】銅箔ベタパタンの重なり層数制約数が5層
以上(図4のC2)であるために、エラーとして検出し
て銅箔ベタパタン重なりエラーファイル133にエラー
メッセージ(図5のD1)として出力される。
Since the number of overlapping layers of the copper foil solid pattern is five or more (C2 in FIG. 4), it is detected as an error and output as an error message (D1 in FIG. 5) to the copper foil solid pattern overlapping error file 133. Is done.

【0033】銅箔ベタパタンの重なり制約値(図4のC
1とC2)は任意に指定することができる。
The overlapping constraint value of the copper foil solid pattern (C in FIG. 4)
1 and C2) can be arbitrarily specified.

【0034】[0034]

【発明の効果】本発明は、以上の如く構成され、作用す
るものであり、従って本発明によれば、以下に示すよう
な効果が得られる。
The present invention is constructed and operates as described above. Therefore, according to the present invention, the following effects can be obtained.

【0035】第1の効果は、銅箔ベタパタンの重なり制
約違反を正確に検出することができる。
The first effect is that it is possible to accurately detect an overlap constraint violation of a copper foil solid pattern.

【0036】その理由は、銅箔ベタパタンの重なり検出
手段によりプリント基板のレイアウト情報を正確に分析
できることにある。
The reason is that the layout information of the printed circuit board can be accurately analyzed by the overlap detecting means of the copper foil solid pattern.

【0037】第2の効果は、銅箔ベタパタンの重なり制
約値を任意に指定できるので、プリント基板の層数、層
厚等の製造条件に柔軟に対応できることにある。
The second effect is that since the overlapping constraint value of the copper foil solid pattern can be arbitrarily specified, it is possible to flexibly cope with the manufacturing conditions such as the number of layers and the thickness of the printed circuit board.

【0038】その理由は、銅箔ベタパタンの重なり制約
値を(銅箔ベタパタン重なり制約情報入力手段)102
により外部から取り込み可能としたことにある。
The reason is that the overlapping constraint value of the copper foil solid pattern is set to (copper foil solid pattern overlapping constraint information input means) 102.
To allow external capture.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による一実施の形態を示すブロック構成
図である。
FIG. 1 is a block diagram showing an embodiment according to the present invention.

【図2】本発明による一実施の形態の動作を説明する流
れ図(フローチャート)である。
FIG. 2 is a flowchart (flow chart) for explaining the operation of the embodiment according to the present invention;

【図3】本発明による一実施の形態におけるプリント基
板の銅箔ベタパタンの重なりを示す斜視図である。
FIG. 3 is a perspective view showing overlapping copper foil solid patterns on a printed circuit board according to an embodiment of the present invention.

【図4】本発明による一実施の形態の銅箔ベタパタン重
なり制約値ファイルを示す図である。
FIG. 4 is a diagram showing a copper foil solid pattern overlap constraint value file according to an embodiment of the present invention.

【図5】本発明による一実施の形態の銅箔ベタパタン重
なりエラーファイルを示す図である。
FIG. 5 is a diagram showing a copper foil solid pattern overlapping error file according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

100…中央処理装置 101…プリント基板レイアウト図入力手段 102…銅箔ベタパタン重なり制約情報入力手段 103…銅箔ベタパタン重なり検出手段 104…銅箔ベタパタン重なり検出結果出力手段 110…主記憶装置 111…プリント基板レイアウト図情報 112…銅箔ベタパタン重なり制約情報 113…銅箔ベタパタン重なりエラー情報 120…入出力装置 130…外部記憶装置 131…プリント基板レイアウト図ファイル 132…銅箔ベタパタン重なり制約値ファイル 133…銅箔ベタパタン重なりエラーファイル 100 central processing unit 101 printed board layout diagram input means 102 copper foil solid pattern overlap constraint information input means 103 copper foil solid pattern overlap detection means 104 copper light solid pattern overlap detection result output means 110 main storage device 111 printed circuit board Layout diagram information 112 ... Copper foil solid pattern overlapping constraint information 113 ... Copper foil solid pattern overlapping error information 120 ... I / O device 130 ... External storage device 131 ... Printed circuit board layout drawing file 132 ... Copper foil solid pattern overlapping constraint value file 133 ... Copper foil solid pattern Overlap error file

───────────────────────────────────────────────────── フロントページの続き (72)発明者 清野 克幸 東京都港区三田一丁目4番28号日本電気通 信システム株式会社内 Fターム(参考) 5B046 AA08 BA04 JA02  ────────────────────────────────────────────────── ─── Continuing on the front page (72) Katsuyuki Seino Inventor F-term (reference) in NEC Communication Systems Co., Ltd. 4-28 Mita, Minato-ku, Tokyo 5B046 AA08 BA04 JA02

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 複数層からなるプリント基板のレイアウ
ト設計において、主記憶装置に展開されたプリント基板
のレイアウト情報と銅箔ベタパタンの重なり制約の情報
とに基づいて前記銅箔ベタパタンの重なり制約違反を検
出する銅箔ベタパタン重なり制約違反検出手段を具備す
ることを特徴とした銅箔ベタパタン重なり自動検出方
式。
In a layout design of a printed circuit board composed of a plurality of layers, a violation of the overlapping constraint of the copper foil solid pattern is determined based on the layout information of the printed circuit board developed in the main storage device and the information of the overlapping restriction of the copper foil solid pattern. An automatic copper foil solid pattern overlap detection method, comprising a copper foil solid pattern overlap constraint violation detecting means.
【請求項2】 複数層からなるプリント基板のレイアウ
ト設計において、プログラム制御により動作する中央処
理装置と、プリント基板のレイアウト情報を定義したプ
リント基板レイアウト図ファイルと銅箔ベタパタンの重
なり制約値を定義した銅箔ベタパタン重なり制約値ファ
イルと銅箔ベタパタン重なり違反を定義した銅箔ベタパ
タン重なりエラーファイルとを格納する外部記憶装置
と、プリント基板のレイアウト情報と銅箔ベタパタンの
重なり制約の情報と銅箔ベタパタンの重なりが違反して
いる情報である銅箔ベタパタン重なりエラー情報とをプ
ログラム制御により情報処理する主記憶装置と、前記各
情報の入出力処理をする入出力装置と、プリント基板の
レイアウト情報を定義した前記プリント基板レイアウト
図ファイルを入力処理するプリント基板レイアウト図入
力手段と、銅箔ベタパタンの重なり制約値を定義した前
記銅箔ベタパタン重なり制約値ファイルを入力処理する
銅箔ベタパタン重なり制約入力手段と、前記銅箔ベタパ
タン重なり制約値情報から銅箔ベタパタン重なり制約違
反を検出する銅箔ベタパタン重なり検出手段と、該銅箔
ベタパタン重なり検出手段による検出結果を銅箔ベタパ
タン重なり違反を定義した前記銅箔ベタパタン重なりエ
ラーファイルとして出力する銅箔ベタパタン重なり検出
結果出力手段とを具備することを特徴とした銅箔ベタパ
タン重なり自動検出方式。
2. In a layout design of a printed circuit board composed of a plurality of layers, a central processing unit that operates under program control, a printed circuit board layout drawing file defining layout information of the printed circuit board, and an overlapping constraint value of a copper foil solid pattern are defined. An external storage device that stores the copper foil pattern overlap constraint value file and the copper foil pattern overlap error file that defines the copper foil pattern overlap violation, the layout information of the printed circuit board, the information of the copper foil pattern overlap constraint, and the copper foil pattern A main storage device that processes information on the copper foil solid pattern overlapping error information, which is information where the overlap is violated, under program control, an input / output device that performs input / output processing of the information, and layout information of a printed circuit board are defined. Input processing of the PCB layout drawing file A printed circuit board layout diagram input means, a copper foil solid pattern overlap constraint value input means for inputting a copper solid pattern overlap constraint value file defining copper foil solid pattern overlap constraint values, and copper from the copper foil solid pattern overlap constraint value information. Copper foil solid pattern overlap detection means for detecting a violation of the foil solid pattern overlap constraint, and copper foil solid pattern overlap detection for outputting a detection result by the copper foil solid pattern overlap detection means as the copper foil solid pattern overlap error file defining the copper foil solid pattern overlap violation A copper foil solid pattern overlapping automatic detection system comprising a result output means.
【請求項3】 前記銅箔ベタパタンの重なり制約値は任
意に指定可能であることを更に特徴とする請求項1また
は2のいずれか一項に記載の銅箔ベタパタン重なり自動
検出方式。
3. The automatic copper foil solid pattern overlapping detection method according to claim 1, wherein the overlap constraint value of the copper foil solid pattern can be arbitrarily specified.
【請求項4】 前記銅箔ベタパタンの重なり制約値は該
銅箔ベタパタンの大きさの制約値であることを更に特徴
とする請求項3に記載の銅箔ベタパタン重なり自動検出
方式。
4. The automatic copper foil solid pattern overlapping detection method according to claim 3, wherein the overlapping restriction value of the copper foil solid pattern is a restriction value of the size of the copper foil solid pattern.
【請求項5】 前記銅箔ベタパタンの重なり制約値は該
銅箔ベタパタンの重なり層数の制約値であることを更に
特徴とする請求項3に記載の銅箔ベタパタン重なり自動
検出方式。
5. The automatic copper foil solid pattern overlap detection method according to claim 3, wherein the copper foil solid pattern overlap constraint value is a constraint value of the number of overlapping layers of the copper foil solid pattern.
【請求項6】 前記銅箔ベタパタン重なり検出手段は、
現在検査対象のレイアウト層の銅箔ベタパタンの辺が重
なり制約長を超えているか否かを判断し、該判断の結果
前記重なり制約長の範囲内であれば、同一レイアウト層
の他の銅箔ベタパタンまたは他のレイアウト層の銅箔ベ
タパタンについて前記判断と同様の判断を実行し、前記
判断の結果前記重なり制約長の範囲外であるであるとき
にはエラー信号を出力することを更に特徴とする請求項
1または2のいずれか一項に記載の銅箔ベタパタン重な
り自動検出方式。
6. The copper foil solid pattern overlap detecting means,
It is determined whether or not the sides of the copper foil solid pattern of the layout layer currently being inspected exceed the overlap constraint length. If the result of the determination is within the range of the overlap constraint length, another copper foil solid pattern of the same layout layer is determined. 2. The method according to claim 1, further comprising: executing a determination similar to the determination for the copper foil solid pattern of another layout layer, and outputting an error signal when the determination result indicates that the pattern is outside the range of the overlap constraint length. Or the copper foil solid pattern overlap automatic detection system according to any one of the above items 2 and 3.
【請求項7】 前記銅箔ベタパタン重なり検出手段は、
現在検査対象のレイアウト層の銅箔ベタパタンが他のレ
イアウト層の銅箔ベタパタンと重なっているか否かを判
断し、該判断の結果両者の銅箔ベタパタンが重なってい
なければ更に他のレイアウト層の銅箔ベタパタンに対し
て前記判断を繰り返し、前記判断の結果両者の銅箔ベタ
パタンが重なっている場合には重なり信号を検出すると
共に該重なり信号をカウントし、該重なりカウント数が
前記銅箔ベタパタン重なり制約値ファイルの重なり制約
数を超えたときにエラー信号を出力することを更に特徴
とする請求項1または2のいずれか一項に記載の銅箔ベ
タパタン重なり自動検出方式。
7. The copper foil solid pattern overlap detecting means,
It is determined whether or not the copper foil solid pattern of the layout layer currently being inspected overlaps with the copper foil solid pattern of the other layout layer. The above determination is repeated for the foil solid pattern, and when both the copper foil solid patterns overlap, the overlap signal is detected and the overlap signal is counted when the both copper foil solid patterns overlap, and the overlap count is set to the copper foil solid pattern overlap constraint. 3. The automatic copper foil solid pattern overlapping detection method according to claim 1, further comprising outputting an error signal when the number of overlapping constraints of the value file is exceeded.
JP2000379599A 2000-12-14 2000-12-14 System for automatically detecting overlapping of copper foil solid pattern Pending JP2002183236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000379599A JP2002183236A (en) 2000-12-14 2000-12-14 System for automatically detecting overlapping of copper foil solid pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000379599A JP2002183236A (en) 2000-12-14 2000-12-14 System for automatically detecting overlapping of copper foil solid pattern

Publications (1)

Publication Number Publication Date
JP2002183236A true JP2002183236A (en) 2002-06-28

Family

ID=18847930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000379599A Pending JP2002183236A (en) 2000-12-14 2000-12-14 System for automatically detecting overlapping of copper foil solid pattern

Country Status (1)

Country Link
JP (1) JP2002183236A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106604576A (en) * 2016-12-30 2017-04-26 广州兴森快捷电路科技有限公司 Circuit board lamination method and system
CN114113147A (en) * 2021-11-17 2022-03-01 佛山市南海区广工大数控装备协同创新研究院 Multilayer PCB (printed Circuit Board) stacking information extraction and level fool-proof detection method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106604576A (en) * 2016-12-30 2017-04-26 广州兴森快捷电路科技有限公司 Circuit board lamination method and system
CN114113147A (en) * 2021-11-17 2022-03-01 佛山市南海区广工大数控装备协同创新研究院 Multilayer PCB (printed Circuit Board) stacking information extraction and level fool-proof detection method

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