CH402194A - Verfahren zur Herstellung von Halbleitervorrichtungen - Google Patents

Verfahren zur Herstellung von Halbleitervorrichtungen

Info

Publication number
CH402194A
CH402194A CH971962A CH971962A CH402194A CH 402194 A CH402194 A CH 402194A CH 971962 A CH971962 A CH 971962A CH 971962 A CH971962 A CH 971962A CH 402194 A CH402194 A CH 402194A
Authority
CH
Switzerland
Prior art keywords
semiconductor devices
manufacturing semiconductor
manufacturing
devices
semiconductor
Prior art date
Application number
CH971962A
Other languages
English (en)
Inventor
James Rideout Arthur
Keith Worthington Thomas
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH402194A publication Critical patent/CH402194A/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/169—Vacuum deposition, e.g. including molecular beam epitaxy
CH971962A 1961-08-16 1962-08-14 Verfahren zur Herstellung von Halbleitervorrichtungen CH402194A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US131771A US3144366A (en) 1961-08-16 1961-08-16 Method of fabricating a plurality of pn junctions in a semiconductor body

Publications (1)

Publication Number Publication Date
CH402194A true CH402194A (de) 1965-11-15

Family

ID=22450959

Family Applications (1)

Application Number Title Priority Date Filing Date
CH971962A CH402194A (de) 1961-08-16 1962-08-14 Verfahren zur Herstellung von Halbleitervorrichtungen

Country Status (6)

Country Link
US (1) US3144366A (de)
BE (1) BE621451A (de)
CH (1) CH402194A (de)
DE (1) DE1266609B (de)
GB (1) GB992671A (de)
NL (1) NL281568A (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3377215A (en) * 1961-09-29 1968-04-09 Texas Instruments Inc Diode array
GB1052379A (de) * 1963-03-28 1900-01-01
US3291640A (en) * 1963-05-27 1966-12-13 Chemclean Corp Ultrasonic cleaning process
DE1290925B (de) * 1963-06-10 1969-03-20 Philips Nv Verfahren zum Abscheiden von Silicium auf einem Halbleiterkoerper
NL136562C (de) * 1963-10-24
US3352726A (en) * 1964-04-13 1967-11-14 Philco Ford Corp Method of fabricating planar semiconductor devices
US3477886A (en) * 1964-12-07 1969-11-11 Motorola Inc Controlled diffusions in semiconductive materials
US3372071A (en) * 1965-06-30 1968-03-05 Texas Instruments Inc Method of forming a small area junction semiconductor
US3447238A (en) * 1965-08-09 1969-06-03 Raytheon Co Method of making a field effect transistor by diffusion,coating with an oxide and placing a metal layer on the oxide
US3391035A (en) * 1965-08-20 1968-07-02 Westinghouse Electric Corp Method of making p-nu-junction devices by diffusion
US3347720A (en) * 1965-10-21 1967-10-17 Bendix Corp Method of forming a semiconductor by masking and diffusion
US3383251A (en) * 1965-12-10 1968-05-14 Rca Corp Method for forming of semiconductor devices by masking and diffusion
US3468729A (en) * 1966-03-21 1969-09-23 Westinghouse Electric Corp Method of making a semiconductor by oxidizing and simultaneous diffusion of impurities having different rates of diffusivity
GB1130666A (en) * 1966-09-30 1968-10-16 Nippon Electric Co A semiconductor device
US3419746A (en) * 1967-05-25 1968-12-31 Bell Telephone Labor Inc Light sensitive storage device including diode array
US3442012A (en) * 1967-08-03 1969-05-06 Teledyne Inc Method of forming a flip-chip integrated circuit
US3772102A (en) * 1969-10-27 1973-11-13 Gen Electric Method of transferring a desired pattern in silicon to a substrate layer
FR2252638B1 (de) * 1973-11-23 1978-08-04 Commissariat Energie Atomique
DE2415290A1 (de) * 1974-03-29 1975-10-09 Licentia Gmbh Maske zur bearbeitung einer halbleiteranordnung
US6087263A (en) * 1998-01-29 2000-07-11 Micron Technology, Inc. Methods of forming integrated circuitry and integrated circuitry structures

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE880658C (de) * 1950-09-06 1953-05-07 Alois Vogt Dr Verfahren zur Herstellung von Zeichen, wie Skalenstrichen, Faden-kreuzungen u. dgl., mit durch optisch homogene Randbegrenzungen bestimmter Raumform auf Unterlagen aller Art und durch dieses Verfahren hergestelltes Erzeugnis
US2796562A (en) * 1952-06-02 1957-06-18 Rca Corp Semiconductive device and method of fabricating same
DE1047911B (de) * 1955-06-07 1958-12-31 Dr Erwin Daniels Verfahren zur Herstellung temperaturempfindlicher Hochohmwiderstaende geringer Waermetraegheit, insbesondere zur Strahlungsmessung
US2995461A (en) * 1956-04-02 1961-08-08 Libbey Owens Ford Glass Co Protective coatings
DE1097039B (de) * 1958-07-02 1961-01-12 Licentia Gmbh Verfahren zur Herstellung von elektrisch unsymmetrisch leitenden Halbleiteranordnungen
US2961354A (en) * 1958-10-28 1960-11-22 Bell Telephone Labor Inc Surface treatment of semiconductive devices
NL125412C (de) * 1959-04-15

Also Published As

Publication number Publication date
US3144366A (en) 1964-08-11
GB992671A (en) 1965-05-19
DE1266609B (de) 1968-04-18
BE621451A (de)
NL281568A (de)

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