CA2275644A1 - Conversion a/n pipeline - Google Patents

Conversion a/n pipeline Download PDF

Info

Publication number
CA2275644A1
CA2275644A1 CA002275644A CA2275644A CA2275644A1 CA 2275644 A1 CA2275644 A1 CA 2275644A1 CA 002275644 A CA002275644 A CA 002275644A CA 2275644 A CA2275644 A CA 2275644A CA 2275644 A1 CA2275644 A1 CA 2275644A1
Authority
CA
Canada
Prior art keywords
signal
stage
pipeline
output
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002275644A
Other languages
English (en)
Inventor
Svante Signell
Bengt Erik Jonsson
Helge Stenstrom
Nianxiong Tan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2275644A1 publication Critical patent/CA2275644A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0687Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using fault-tolerant coding, e.g. parity check, error correcting codes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/667Recirculation type
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0678Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
    • H03M1/068Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
    • H03M1/0682Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/34Analogue value compared with reference values
    • H03M1/38Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/44Sequential comparisons in series-connected stages with change in value of analogue signal
    • H03M1/442Sequential comparisons in series-connected stages with change in value of analogue signal using switched capacitors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/72Sequential conversion in series-connected stages

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

La conversion A/N pipeline d'un signal analogique d'entrée se fait à l'aide d'un nouvel algorithme selon la présente invention, produisant un signal numérique de sortie à codage Gray. Le convertisseur A/N pipeline comporte plusieurs étages en cascade à travers lesquels se propage le signal d'entrée analogique. Chacun des étages produit l'un des bits de sortie du signal numérique de sortie et traite en outre le signal pipelinisé. En fonction de l'algorithme de codage Gray, le bit de sortie produit dans un étage détermine si le signal pipeline de cet étage est oui ou non inversé. Dans un convertisseur A/N pipeline utilisant l'algorithme de codage Gray selon l'invention, l'accumulation des erreurs de décalage est généralement très faible. De plus, le fait que l'inversion de signal soit commandée numériquement autorise des réalisations de grande précision qui améliorent encore les performances du convertisseur A/N pipeline selon l'invention. Dans une variante, l'algorithme de codage Gray est modifié pour former un deuxième algorithme qui rend possibles des réalisations à faible nombre de dispositifs.
CA002275644A 1996-12-16 1997-12-05 Conversion a/n pipeline Abandoned CA2275644A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9604616A SE9604616L (sv) 1996-12-16 1996-12-16 Analog-digitalomvandling av pipelinetyp
SE9604616-4 1997-05-15
PCT/SE1997/002037 WO1998027655A2 (fr) 1996-12-16 1997-12-05 Conversion a/n pipeline

Publications (1)

Publication Number Publication Date
CA2275644A1 true CA2275644A1 (fr) 1998-06-25

Family

ID=20404989

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002275644A Abandoned CA2275644A1 (fr) 1996-12-16 1997-12-05 Conversion a/n pipeline

Country Status (8)

Country Link
US (1) US6028546A (fr)
AR (1) AR008942A1 (fr)
AU (1) AU5422698A (fr)
CA (1) CA2275644A1 (fr)
CO (1) CO4771135A1 (fr)
SE (1) SE9604616L (fr)
TW (1) TW388147B (fr)
WO (1) WO1998027655A2 (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1127148A (ja) * 1997-07-02 1999-01-29 Tadahiro Omi 半導体集積回路
US6222471B1 (en) * 1998-01-15 2001-04-24 Texas Instruments Incorporated Digital self-calibration scheme for a pipelined A/D converter
DE19847662A1 (de) * 1998-10-15 2000-04-20 Siemens Ag A/D-Wandler
US6124818A (en) * 1998-10-21 2000-09-26 Linear Technology Corporation Pipelined successive approximation analog-to-digital converters
US6532370B1 (en) 1999-09-30 2003-03-11 Skyworks Solutions, Inc. Cellular handset with adjustable analog to digital conversion
US6323791B1 (en) * 1999-10-13 2001-11-27 Analog Devices, Inc. Control systems and methods for reducing residue signal offset in subranging analog-to-digital converters
US6486820B1 (en) 2001-03-19 2002-11-26 Cisco Systems Wireless Networking (Australia) Pty Limited Pipeline analog-to-digital converter with common mode following reference generator
US6577185B1 (en) 2001-03-19 2003-06-10 Cisco Systems Wireless Networking (Australia) Pty. Limited Multi-stage operational amplifier for interstage amplification in a pipeline analog-to-digital converter
US6600440B1 (en) * 2001-08-15 2003-07-29 National Semiconductor Corporation Capacitor mismatch independent gain stage for pipeline analog to digital converters
JP4368223B2 (ja) * 2003-03-26 2009-11-18 三洋電機株式会社 バイアス電圧生成回路および増幅回路
US6914549B2 (en) * 2003-09-12 2005-07-05 Texas Instruments Incorporated Reconfigurable analog-to-digital converter
DE60302468T2 (de) * 2003-09-23 2006-06-08 Alcatel Pipeline Analog-Digital-Wandler
US7356424B2 (en) * 2003-09-26 2008-04-08 Texas Instruments Incorporated Diagnostic compiler for pipeline analog-to-digital converter, method of compiling and test system employing the same
ATE527756T1 (de) * 2003-10-23 2011-10-15 Nxp Bv Doppel-rest-pipeline-ad-umsetzer
US7348906B2 (en) * 2004-09-10 2008-03-25 Analog Devices, Inc. INL curve correction in a pipeline ADC
US7161521B2 (en) * 2004-11-29 2007-01-09 Texas Instruments Incorporated Multi-stage analog to digital converter architecture
US7002506B1 (en) * 2004-12-23 2006-02-21 Texas Instruments Incorporated Providing pipe line ADC with acceptable bit error and power efficiency combination
US7746261B2 (en) * 2007-08-01 2010-06-29 Denso Corporation Variable gain amplifier and D/A converter
JP5243352B2 (ja) * 2009-06-17 2013-07-24 シャープ株式会社 Ad変換装置、固体撮像装置および電子情報機器
US8018370B2 (en) * 2010-02-01 2011-09-13 Linear Technology Corporation Time-multiplexed residue amplifier
US8947142B2 (en) 2012-05-16 2015-02-03 Cypress Semiconductor Corporation Common mode trimming with variable duty cycle
CN109728817B (zh) * 2017-10-27 2022-10-14 瑞昱半导体股份有限公司 流水线式模拟数字转换器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3035258A (en) * 1960-11-14 1962-05-15 Bell Telephone Labor Inc Pulse code modulation encoder
US3187325A (en) * 1962-07-02 1965-06-01 Bell Telephone Labor Inc Analog-to-digital converter
US4599602A (en) * 1983-08-03 1986-07-08 Matsushita Electric Industrial Co., Ltd. Serial-type A/D converter utilizing folding circuit cells
US4691190A (en) * 1986-01-27 1987-09-01 General Datacomm, Inc. Analog-digital converter
US4745394A (en) * 1987-04-03 1988-05-17 Motorola, Inc. Pipelined A/D converter
US4931797A (en) * 1987-11-11 1990-06-05 Matsushita Electric Industrial Co., Ltd. Folding circuit and serial-type A/D converter
JPH04371025A (ja) * 1991-06-19 1992-12-24 Nec Corp A/d変換回路
US5550492A (en) * 1994-12-01 1996-08-27 Analog Devices, Inc. Analog to digital converter using complementary differential emitter pairs

Also Published As

Publication number Publication date
WO1998027655A2 (fr) 1998-06-25
US6028546A (en) 2000-02-22
TW388147B (en) 2000-04-21
AU5422698A (en) 1998-07-15
SE9604616L (sv) 1998-06-17
SE9604616D0 (sv) 1996-12-16
AR008942A1 (es) 2000-02-23
CO4771135A1 (es) 1999-04-30
WO1998027655A3 (fr) 1998-08-06

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Legal Events

Date Code Title Description
FZDE Discontinued