CA2060338A1 - Circuit multiprocesseur - Google Patents

Circuit multiprocesseur

Info

Publication number
CA2060338A1
CA2060338A1 CA2060338A CA2060338A CA2060338A1 CA 2060338 A1 CA2060338 A1 CA 2060338A1 CA 2060338 A CA2060338 A CA 2060338A CA 2060338 A CA2060338 A CA 2060338A CA 2060338 A1 CA2060338 A1 CA 2060338A1
Authority
CA
Canada
Prior art keywords
interruption
cpu
signals
input
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2060338A
Other languages
English (en)
Other versions
CA2060338C (fr
Inventor
Nobumasa Kurihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nobumasa Kurihara
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nobumasa Kurihara, Nec Corporation filed Critical Nobumasa Kurihara
Publication of CA2060338A1 publication Critical patent/CA2060338A1/fr
Application granted granted Critical
Publication of CA2060338C publication Critical patent/CA2060338C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
CA002060338A 1991-01-31 1992-01-30 Circuit multiprocesseur Expired - Fee Related CA2060338C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3032150A JPH04246763A (ja) 1991-01-31 1991-01-31 マルチプロセッサ回路
JP3-32150 1991-01-31

Publications (2)

Publication Number Publication Date
CA2060338A1 true CA2060338A1 (fr) 1992-08-01
CA2060338C CA2060338C (fr) 1998-02-10

Family

ID=12350884

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002060338A Expired - Fee Related CA2060338C (fr) 1991-01-31 1992-01-30 Circuit multiprocesseur

Country Status (5)

Country Link
US (1) US5423049A (fr)
EP (1) EP0497628B1 (fr)
JP (1) JPH04246763A (fr)
AU (1) AU644937B2 (fr)
CA (1) CA2060338C (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5717932A (en) * 1994-11-04 1998-02-10 Texas Instruments Incorporated Data transfer interrupt pacing
US5754866A (en) * 1995-05-08 1998-05-19 Nvidia Corporation Delayed interrupts with a FIFO in an improved input/output architecture
US5708817A (en) * 1995-05-31 1998-01-13 Apple Computer, Inc. Programmable delay of an interrupt
US6189065B1 (en) * 1998-09-28 2001-02-13 International Business Machines Corporation Method and apparatus for interrupt load balancing for powerPC processors
US6701429B1 (en) 1998-12-03 2004-03-02 Telefonaktiebolaget Lm Ericsson(Publ) System and method of start-up in efficient way for multi-processor systems based on returned identification information read from pre-determined memory location
DE50114481D1 (de) * 2000-09-22 2008-12-24 Infineon Technologies Ag Vorrichtung zur Auswahl und Weiterleitung von empfangenen Unterbrechungsanfragen gemäss konfigurierbarer Konditionen
KR100656296B1 (ko) 2001-09-12 2006-12-11 마쯔시다덴기산교 가부시키가이샤 화상 부호화 방법 및 화상 복호화 방법
US6813665B2 (en) * 2001-09-21 2004-11-02 Intel Corporation Interrupt method, system and medium
US20060112208A1 (en) * 2004-11-22 2006-05-25 International Business Machines Corporation Interrupt thresholding for SMT and multi processor systems
DE102005045785A1 (de) * 2005-09-23 2007-04-05 Siemens Ag Microcontroller und Verfahren zum Betrieb
TW200810523A (en) * 2005-12-23 2008-02-16 Nxp Bv An AV renderer peripheral with dual interrupt lines for staggered interrupts
JP4675293B2 (ja) * 2006-07-19 2011-04-20 パナソニック株式会社 割り込み制御回路
KR100771125B1 (ko) 2006-11-24 2007-10-29 서울통신기술 주식회사 Ｃｐｕ 보안을 위한 이더넷 트래픽 수신율 제한 시스템 및그 방법
ATE521037T1 (de) 2007-02-08 2011-09-15 Freescale Semiconductor Inc Anforderungssteuerung, verarbeitungseinheit, verfahren zur steuerung von anforderungen und computerprogrammprodukt
WO2008099238A1 (fr) 2007-02-16 2008-08-21 Freescale Semiconductor, Inc. Contrôleur de requête, unité de traitement, agencement, procédé de commande de requêtes et produit de programme d'ordinateur
US9370081B2 (en) * 2010-11-29 2016-06-14 Antonio Pantolios Josefides System and method for a delayed light switch network

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3665404A (en) * 1970-04-09 1972-05-23 Burroughs Corp Multi-processor processing system having interprocessor interrupt apparatus
US4099255A (en) * 1976-12-10 1978-07-04 Honeywell Information Systems Inc. Interrupt apparatus for enabling interrupt service in response to time out conditions
US4080649A (en) * 1976-12-16 1978-03-21 Honeywell Information Systems Inc. Balancing the utilization of I/O system processors
JPS56111951A (en) * 1980-02-07 1981-09-04 Matsushita Electric Ind Co Ltd Generator circuit of interruption signal
JPS62226249A (ja) * 1986-03-27 1987-10-05 Nec Corp 入出力装置切り離し方式
JPS62243058A (ja) * 1986-04-15 1987-10-23 Fanuc Ltd マルチプロセツサシステムの割込制御方法
US4816990A (en) * 1986-11-05 1989-03-28 Stratus Computer, Inc. Method and apparatus for fault-tolerant computer system having expandable processor section
JPS6448160A (en) * 1987-08-19 1989-02-22 Fujitsu Ltd Serial interface control system
US4935894A (en) * 1987-08-31 1990-06-19 Motorola, Inc. Multi-processor, multi-bus system with bus interface comprising FIFO register stocks for receiving and transmitting data and control information
GB8815042D0 (en) * 1988-06-24 1988-08-03 Int Computers Ltd Data processing apparatus
US5031089A (en) * 1988-12-30 1991-07-09 United States Of America As Represented By The Administrator, National Aeronautics And Space Administration Dynamic resource allocation scheme for distributed heterogeneous computer systems
US5179707A (en) * 1990-06-01 1993-01-12 At&T Bell Laboratories Interrupt processing allocation in a multiprocessor system
US5125093A (en) * 1990-08-14 1992-06-23 Nexgen Microsystems Interrupt control for multiprocessor computer system

Also Published As

Publication number Publication date
JPH04246763A (ja) 1992-09-02
CA2060338C (fr) 1998-02-10
AU644937B2 (en) 1993-12-23
EP0497628B1 (fr) 1997-08-06
US5423049A (en) 1995-06-06
EP0497628A3 (en) 1993-05-05
AU1063692A (en) 1992-08-06
EP0497628A2 (fr) 1992-08-05

Similar Documents

Publication Publication Date Title
CA2060338A1 (fr) Circuit multiprocesseur
EP0382469A3 (fr) Arbitrage d'accès de bus dans des ordinateurs numériques
EP0378070A3 (fr) Méthode et appareil pour limiter l'utilisation d'un bus asynchrone avec commande d'accès distribuée
EP0678843A3 (fr) Système de veille à faible consommation pour un moniteur.
DE3464452D1 (en) Circuit arrangement for telecommunication installations, especially for telephone exchanges comprising information processors and devices for overload control
EP0777359B1 (fr) Circuits répéteurs expansibles
AU4735989A (en) Method for unblocking a multibus multiprocessor system
JPS55154653A (en) Interruption distributing system to multiprocessor
US6260100B1 (en) System and method for arbitrating interrupts on a daisy-chained architected bus
JPS5450247A (en) Interrupt control system
JPS5461846A (en) Data input processing system
JPS6459558A (en) Data processing system
JPS56152030A (en) Bus controlling system
KR0158940B1 (ko) 백플레인보드를 이용한 다중 이더넷 버스 중재 처리 시스템
SU1525903A1 (ru) Управл емый распределитель
JPS5734234A (en) Extension of data bus
JPS5638643A (en) Interruption priority processing system
JPS6448160A (en) Serial interface control system
JPS57196335A (en) Shared storage device
JPS5536830A (en) Multiprocessor control system of copier
JPS54114935A (en) Bus scramble circuit
JPS56166531A (en) Control system of priority for obtaining bus
JPS5739474A (en) Vector operation system
JPS644852A (en) Dma device
JPS57111763A (en) Device connecting system of multi-system

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed