CA2003571A1 - Systeme de controle des communications entre unites centrales - Google Patents

Systeme de controle des communications entre unites centrales

Info

Publication number
CA2003571A1
CA2003571A1 CA2003571A CA2003571A CA2003571A1 CA 2003571 A1 CA2003571 A1 CA 2003571A1 CA 2003571 A CA2003571 A CA 2003571A CA 2003571 A CA2003571 A CA 2003571A CA 2003571 A1 CA2003571 A1 CA 2003571A1
Authority
CA
Canada
Prior art keywords
local
command
priority
data
cpus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2003571A
Other languages
English (en)
Other versions
CA2003571C (fr
Inventor
Miyuki Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CA2003571A1 publication Critical patent/CA2003571A1/fr
Application granted granted Critical
Publication of CA2003571C publication Critical patent/CA2003571C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
CA002003571A 1988-11-22 1989-11-22 Systeme de controle des communications entre unites centrales Expired - Fee Related CA2003571C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63-293694 1988-11-22
JP63293694A JPH02140860A (ja) 1988-11-22 1988-11-22 中央処理装置間通信命令制御方式

Publications (2)

Publication Number Publication Date
CA2003571A1 true CA2003571A1 (fr) 1990-05-22
CA2003571C CA2003571C (fr) 1995-08-29

Family

ID=17798027

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002003571A Expired - Fee Related CA2003571C (fr) 1988-11-22 1989-11-22 Systeme de controle des communications entre unites centrales

Country Status (6)

Country Link
US (1) US5170473A (fr)
EP (1) EP0370780B1 (fr)
JP (1) JPH02140860A (fr)
AU (1) AU619916B2 (fr)
CA (1) CA2003571C (fr)
DE (1) DE68926382T2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432920A (en) * 1990-04-13 1995-07-11 Hitachi, Ltd. Store control method with hierarchic priority scheme for computer system
JP2561759B2 (ja) * 1991-03-29 1996-12-11 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセッサシステムおよびそのメッセージ送受信制御装置
US5764928A (en) * 1994-09-30 1998-06-09 Rosemount Inc. Microprocessor communication protocol in a multiprocessor transmitter
US6147991A (en) * 1997-09-05 2000-11-14 Video Network Communications, Inc. Scalable high speed packet switch using packet diversion through dedicated channels
US7228442B2 (en) * 2004-03-30 2007-06-05 The Boeing Company Method and systems for a radiation tolerant bus interface circuit
US8050176B2 (en) * 2004-03-30 2011-11-01 The Boeing Company Methods and systems for a data processing system having radiation tolerant bus
EP1990726B1 (fr) 2006-02-27 2017-05-17 Fujitsu Limited Appareil de contrôle de données, méthode de contrôle de données et programme de contrôle de données
JP4701152B2 (ja) * 2006-10-20 2011-06-15 富士通株式会社 データ中継装置、データ中継方法およびデータ中継プログラム

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD97499A1 (fr) * 1971-11-12 1973-05-14
JPS5833972B2 (ja) * 1979-11-12 1983-07-23 富士通株式会社 計算機システム間通信方式
US4639856A (en) * 1983-11-04 1987-01-27 International Business Machines Corporation Dual stream processor apparatus
US4807109A (en) * 1983-11-25 1989-02-21 Intel Corporation High speed synchronous/asynchronous local bus and data transfer method
JPS60160462A (ja) * 1984-02-01 1985-08-22 Nec Corp プロセツサ間通信装置
JPH0670787B2 (ja) * 1984-06-29 1994-09-07 富士通株式会社 処理装置間指令転送制御システム
US5062076A (en) * 1985-07-12 1991-10-29 Wang Laboratories, Inc. Cascadable, high-bandwidth, multi-channel image transfer controller
JPS63132369A (ja) * 1986-11-21 1988-06-04 Oki Electric Ind Co Ltd メモリ情報転送方式

Also Published As

Publication number Publication date
CA2003571C (fr) 1995-08-29
JPH02140860A (ja) 1990-05-30
DE68926382D1 (de) 1996-06-05
JPH0559464B2 (fr) 1993-08-31
US5170473A (en) 1992-12-08
EP0370780A2 (fr) 1990-05-30
EP0370780A3 (fr) 1991-11-27
AU4546389A (en) 1990-07-19
AU619916B2 (en) 1992-02-06
DE68926382T2 (de) 1996-09-05
EP0370780B1 (fr) 1996-05-01

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Legal Events

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