CA2001682A1 - Transistor en couches minces a fonction de memorisation et methode pour utiliser ce transistor comme element de memoire - Google Patents

Transistor en couches minces a fonction de memorisation et methode pour utiliser ce transistor comme element de memoire

Info

Publication number
CA2001682A1
CA2001682A1 CA2001682A CA2001682A CA2001682A1 CA 2001682 A1 CA2001682 A1 CA 2001682A1 CA 2001682 A CA2001682 A CA 2001682A CA 2001682 A CA2001682 A CA 2001682A CA 2001682 A1 CA2001682 A1 CA 2001682A1
Authority
CA
Canada
Prior art keywords
thin film
film transistor
semiconductor layer
gate
memory element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2001682A
Other languages
English (en)
Other versions
CA2001682C (fr
Inventor
Hiroshi Matsumoto
Hiroyasu Yamada
Nobuyuki Yamamura
Shinichi Shimomaki
Naohiro Konya
Kyuya Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63270893A external-priority patent/JPH0831607B2/ja
Priority claimed from JP63282596A external-priority patent/JPH02130837A/ja
Priority claimed from JP1078390A external-priority patent/JPH02260462A/ja
Priority claimed from JP1087009A external-priority patent/JPH02266570A/ja
Priority claimed from JP1989043098U external-priority patent/JPH02137053U/ja
Priority claimed from JP1989043099U external-priority patent/JPH02137054U/ja
Priority claimed from JP1117580A external-priority patent/JPH02297972A/ja
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of CA2001682A1 publication Critical patent/CA2001682A1/fr
Publication of CA2001682C publication Critical patent/CA2001682C/fr
Application granted granted Critical
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
CA002001682A 1988-10-28 1989-10-27 Transistor en couches minces a fonction de memorisation et methode pour utiliser ce transistor comme element de memoire Expired - Fee Related CA2001682C (fr)

Applications Claiming Priority (14)

Application Number Priority Date Filing Date Title
JP63270893A JPH0831607B2 (ja) 1988-10-28 1988-10-28 メモリ用薄膜トランジスタ
JP63-270893 1988-10-28
JP63282596A JPH02130837A (ja) 1988-11-10 1988-11-10 薄膜トランジスタおよびその製造方法
JP63-282596 1988-11-10
JP1-78390 1989-03-31
JP1078390A JPH02260462A (ja) 1989-03-31 1989-03-31 薄膜メモリ素子
JP1-87009 1989-04-07
JP1087009A JPH02266570A (ja) 1989-04-07 1989-04-07 メモリ用薄膜トランジスタ
JP1989043099U JPH02137054U (fr) 1989-04-14 1989-04-14
JP1989043098U JPH02137053U (fr) 1989-04-14 1989-04-14
JP1117580A JPH02297972A (ja) 1989-05-12 1989-05-12 メモリ用薄膜トランジスタおよびそのゲート絶縁膜の形成方法
JP1-117580 1989-05-12
JP1-43098 1989-11-29
JP1-43099 1989-11-29

Publications (2)

Publication Number Publication Date
CA2001682A1 true CA2001682A1 (fr) 1990-04-28
CA2001682C CA2001682C (fr) 1994-05-03

Family

ID=27564561

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002001682A Expired - Fee Related CA2001682C (fr) 1988-10-28 1989-10-27 Transistor en couches minces a fonction de memorisation et methode pour utiliser ce transistor comme element de memoire

Country Status (4)

Country Link
EP (1) EP0366146B1 (fr)
KR (1) KR930003556B1 (fr)
CA (1) CA2001682C (fr)
DE (1) DE68912071T2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3613594B2 (ja) 1993-08-19 2005-01-26 株式会社ルネサステクノロジ 半導体素子およびこれを用いた半導体記憶装置
JP4538693B2 (ja) * 1998-01-26 2010-09-08 ソニー株式会社 メモリ素子およびその製造方法
EP0986107A1 (fr) * 1998-09-08 2000-03-15 STMicroelectronics S.r.l. Structure de cellules en matrice pour un dispositif de mémoire électriquement effaçable et programmable
KR100730141B1 (ko) * 2005-08-02 2007-06-19 삼성에스디아이 주식회사 박막 트랜지스터 및 이를 구비한 평판표시장치
CN112909087A (zh) * 2021-03-08 2021-06-04 滁州惠科光电科技有限公司 一种显示面板、薄膜晶体管及其制备方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4096509A (en) * 1976-07-22 1978-06-20 The United States Of America As Represented By The Secretary Of The Air Force MNOS memory transistor having a redeposited silicon nitride gate dielectric
US4053917A (en) * 1976-08-16 1977-10-11 The United States Of America As Represented By The Secretary Of The Air Force Drain source protected MNOS transistor and method of manufacture
US4323910A (en) * 1977-11-28 1982-04-06 Rca Corporation MNOS Memory transistor
US4876582A (en) * 1983-05-02 1989-10-24 Ncr Corporation Crystallized silicon-on-insulator nonvolatile memory device
EP0138439B1 (fr) * 1983-09-28 1990-12-19 Kabushiki Kaisha Toshiba Dispositif de mémoire semi-conducteur non volatil, électriquement effaçable et programmable ayant deux électrodes de portes

Also Published As

Publication number Publication date
KR930003556B1 (ko) 1993-05-06
EP0366146A2 (fr) 1990-05-02
EP0366146A3 (en) 1990-11-07
DE68912071D1 (de) 1994-02-17
DE68912071T2 (de) 1994-04-28
CA2001682C (fr) 1994-05-03
EP0366146B1 (fr) 1994-01-05
KR900007075A (ko) 1990-05-09

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Legal Events

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