CA1136291A - Plural polygon source pattern for mosfet - Google Patents
Plural polygon source pattern for mosfetInfo
- Publication number
- CA1136291A CA1136291A CA000389973A CA389973A CA1136291A CA 1136291 A CA1136291 A CA 1136291A CA 000389973 A CA000389973 A CA 000389973A CA 389973 A CA389973 A CA 389973A CA 1136291 A CA1136291 A CA 1136291A
- Authority
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- Canada
- Prior art keywords
- regions
- source
- region
- hexagonal
- polygonal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 230000002441 reversible effect Effects 0.000 claims description 19
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- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- 241000478345 Afer Species 0.000 description 3
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- 239000004020 conductor Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
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- 229910052698 phosphorus Inorganic materials 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
- Amplifiers (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A high power MOSFET has a plurality of closely packed polygonal sources spaced from one another on one surface of a semiconductor body. An elongated gate electrode is exposed in the spacing between the poly-gonal sources and cooperates with two channels, one for each adjacent source electrode J to control con-duction from the source electrode through the channel and then to drain electrode on the opposite surface of the semiconductor body. The conductive region adjacent the channel and between adjacent sources is relatively highly conductive in the section of the channel adjacent to the surface containing the sources. The polygonal shaped source members are preferably hexagonal so that the distances between adjacent sources is relatively constant throughout the device. Each polygonal region has a relatively deep central portion and a shallow outer shelf portion. The shelf portion generally underlies an annular source region. The deep central portion underlies an aluminum conductive electrode and is sufficiently deep that it will not be fully penetrated by aluminum spiking.
A high power MOSFET has a plurality of closely packed polygonal sources spaced from one another on one surface of a semiconductor body. An elongated gate electrode is exposed in the spacing between the poly-gonal sources and cooperates with two channels, one for each adjacent source electrode J to control con-duction from the source electrode through the channel and then to drain electrode on the opposite surface of the semiconductor body. The conductive region adjacent the channel and between adjacent sources is relatively highly conductive in the section of the channel adjacent to the surface containing the sources. The polygonal shaped source members are preferably hexagonal so that the distances between adjacent sources is relatively constant throughout the device. Each polygonal region has a relatively deep central portion and a shallow outer shelf portion. The shelf portion generally underlies an annular source region. The deep central portion underlies an aluminum conductive electrode and is sufficiently deep that it will not be fully penetrated by aluminum spiking.
Description
~3f~;~9~ ~:
BACKGROUND OF THE INVFNTION
~ `
This ;nvention relates to MOS~T devices and _ ;
more specifically rclates to a novel struc~ure for a ~IOS~ET dcvice which permits i* to be used in high power applications with a relatively high reverse voltage and with an exceptionally low on-resistance. T}-e major ad-vantage of the bipolar transistor over the MOSFET
transistor is that t~e bipolar transistor has a very low on-resistance per unit conductive area. The MOSPET
*ransistor has numerous advantages over `the bipolar transistor including very high switching speed, very high gain and lack of the secondary breakdown character-istics e~hibited by a minority carrier devlce. However, because the MOSFET transistor has high on-resistance, its use in higll power s~ri*ching applications has been limited.
BRI~P DESCRIPTION OP ~HE INVENTION
The present inven*ion provides a novel high po~er MOSFET device which has a low forward resistance so that the device b~ecomes more competltive with bipolar devices in a s~itching type application wllile retaining all of the numerous advan*ages of the MOSFET over the bipolar device. In par*icular, with the present invention, the ~or~ard resistance per unit area of the ~-. .
L3~iZ~
device has been reduced by at least a Eactor o two, compared to t~e limiting resistance per unit area previously existing in a MOS~ET-type device.
In one embodiment of the invention, two sources are placed on the same surface of a sernicon- -ductor wafer and are laterally spaced from one ano~her.
A gate electrode, depos~ted on a conventional gate oxide, is disposed be-twecn the sources. Two p-type conduc*ion channels are disposed beneath the gate and are spaced -~rom one anot~er by an n-type bulk region.
Current ~rom each source can flow through its respective-channel (after the creation of the inversion layer defining the channel~, so that majority carrier con-duction can flow through the bulk region and across the wafer or chlp to the drain electrode. The drain electrode may be on the opposite surface of the ~aer or on a laterally displaced surface region ~rom the source electrodes. Th~s configuration is made using the desirable manufacturing techniques of the D-~IOS device~ which permits precise allgr~ent of the various electrodes and channels and permlts use of extremely small channel lengths. Whlle the above con~iguration device may have been previously described ~or a ~IOSFET signal-type device, the structure is not that of the commonly used signal MOSFET.
The device is basically formed in an n(-~ sub-strate which has the relatively h;gh resisti~ity which is .
,~: ,' ' 36;~:91 necessary to obtain the desired reverse ~oltage capability o~ the device. For example, for a 400 volt device, the n~-~ region will have a resistivity of about 20 ohm-centîmeters. However, this same necessary high resistivity characteristIc has caused the on-resistance of -the ~IOSFET devlce, ~rhen used as a po~er switch, to be relatively high, In accordance with t~e present invention, it has been found that in the upper por~ion of the central bulk region ~o which the t~o inversion layers feed current in the path to the drain electrode, the central region immediately beneath the gate oxide can be a relatively low resistivit~ material formed, for example, by an nC+l diffusion in that channel reglon3 ~iithout affecting the reverse voItage characteristics of the device.
More specifically, and in accordance ~rith the invent~on, this co~mon~channel l~ili have an upper portion beneath the gate oxide and a lower bulk portion extending toward the drain electrode. The lo~er portion has the high resistivity desired to produce high reverse voltage ability-, and will have a depth dependent on the ~.
desired reverse voltage for the device. Thus, for a 400 volt devIce, the lower n~-l region may have a depth o about 35 mierons, wllile for a 90 volt device it ~ill have a depth of about ~ microns. Other deptlls ~ill be selected, depending on the desired reverse Yolta~e o:E the device to provide the necessary thicker depletion reglon required to prevent punch-through during reverse voltage conditions. The upper portion of the common channel is made highly conductive (n~) to a depth of from about 3 to about 6 microns. It has been found that this does not interfera with the reverse voltage withstand a~ility of the de~ice. ~owever, it decreases the on-resistance per unit area of the deviice by more than a factor of two.
The result~ng device becomes competitive with conventional high power blpolar switching devices since it retains all of the advantages of khe ~IOSFET deYice over the bipolar device but now has the relatively low fon~ard resistance which was the major characterizing advantage of the bipolar device.
The present in~ention also provides a novel high po~er ~IOSFET device with low forward resistance -where, however, a very high packing density is available and whLch can be made with relatively simple masks. The device further has relatively low capacitanc~.
Each o-f the individual spaced source reg;ons, in accordance with a preferred embodiment o *he invention, IS polygonal in coniguration and is preferably hexagonal to ensure a constank spacing along the major lengths of the sources disposed over the surface of tlle ~ody.
An exkremely large number o small hexagonal source elements may be formed in the sa~e sur-~ace of the semi-conductor body for a given device. By way of example, 6,600 hexagonal source regions can ~e ormed in a ch;p area . - .
... .
. ` ' : ' . ' : : , ' .' " . :' ,: ' , : :,,:
~316Z9~
having a dimension of about 100 by 140 m;ls to produce an effective channel width o about 22,000 rnils, thus permitting very high current cap~city or the device.
The space between the adjacent sources may contain a polysilicon gate or any other gate structure where the gate structure i:s conltacted over the surace of the device by- elongated gate contact fingers wh;ch ensure good contact over the full surface of the device.
Each of the polygonal source regions is con-tacted by a uniform conductire layer which engages thexndi~idual polygonal sources through openings in an insulation layer covering the source regions, which openings can be formed by conventional D-MOS photolitho-graphic techniques. A source pad connection region is then provided for the source conductor and a gate pad connection region is provided for the elongated gate fingers and a drain connection region is made to the reverse surface of the semiconductor device.
~ plurality o~ such devices can be for3ned from a single semiconductor wa~er and the individual ele3ne3lts can be separated ~rom one another ~y- scriblng or any other suitable 3nethod.
In accordance wit~ another feature of the present invent~on, the p-type region ~Yhich deines the channel beneath the gate oxide has a relatively dceply di~fused portion beneath the source so that the p-type diffusion region will have a lar~e radius of curvature .
: ~, . . .
in thc n~-) epitaxial layer forming the body of the device. This deeper diffusion or deeper junction has been found to improve the voltage gradient at the edge of ~he device and thus permIts the use of the device with 5 h;gher reverse voltages, '~
B~IEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a plan view of a hi~h po~er MOSFET
chip which incorporates the present invention and particularly illustrates the metalizing pattèrns o the two sources and the gate.
Figure 2 is a cross-sectional view of Figure 1 taken across the section line 2-2 in Figure 1.
Figure 3 ~s a cross-sectional vlew similar to Figure 2 sho~Ying the initial step in the process of manufacture of the~chip of ~igures 1 and 2 and parti-cularly shows the P(~l contact implant and diffusion step.
Figure 4 shows the second step in the manu-facturing process and shows the n(~ implant and dif~
fusion step.
Figure 5 sho-~s a further step in tha process of manu-~acture of the chip of Figures 1 and 2 and shows the channel implant and diffuslon step.
' L3~%~
.. .
Figure 6 sho~s a further step in tlle process of manuacture and illustrates the source predeposition and diffusion step. This preeedes the last step in which the gate oxide is cut for the metalization step which produces th~ device of Figure 2.
Figure 7 is a plan view of the metaliz;ng pattern of a second em~odiment 'of the lnvention.
Figure ~ is a cross-sectional -vie-~ of ~igure 7 taken across the section line 8-8 in Figure 7.
Figure ~a is a view sim;lar to F;gure 2 and shows a modi~ied source contact configura*ion.
Figure 9 shows the shape of forward-current charac~erist;cs of a device like that of F;gure 2 where the region 40 beneath the oxide is n(-?.
Figure 10 shol~s the shape of the characteristic o a de~ice identical to that o~ ~igure 2 where the region 40 has hlgh n(+l conductivity.
Figure 11 is a plan view of a completed element on a semiconductor wafer prior -to the separation of the element away ~rom the remainder of the wafer.
Pigure 12 is an enlarged detail o the gate pad to illustrate the relationship of the gate contact and the source polygons in the region of the gate pad.
P;gure 13 IS a detailed plan view o a small portion of the source region during one stage o;~ the manufacturing process of the device.
.
": :
Figure 14 is a cross-sectional view of Figure 3 taken across the section line 14-14 in ~igure 13.
Figure 15 is similar to Figure 14 and shows the addition of a polysilicon gate~ a source electrode means --and drain electrode to the wa~er.
DETAILFD DESCRIPTION OF TIIE DRAWINGS
A first embodiment of the novel MOSPET deviceO e the present invention is shown in ~igures 1 and 2 which show a chip of monocrystalline silicon 20 ~or some other suitable material2, with the device electrodes ~ollowing the serpentine path 21 best shown in ~igure 1 in order to increase the current-carrying area of the device. Othe,r geome~ries could be used. The device illustrated has a reverse voltage of about 400 volts and an on-resistance less than about 0.4 ohm with a channel width of 50 centimeters. Devices having reverse voltages of from 90 to 400 volts have been made. The 400 volt devices have car~ied pulse currents of 30 amperes. The 90 volt devices have had for~ard on-resistances of about 0.1 ohm with a channel ~idth of50 centimeters and have carried pulse currents up to about 100 amperes. Higher and lower voltage devices can also be made Wit]l varying channel widths.
Presently kno~n ~IOSFET devices have much highsr on-resistances than the above. ~'or example, a 400 volt ~OSFET compara~le to that described below but made with 1'' , ' ' ' ,: . . :
``` ~L13~
prior art techniques would normally have an on-resistance much greater than abou~ 1.5 ohms, as compared to an on-resistance less than about ~.4 ohm in a device made ac-cording to this invention. Moreover~ the MOSFET switching device o~ the present invention will exhibi~ all of the desirable advantages o the MOS~`ET device, since it operates as a majority carrier device. Tllese advantages ;nclude high switching speed, lligh gain and avoidance of the secondary breakdown characteristics which exist in m;nority carrier devices.
The device o-f Figures 1 and 2 has two source electrodes 22 and 23 which are separated by a metalized gate electrode 24 which is fixed to but spaced from the semiconductor de~ice sur~ace by a silicon dioxide layer 25. The serpentine path followed by gate oxide 24 has a length o 50 centimete~rs and has 667 undulations, but is shown more simply in Figure 1. Oth~r channel widths can be used. Source electrodes 22 and 23 can be later-ally extended as shown to serve as field plates to help spread the depletion region created during reverse voltage conditions. Eac~l of source electrodes 22 and 23 supply current to a common drain electrode 26 which is fixed to the bottom o the wa-fer. The relative dimensions for the device, particularly in thickness, have been grossly exaggerated in Figure 2 for purposes o$ clarity. The s;licon chip or wafer 20 is formea on an n~) substrate which may have a thickness o-f about 14 mils. An n(-~ epitaxial layer is deposited on 3~
su~strate 20 and will have a ~hickness and resistivity depending on the desired reverse voltage. All junctions are formed in this epitaxial layer which can have a relatively high resistivity. In the embodiment dis-closed, the epitaxial layer has a thickness of about 35microns and a resistivity o about 20 ohm-centimeters.
~or a 90 volt device~ epitaxial layer 20 ~ould be about 10 microns thick and would have a resistivity of a~out
BACKGROUND OF THE INVFNTION
~ `
This ;nvention relates to MOS~T devices and _ ;
more specifically rclates to a novel struc~ure for a ~IOS~ET dcvice which permits i* to be used in high power applications with a relatively high reverse voltage and with an exceptionally low on-resistance. T}-e major ad-vantage of the bipolar transistor over the MOSFET
transistor is that t~e bipolar transistor has a very low on-resistance per unit conductive area. The MOSPET
*ransistor has numerous advantages over `the bipolar transistor including very high switching speed, very high gain and lack of the secondary breakdown character-istics e~hibited by a minority carrier devlce. However, because the MOSFET transistor has high on-resistance, its use in higll power s~ri*ching applications has been limited.
BRI~P DESCRIPTION OP ~HE INVENTION
The present inven*ion provides a novel high po~er MOSFET device which has a low forward resistance so that the device b~ecomes more competltive with bipolar devices in a s~itching type application wllile retaining all of the numerous advan*ages of the MOSFET over the bipolar device. In par*icular, with the present invention, the ~or~ard resistance per unit area of the ~-. .
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device has been reduced by at least a Eactor o two, compared to t~e limiting resistance per unit area previously existing in a MOS~ET-type device.
In one embodiment of the invention, two sources are placed on the same surface of a sernicon- -ductor wafer and are laterally spaced from one ano~her.
A gate electrode, depos~ted on a conventional gate oxide, is disposed be-twecn the sources. Two p-type conduc*ion channels are disposed beneath the gate and are spaced -~rom one anot~er by an n-type bulk region.
Current ~rom each source can flow through its respective-channel (after the creation of the inversion layer defining the channel~, so that majority carrier con-duction can flow through the bulk region and across the wafer or chlp to the drain electrode. The drain electrode may be on the opposite surface of the ~aer or on a laterally displaced surface region ~rom the source electrodes. Th~s configuration is made using the desirable manufacturing techniques of the D-~IOS device~ which permits precise allgr~ent of the various electrodes and channels and permlts use of extremely small channel lengths. Whlle the above con~iguration device may have been previously described ~or a ~IOSFET signal-type device, the structure is not that of the commonly used signal MOSFET.
The device is basically formed in an n(-~ sub-strate which has the relatively h;gh resisti~ity which is .
,~: ,' ' 36;~:91 necessary to obtain the desired reverse ~oltage capability o~ the device. For example, for a 400 volt device, the n~-~ region will have a resistivity of about 20 ohm-centîmeters. However, this same necessary high resistivity characteristIc has caused the on-resistance of -the ~IOSFET devlce, ~rhen used as a po~er switch, to be relatively high, In accordance with t~e present invention, it has been found that in the upper por~ion of the central bulk region ~o which the t~o inversion layers feed current in the path to the drain electrode, the central region immediately beneath the gate oxide can be a relatively low resistivit~ material formed, for example, by an nC+l diffusion in that channel reglon3 ~iithout affecting the reverse voItage characteristics of the device.
More specifically, and in accordance ~rith the invent~on, this co~mon~channel l~ili have an upper portion beneath the gate oxide and a lower bulk portion extending toward the drain electrode. The lo~er portion has the high resistivity desired to produce high reverse voltage ability-, and will have a depth dependent on the ~.
desired reverse voltage for the device. Thus, for a 400 volt devIce, the lower n~-l region may have a depth o about 35 mierons, wllile for a 90 volt device it ~ill have a depth of about ~ microns. Other deptlls ~ill be selected, depending on the desired reverse Yolta~e o:E the device to provide the necessary thicker depletion reglon required to prevent punch-through during reverse voltage conditions. The upper portion of the common channel is made highly conductive (n~) to a depth of from about 3 to about 6 microns. It has been found that this does not interfera with the reverse voltage withstand a~ility of the de~ice. ~owever, it decreases the on-resistance per unit area of the deviice by more than a factor of two.
The result~ng device becomes competitive with conventional high power blpolar switching devices since it retains all of the advantages of khe ~IOSFET deYice over the bipolar device but now has the relatively low fon~ard resistance which was the major characterizing advantage of the bipolar device.
The present in~ention also provides a novel high po~er ~IOSFET device with low forward resistance -where, however, a very high packing density is available and whLch can be made with relatively simple masks. The device further has relatively low capacitanc~.
Each o-f the individual spaced source reg;ons, in accordance with a preferred embodiment o *he invention, IS polygonal in coniguration and is preferably hexagonal to ensure a constank spacing along the major lengths of the sources disposed over the surface of tlle ~ody.
An exkremely large number o small hexagonal source elements may be formed in the sa~e sur-~ace of the semi-conductor body for a given device. By way of example, 6,600 hexagonal source regions can ~e ormed in a ch;p area . - .
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having a dimension of about 100 by 140 m;ls to produce an effective channel width o about 22,000 rnils, thus permitting very high current cap~city or the device.
The space between the adjacent sources may contain a polysilicon gate or any other gate structure where the gate structure i:s conltacted over the surace of the device by- elongated gate contact fingers wh;ch ensure good contact over the full surface of the device.
Each of the polygonal source regions is con-tacted by a uniform conductire layer which engages thexndi~idual polygonal sources through openings in an insulation layer covering the source regions, which openings can be formed by conventional D-MOS photolitho-graphic techniques. A source pad connection region is then provided for the source conductor and a gate pad connection region is provided for the elongated gate fingers and a drain connection region is made to the reverse surface of the semiconductor device.
~ plurality o~ such devices can be for3ned from a single semiconductor wa~er and the individual ele3ne3lts can be separated ~rom one another ~y- scriblng or any other suitable 3nethod.
In accordance wit~ another feature of the present invent~on, the p-type region ~Yhich deines the channel beneath the gate oxide has a relatively dceply di~fused portion beneath the source so that the p-type diffusion region will have a lar~e radius of curvature .
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in thc n~-) epitaxial layer forming the body of the device. This deeper diffusion or deeper junction has been found to improve the voltage gradient at the edge of ~he device and thus permIts the use of the device with 5 h;gher reverse voltages, '~
B~IEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a plan view of a hi~h po~er MOSFET
chip which incorporates the present invention and particularly illustrates the metalizing pattèrns o the two sources and the gate.
Figure 2 is a cross-sectional view of Figure 1 taken across the section line 2-2 in Figure 1.
Figure 3 ~s a cross-sectional vlew similar to Figure 2 sho~Ying the initial step in the process of manufacture of the~chip of ~igures 1 and 2 and parti-cularly shows the P(~l contact implant and diffusion step.
Figure 4 shows the second step in the manu-facturing process and shows the n(~ implant and dif~
fusion step.
Figure 5 sho-~s a further step in tha process of manu-~acture of the chip of Figures 1 and 2 and shows the channel implant and diffuslon step.
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Figure 6 sho~s a further step in tlle process of manuacture and illustrates the source predeposition and diffusion step. This preeedes the last step in which the gate oxide is cut for the metalization step which produces th~ device of Figure 2.
Figure 7 is a plan view of the metaliz;ng pattern of a second em~odiment 'of the lnvention.
Figure ~ is a cross-sectional -vie-~ of ~igure 7 taken across the section line 8-8 in Figure 7.
Figure ~a is a view sim;lar to F;gure 2 and shows a modi~ied source contact configura*ion.
Figure 9 shows the shape of forward-current charac~erist;cs of a device like that of F;gure 2 where the region 40 beneath the oxide is n(-?.
Figure 10 shol~s the shape of the characteristic o a de~ice identical to that o~ ~igure 2 where the region 40 has hlgh n(+l conductivity.
Figure 11 is a plan view of a completed element on a semiconductor wafer prior -to the separation of the element away ~rom the remainder of the wafer.
Pigure 12 is an enlarged detail o the gate pad to illustrate the relationship of the gate contact and the source polygons in the region of the gate pad.
P;gure 13 IS a detailed plan view o a small portion of the source region during one stage o;~ the manufacturing process of the device.
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Figure 14 is a cross-sectional view of Figure 3 taken across the section line 14-14 in ~igure 13.
Figure 15 is similar to Figure 14 and shows the addition of a polysilicon gate~ a source electrode means --and drain electrode to the wa~er.
DETAILFD DESCRIPTION OF TIIE DRAWINGS
A first embodiment of the novel MOSPET deviceO e the present invention is shown in ~igures 1 and 2 which show a chip of monocrystalline silicon 20 ~or some other suitable material2, with the device electrodes ~ollowing the serpentine path 21 best shown in ~igure 1 in order to increase the current-carrying area of the device. Othe,r geome~ries could be used. The device illustrated has a reverse voltage of about 400 volts and an on-resistance less than about 0.4 ohm with a channel width of 50 centimeters. Devices having reverse voltages of from 90 to 400 volts have been made. The 400 volt devices have car~ied pulse currents of 30 amperes. The 90 volt devices have had for~ard on-resistances of about 0.1 ohm with a channel ~idth of50 centimeters and have carried pulse currents up to about 100 amperes. Higher and lower voltage devices can also be made Wit]l varying channel widths.
Presently kno~n ~IOSFET devices have much highsr on-resistances than the above. ~'or example, a 400 volt ~OSFET compara~le to that described below but made with 1'' , ' ' ' ,: . . :
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prior art techniques would normally have an on-resistance much greater than abou~ 1.5 ohms, as compared to an on-resistance less than about ~.4 ohm in a device made ac-cording to this invention. Moreover~ the MOSFET switching device o~ the present invention will exhibi~ all of the desirable advantages o the MOS~`ET device, since it operates as a majority carrier device. Tllese advantages ;nclude high switching speed, lligh gain and avoidance of the secondary breakdown characteristics which exist in m;nority carrier devices.
The device o-f Figures 1 and 2 has two source electrodes 22 and 23 which are separated by a metalized gate electrode 24 which is fixed to but spaced from the semiconductor de~ice sur~ace by a silicon dioxide layer 25. The serpentine path followed by gate oxide 24 has a length o 50 centimete~rs and has 667 undulations, but is shown more simply in Figure 1. Oth~r channel widths can be used. Source electrodes 22 and 23 can be later-ally extended as shown to serve as field plates to help spread the depletion region created during reverse voltage conditions. Eac~l of source electrodes 22 and 23 supply current to a common drain electrode 26 which is fixed to the bottom o the wa-fer. The relative dimensions for the device, particularly in thickness, have been grossly exaggerated in Figure 2 for purposes o$ clarity. The s;licon chip or wafer 20 is formea on an n~) substrate which may have a thickness o-f about 14 mils. An n(-~ epitaxial layer is deposited on 3~
su~strate 20 and will have a ~hickness and resistivity depending on the desired reverse voltage. All junctions are formed in this epitaxial layer which can have a relatively high resistivity. In the embodiment dis-closed, the epitaxial layer has a thickness of about 35microns and a resistivity o about 20 ohm-centimeters.
~or a 90 volt device~ epitaxial layer 20 ~ould be about 10 microns thick and would have a resistivity of a~out
2.5 oh~-centimeters. A channel width o 5Q centimeters is also used ~o provIde the desired current carrying capacity for the device.
In a preerred embodiment o~ the invention J
there is an elongated serpentine P(+l conductivity region beneath each of the source electrodes 22 and 23 which thus extends around the serpentine path shown in Figure 1. These P~l regions are sho~n in Figure 2 as the p~) regions 30 and 31~ respectively, and are similar to those of the prior art except that the maximum P~i reg~on depth is greatly exaggerated in order to form a large radius of curvatur-e. This allows the device to withstand higher reverse voltages. By ay of example, t~e depth of re~ions 30 and 31 is preferably about 4 microns at the dimension X in Figur~ ;
2 and about 3 microns at the dimension Y in Figure 2.
By using D-~IOS abrication techniques~ two n~) regions 32 and 33 are formed beneath source elec-trodes 22 and 23, respectively, and define, with the ~ ~ ~ 3~%~
p(-~) regions 3~ and 31, n-type channel rcgions 34 and 35, respectively. Channel regions 34 and 35 are dis-posed beneath the gate oxide 25 and can be ;nverted by the appropriate application o a biasing signal to the gate 24 in order to permit conduction fro3n the sou~ce 22 and the source ~3 through the inversion layers into the central region disposed beneath the gate 24 and then to tlle drain electrode 26. Channels 34 and 35 may each have a length o~ a~out 1 micron.
It has previously been thought necessary that the central n(-l region between channels 34 and 35 (and between p(~) regions 30 and 31~ should have a high resistivity in order to permit the de~ice to withstand high reverse voltages. However, the relatively high resistIvity n(-) material is also a significant con-tributing factor to the high for~Yard on-resistance of the device.
In accordance with the significant feature of ~:
the present invention, a signi~icant portion o:E this central conducting region is ~lade relatively highly conductive and consists o~ an n(~l region 40 disposed immediately beneath the gate oxide 25. The n(~ region 40 has a depth of about 4 microns and could range from about 3 microns to about 6 microns. While its exact conductivity is not kno~n, and varles ~ith depth, it is high relative to the n( ) region beneath it. More particularly, leglcn 40 has a high conductivity ~hich ,, ~
36;2~
~ould be determined by a total ion implanted dose o-E
from about 1 x 10l2 to 1 x 1014 phosphorus atoms/cm2 at 50 kV followed by a dif-fusion drive at from 1150C
to 1250C for rom 30 mînutes to 24Q minutes. It has been found that by making this reg;on 4Q relatively highly conductive nC~ material through a diffusion or other operation, the device character;stics are s;gn;ficantly improved and the forward on-resistance o~ the device is reduced by a -factor greater than t~o.
Moreover, it has been ~ound that the provision of the high conductivity region 40 does not interfere with the reverse voltage characteristics of the device.
Accordingly, by making the region beneath the gate oxide 25 and between channels 34 and 35 more highly conductive, the for~ard on-resistance of the ultimate high po~er~
switching device has been significantly reduced and the ~OSFET device becomes far more competitlve ~ith an equivalent junc*ion-type device while still retaining all of the advan~ages o$ the MOSFET majority carrler operation.
In the above description of Figures 1 and 2, it has been assumed that the conduction channels 34 and 35 are o~ P(~l material and are, accordingly, inverted to an n-typ~ conductivity to provide a majority carrier conduction channel from sources 22 and 23 to the central region 40 upon the applicat;on of an appropriate gate voltage. Clearly, ho~ever~ all of these conductivity ... .
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types could be reversed so that the device could work as a ' p-cllanncl clevice rather than an n-channel de~ice as disclosed.
One process by which the device oE Figures 1 , and 2 could be constructed is shown in Figures 3 to 6.
Reerring to ~igure 3, the base wafer 20 is shol~n as an n(+) material having an n(,-~ epitaxially deposited region on top thereo. ~ thick oxicle layer 50 is formed on waEer 20 and windows 51 and 52 are opened 10 therein. The open windows 51 and 52 are exposed ko a ;,~
beam of boron atoms in an ion implanting apparatus to form p(~ regions. Thereafter the implanted boron atoms are caused to di-~use deeper into the waEer to form the rounded pt+~ concentration region shown in ~, Pigure 3 which might have a depth of about 4 microns.
During this diffusion operation, shallow oxide layers 53 and 54 grow over th~ windows 51 and 52.
~s is next sho~n in Figure 4, windows 61 and 62 are cut in the oxide layer 5Q and an n(+) implant takes place to implant the n(,+) regions 63 and 64 into the (-l epitaxial layer. This n(~l implantation can be carried out with a phosphorus beam. Thereafter~ the implanted reglons are subjected to a di-ffusion step to ~ -cause the regions 63 and 64 to expand and deepen to a depth of a~out 3-1/2 microns with a concentration determined by an implantation dose of l x 1012 to ~ -- l x 1014 phosp]lorus atoms/cm2 ollowed by a drive for 1136Z9~ ~
30 m;nutes to 4 hours at from 1150C to 1250C. As will -be later seen, regions 63 and G4 produce the novel n(-~) region which substantially reduces the on-resistance of the device.
It should be noted that the n~) regions 63 and 6~ could, i desired, be epitaxially deposited and need not be dif~used. Similarly, the resulting device being described herein could be manu-Eactured by any desired process as would be apparent to those skilled in the art.
The next step in the process is shown in Figure 5 and is the channel implantation and diffusion step in which the P(+l regions 71 and 72 are formed through~the same windows 61 and 62 that were used for the n(+~ implantation for regions 63 and 64. The P~-~?
regions 71 and 72 are formed by implanting with a boron beam to a dose o about 5 ~ 1013 to 5 x 1014 atomslcm2 ollowed by a diffusion drive for 30 to 120 minutes at 1150C to 1250C.
Thereafter, and as shown in ~igure 6, steps are carried out for the source predeposition and the difusion of the source regions 32 and 33. This is carried out by a conventional and non-critical phosphorus difusion step where the diffusion proceeds t]lroug]l the windows 61 and 62 so that the source regions 32 and 33 are automatically aligned relative to thc other preformed .' ~.
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regions. Thus, the wa~er is placed in a furnace and exposed ~o POC13 suspended in a carrier gas for from 10 minutes to 50 minutes at a kemperature of from 850C to 1000.
~Yhen this step is completed, the basic ~:
junction configuration required in Figure 2 is formed with short p~+~ regions disposed beneath the oxide 50 to serve as the conducting channel for the ultimately constructed device and with an n(+) region filllng the area bet~e2n the channels 34 and 35 and between p~
regions 30 and 31. The manufacturing process then ;~
cont;nues from the step of Figure 6 to the device shown - in Pigure 2 wherein the oxide surfaces on top of the chip are suitably stripped and the metalizing patterns for contacts 22 ? 23 and 24 are formed to establish electrical contacts to the de~ice. The drain contact 26 is applied to the device in a subsequent metaliz;ng operation. Thereafter, the entire device may be appro-priately coated with a suitable passivation coating and ~.
~ire leads are connected to the source electrodes 22 and 23 and the gate 24, The device is then mounted within a suitable protective housing, witll the drain electrode fixed to the housing or other conductive support l~hich serves as a drain connection.
The device sho~n in Figures 1 and 2 utilizes a serpentine path for each of the source regions and gate regions and a drain on the surface of the ~afer Z~
opposite *o the source electrodes. Other configurations can be used. Figures 7 and 8 illustrate a planar con-figuration which is a simple rectangular arrangement having a ring-shaped gate 80 ~hich is disposed between S a first source electrode 81 of ring shape and a central source 82. The device as shown in Figure 8 is contained witllin a base ~af2r of p( ) monocrystalline silicon 83 ~hich may have a buried n~l region 84 to reduce the lateral resistanca of the various current paths of the device leading to the laterally displaced drain electrode 85 whlch surrounds source 81.
A ring-shaped n(+) region 86 is formed within the device as sho~n in ~igure 8 and, in accordance with the present invention, the ring-shaped region 86 is o~
much higher conductivity than the n(-~ epitaxially deposited region 87 which contains all of the junctions o~ the device.
The ring shaped region 86 extends from the reglon beneath the gate oxide 88 and adjoins the ends o-f the t~o con-ducting channels formed between the ring-shaped p(~
region 89 and the central p~ region 91 disposed ~eneath the ring-shaped source 81 and central source 82 9 respectively.
~ It ~i11 also be noted in Figure 8 that the ~ ;
outer periphery 90 of the p(~) ring 89 has a large radius to assist the device in ~ithstanding high reverse voltages.
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An n~+) region 95 in Figure 8 is provided to ensure good contact to drain electrode 85. Drain electrode 85 is widely laterally spaced from source 81 (by greater than about 90 microns~ The drain con*act 85 is surrounded by a PC~ isolation dif:fusion 96 to isolate ~he device from other devices on the same chip or l~afer.
In the arrangement of ~igure 8, like that of Figure 2, current flow from source 81 and 82 goes through the width of epitaxial region 87, through the region 86. The cllrrent then flows laterally outward and then up to the drain contact 85. As in the embodiment of ~igure 2, device resistance is greatly reduced by the relatively highly conductive region 86.
In carrying out the a~ove invention, it .
should be noted that any type of contact material can be used to make the source and gate contacts. By way of example, aluminum could be used for the source electrodes while a polysilicon material can be used for the conductive gate 80 in ~igure 8 or the conductive gate 24 in ~i~ure 2.
Nu~erous other geometries can be used to make the device of the învention~ including a plul-ality of pairs of straight, parallel source elements with respectivel~ interposed gates and the like.
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The source electrodes 22 and 23 have been sho~n as separate electrodes which can be connected to separate leads. Clearly, the sources 22 and 23 could be directly connected as shown in Figure 8a where compollents s;.milar to those of ~igurc 2 have been given similar identiying numerals; In ~igure 8a, hol~ever, the gate electrode is a polysilicon layer 101 ~in place of aluminum~ deposited atop gate oxide 25. The gate 25 is then covered Wit}l oxide layer 102 and a conductive 10 layer 103 connects the two sources 22 and 23 together to form a single source conductor wh;ch is insulated from gate 101. Connection is made to the gate at some sultabl.e edge portion o~ the ~afer.
Figures 9 and 10 show the shape of measured curvas wh;ch demonstrate~ the reduction in for~Yard : resistance when the region 40 is made highly conductive ~; (n~). In Figure ~, the devlce tested had a region 40 which had the n~-) resistivity oE the apitaxial region.
Thus~ the forward resistance is characteristicàlly high ~0 at di~ferent gate biases as sho~Yn in ~igure ~.
In the device of the invention ~Yhere region 40 is of n(~) conductivity,: there is a dramatic decrease in the on-resistAnce as sho~n in Pigure 10 -for all gate voltages before velocity saturation o the electrons occurs.
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I'he polygon configuration of the source regions o the present invention is best shown in Figures 13, 14 and 15 wIIich are first described.
Referring irst to Figures 13 and 14, t}Ie de~ice is shown prior to the application o:E th~ gate, source and drain electrodes. The manufacturing process can be of any desired type including the D-~IOS fabr;cation techniques and ion implantation techniques previously described for the formation of the junction and placement o the electrodes in the most advantageous way.
The device IS described as an N channel enhancement type device. It will be apparent that the in~ention will also apply to P channel devices and to depletion mode devices.
The devIce of Figures 13 and 14 has a plurality o~ polygonal source regions on one sur~ace of the device~
where thes_ polygonal regions are preferably hexagonal in shape. Other shapes such as squares could have been used but the hexagonal shape provides better uniformity of spacing between adjacent source region peri~eters.
In Figures 13 and 14, the hexagonal source regions are formed in a ~asic semiconductor body or wafer which can be an N type wafer 120 of monocrystalline silicon which has a thIn N~-) epitaxial region 121 deposited thereon as ~est s~Iown in ~igure 14. All junctions are formed in epitaxial region 121. By using suitable masks, a plurali-ty of P type regions such as regions 122 ~3~
and 123 in Figures 13 and 14 are formed in one surface of the semiconductor wafer region 121, where these regions are generally polygonal in configuration and, preferably~
are hexagonal.
A very large number of SUC]I polygonal reg;ons are formed. For example, in a device having a surface dimensions of 100 by 14~ mils, approximately 6600 poly-gonal regions are ormed to produce a ~otal channel width of about 22,000 mils. Each of the polygonal regions may have a ~idth measured perpendicular to t~o opposing sides of khe polygon o about 1 mil or less. The regions are spaced from one another by a distance of about 0.6 mil when measured perpendicularly bet~een the adjacent straight sides of adjacent polygonal regions.
The P+ regions 122 and 123 will have a depth d which is prcferably about 5 microns to produce a high and reliable field characteristic. Each of th~ P regions has an outer~shelf region shown as shalf regions 124 and 125 for P reglons 122 and 123, respectiYely, having a depth s of about l.S microns. This distance should be as small as poss;ble to reduce the capacitance of the deYice. :
Each of ~he polygon regions including polygonal ~`
regions 122 and 123 receive Nt polygonal ring regions 126 and 127, respective]y. Shelves 124 and lZ5 are located beneath regions 126 and 127, respectively. N~
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regions 126 and 127 coopcrate with a relatively conductive N~ region 128 which is the N~ region disposed between adjacent P type polygons to define the various c~lannels bet~een the source regions and a drain contact ~hich will be later described.
The hIghly conductive N~ regions 128 are formed in the manner described or the precedin~ embodi~ents and produce a very lo~ forward resistance for the device.
In Pigures 13 and 14, it will be noted that the entire surface of the wafer is covered with an oxide layer or combined conventional oxide and nitride layers which are produced for the formation of the various junctions. Thls layer is shown as the insulation layer 130, The insulation layer 130 is provided with polygonal shaped openings such as openings 131 and 132 immediately above polygonal regions 122 and 123. Openings 131 and 132 have boundarles overlying the N~ type source rings 126 20 and 127 for the ragions 122 and 123, respectively. The o~lde strips 130, which remain after the formation of the polygonal shaped openings, de~ine the gate oxide for the device.
Electrodes may then be applied to the device as sho~n in Figure 15. These include a polysilicon grid ~hich includes polysilicon sections 140, 141 and 142 ~hich overlie the oxide sections 130.
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A silicon dioxide coating ls then deposited .
atop the polysilicon grid 140 shown as coating sections 145, 146 and 147 in Figure 15 which.insulates the poly~
sili.con control electrode and the source electrode which is subsequently deposlted over the entire upper sur-face of the wafer. In F;gure 15 the source electrode is sllo~n as conductive coating 150 which may be of any desired material, such as aluminum. A drain electrode 151 is also applied to the device.
The resulting device o~ Figure 15 is an N
channel type de~ice wherein channel regions are formed between each of the individual sources and the body of the semiconductor material which ultimately leads to the drain ele~ctrode 151. Thus, a channel region 160 is `.
formed between the source ring 126, ~rhich is connected to source elec-trode 150, and the ~+ region 128 which ~:
ultimately leads to the drain electrode 151. Channel 160 is inverted to the N type conductivity upon the application of a suitable control voltage to the gate 140.
In a similar manner, chann~ls 161 and 162 are ormed between the source region l26, whic]l is connected to the conductor 150, and the surrounding N+ region 128 which leads to the drain 151. Thus, upon application of a suitable control voltage -to the polysilicon gate (including finger 141 in Figure 15~ cha~nels 161 and 162 become conductive to permit majority carrier conduction from .
the source electrode 150. to the drain 151.
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Each of the sources form parallel conduction paths wllere, for example, channels 163 and 164 beneath gate element 142 permit conduction from the source ring 127 and an N type source strip 170 to the Nf region 128 and then to the drain electrode 151.
It is to be noted that Figures 14 and 15 illus-trate an end P type region 17] which encloses the edge of the wa~er.
The contact 150 of Figure lS is preferably an aluminum contact. It ~ill be noted that the contact region for the contact 150 lies entirely over and in alignment with the deeper portion of the P type region 122. This is done since it was found that aluminum used for the electrode 150 might spike through very thin regions of the P type material. Thus, one feature of the present invention is to ensure that the contact 150 lies principally over the deeper portions of the P
regions such as P regions 122 and 123. This then permits the active channel regions defined by the annular 2~ shelves 124 and 125 to be as thin as desired :;n order to substantially reduce the device capacîtance.
Figure 11 illustrates one completed device using the polygonal source pattern of Figure 15. The completed device shown in Figure 11 is contained within 25 the scribe regions 180~ 181, 182 and 183 which enable the breaking out of a plurality o~ unitary devices each having a di-nension of 100 by 14Q mils from the body of the wafer.
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The polygonal regions described are contained in a plurality of columns and rows. By way o:E example, the dimension A contains 65 columns of polygonal regions -.
and may bs about 83 mils. The dimallsion B may contain 100 rows of polygonal regions and may be about 148 mils. Dim2nsion C, WhiC}l is vdisposed bet~een a source connec-tion pad 190 and a gate connection pad 19l, may contain 82 ro~s of polygonal elements.
The source pad 1~0 is a relati~ely heavy metal sec~ion which is directly connected to the alum;num source electrode 150 and permits conveniant lead connection for the sourca.
The gate connection pad 191 is electrically connectGd to a plurality of extending fingers 192, 193, lS 194 and 195 which extend symmetrically over the outer surface of the area contain~ng the ~olygonal regions and make electrical connection to the polysillcon gate as ~ill be described in connection with Figure 12.
Fina~ly the outer circum~er~nce of the device contains the P~ deep diffusion ring 171 which may be connected to a fiald plate 201 sho~n in Figure 11.
Figure 12 S]lOWS a ~ortion o~ the gate pad 191 and tho gate fingars 194 and 195. It is desirable to make a plurality of contacts to the polysilicon gate in ordar to reduca the R-C delay constant o-f the device.
The polysilicon gate has a plurality of regions including regions 210, 211, 212 and the like ~hich extend out-~ardly ~3~
. ~ ;
and receive extensions of t]le gate pad and the gate pad elements 194 and 195. The polysil;con gate regions may be left exposed during the formation of the oxide coating 145-1~6-1~7 i.n Figure 15 and are not coated by the source electrode 50. Note that in Figure 12 the axis 220 is the axis o:E symmetry 220 which is that shown in Figure 11.
Although the present invention has been described in connection with a preferred embodi~ent thereof, many ~ariations and modifications will now become apparent to those skilled in the art. It is preferredS
therefore, that the present invention be limited not by .
the specific disclosure herein, but only by the appended claims~
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In a preerred embodiment o~ the invention J
there is an elongated serpentine P(+l conductivity region beneath each of the source electrodes 22 and 23 which thus extends around the serpentine path shown in Figure 1. These P~l regions are sho~n in Figure 2 as the p~) regions 30 and 31~ respectively, and are similar to those of the prior art except that the maximum P~i reg~on depth is greatly exaggerated in order to form a large radius of curvatur-e. This allows the device to withstand higher reverse voltages. By ay of example, t~e depth of re~ions 30 and 31 is preferably about 4 microns at the dimension X in Figur~ ;
2 and about 3 microns at the dimension Y in Figure 2.
By using D-~IOS abrication techniques~ two n~) regions 32 and 33 are formed beneath source elec-trodes 22 and 23, respectively, and define, with the ~ ~ ~ 3~%~
p(-~) regions 3~ and 31, n-type channel rcgions 34 and 35, respectively. Channel regions 34 and 35 are dis-posed beneath the gate oxide 25 and can be ;nverted by the appropriate application o a biasing signal to the gate 24 in order to permit conduction fro3n the sou~ce 22 and the source ~3 through the inversion layers into the central region disposed beneath the gate 24 and then to tlle drain electrode 26. Channels 34 and 35 may each have a length o~ a~out 1 micron.
It has previously been thought necessary that the central n(-l region between channels 34 and 35 (and between p(~) regions 30 and 31~ should have a high resistivity in order to permit the de~ice to withstand high reverse voltages. However, the relatively high resistIvity n(-) material is also a significant con-tributing factor to the high for~Yard on-resistance of the device.
In accordance with the significant feature of ~:
the present invention, a signi~icant portion o:E this central conducting region is ~lade relatively highly conductive and consists o~ an n(~l region 40 disposed immediately beneath the gate oxide 25. The n(~ region 40 has a depth of about 4 microns and could range from about 3 microns to about 6 microns. While its exact conductivity is not kno~n, and varles ~ith depth, it is high relative to the n( ) region beneath it. More particularly, leglcn 40 has a high conductivity ~hich ,, ~
36;2~
~ould be determined by a total ion implanted dose o-E
from about 1 x 10l2 to 1 x 1014 phosphorus atoms/cm2 at 50 kV followed by a dif-fusion drive at from 1150C
to 1250C for rom 30 mînutes to 24Q minutes. It has been found that by making this reg;on 4Q relatively highly conductive nC~ material through a diffusion or other operation, the device character;stics are s;gn;ficantly improved and the forward on-resistance o~ the device is reduced by a -factor greater than t~o.
Moreover, it has been ~ound that the provision of the high conductivity region 40 does not interfere with the reverse voltage characteristics of the device.
Accordingly, by making the region beneath the gate oxide 25 and between channels 34 and 35 more highly conductive, the for~ard on-resistance of the ultimate high po~er~
switching device has been significantly reduced and the ~OSFET device becomes far more competitlve ~ith an equivalent junc*ion-type device while still retaining all of the advan~ages o$ the MOSFET majority carrler operation.
In the above description of Figures 1 and 2, it has been assumed that the conduction channels 34 and 35 are o~ P(~l material and are, accordingly, inverted to an n-typ~ conductivity to provide a majority carrier conduction channel from sources 22 and 23 to the central region 40 upon the applicat;on of an appropriate gate voltage. Clearly, ho~ever~ all of these conductivity ... .
, - - , ::, . ;: , :: ,, ; : ;:
types could be reversed so that the device could work as a ' p-cllanncl clevice rather than an n-channel de~ice as disclosed.
One process by which the device oE Figures 1 , and 2 could be constructed is shown in Figures 3 to 6.
Reerring to ~igure 3, the base wafer 20 is shol~n as an n(+) material having an n(,-~ epitaxially deposited region on top thereo. ~ thick oxicle layer 50 is formed on waEer 20 and windows 51 and 52 are opened 10 therein. The open windows 51 and 52 are exposed ko a ;,~
beam of boron atoms in an ion implanting apparatus to form p(~ regions. Thereafter the implanted boron atoms are caused to di-~use deeper into the waEer to form the rounded pt+~ concentration region shown in ~, Pigure 3 which might have a depth of about 4 microns.
During this diffusion operation, shallow oxide layers 53 and 54 grow over th~ windows 51 and 52.
~s is next sho~n in Figure 4, windows 61 and 62 are cut in the oxide layer 5Q and an n(+) implant takes place to implant the n(,+) regions 63 and 64 into the (-l epitaxial layer. This n(~l implantation can be carried out with a phosphorus beam. Thereafter~ the implanted reglons are subjected to a di-ffusion step to ~ -cause the regions 63 and 64 to expand and deepen to a depth of a~out 3-1/2 microns with a concentration determined by an implantation dose of l x 1012 to ~ -- l x 1014 phosp]lorus atoms/cm2 ollowed by a drive for 1136Z9~ ~
30 m;nutes to 4 hours at from 1150C to 1250C. As will -be later seen, regions 63 and G4 produce the novel n(-~) region which substantially reduces the on-resistance of the device.
It should be noted that the n~) regions 63 and 6~ could, i desired, be epitaxially deposited and need not be dif~used. Similarly, the resulting device being described herein could be manu-Eactured by any desired process as would be apparent to those skilled in the art.
The next step in the process is shown in Figure 5 and is the channel implantation and diffusion step in which the P(+l regions 71 and 72 are formed through~the same windows 61 and 62 that were used for the n(+~ implantation for regions 63 and 64. The P~-~?
regions 71 and 72 are formed by implanting with a boron beam to a dose o about 5 ~ 1013 to 5 x 1014 atomslcm2 ollowed by a diffusion drive for 30 to 120 minutes at 1150C to 1250C.
Thereafter, and as shown in ~igure 6, steps are carried out for the source predeposition and the difusion of the source regions 32 and 33. This is carried out by a conventional and non-critical phosphorus difusion step where the diffusion proceeds t]lroug]l the windows 61 and 62 so that the source regions 32 and 33 are automatically aligned relative to thc other preformed .' ~.
L3~
regions. Thus, the wa~er is placed in a furnace and exposed ~o POC13 suspended in a carrier gas for from 10 minutes to 50 minutes at a kemperature of from 850C to 1000.
~Yhen this step is completed, the basic ~:
junction configuration required in Figure 2 is formed with short p~+~ regions disposed beneath the oxide 50 to serve as the conducting channel for the ultimately constructed device and with an n(+) region filllng the area bet~e2n the channels 34 and 35 and between p~
regions 30 and 31. The manufacturing process then ;~
cont;nues from the step of Figure 6 to the device shown - in Pigure 2 wherein the oxide surfaces on top of the chip are suitably stripped and the metalizing patterns for contacts 22 ? 23 and 24 are formed to establish electrical contacts to the de~ice. The drain contact 26 is applied to the device in a subsequent metaliz;ng operation. Thereafter, the entire device may be appro-priately coated with a suitable passivation coating and ~.
~ire leads are connected to the source electrodes 22 and 23 and the gate 24, The device is then mounted within a suitable protective housing, witll the drain electrode fixed to the housing or other conductive support l~hich serves as a drain connection.
The device sho~n in Figures 1 and 2 utilizes a serpentine path for each of the source regions and gate regions and a drain on the surface of the ~afer Z~
opposite *o the source electrodes. Other configurations can be used. Figures 7 and 8 illustrate a planar con-figuration which is a simple rectangular arrangement having a ring-shaped gate 80 ~hich is disposed between S a first source electrode 81 of ring shape and a central source 82. The device as shown in Figure 8 is contained witllin a base ~af2r of p( ) monocrystalline silicon 83 ~hich may have a buried n~l region 84 to reduce the lateral resistanca of the various current paths of the device leading to the laterally displaced drain electrode 85 whlch surrounds source 81.
A ring-shaped n(+) region 86 is formed within the device as sho~n in ~igure 8 and, in accordance with the present invention, the ring-shaped region 86 is o~
much higher conductivity than the n(-~ epitaxially deposited region 87 which contains all of the junctions o~ the device.
The ring shaped region 86 extends from the reglon beneath the gate oxide 88 and adjoins the ends o-f the t~o con-ducting channels formed between the ring-shaped p(~
region 89 and the central p~ region 91 disposed ~eneath the ring-shaped source 81 and central source 82 9 respectively.
~ It ~i11 also be noted in Figure 8 that the ~ ;
outer periphery 90 of the p(~) ring 89 has a large radius to assist the device in ~ithstanding high reverse voltages.
~3~
An n~+) region 95 in Figure 8 is provided to ensure good contact to drain electrode 85. Drain electrode 85 is widely laterally spaced from source 81 (by greater than about 90 microns~ The drain con*act 85 is surrounded by a PC~ isolation dif:fusion 96 to isolate ~he device from other devices on the same chip or l~afer.
In the arrangement of ~igure 8, like that of Figure 2, current flow from source 81 and 82 goes through the width of epitaxial region 87, through the region 86. The cllrrent then flows laterally outward and then up to the drain contact 85. As in the embodiment of ~igure 2, device resistance is greatly reduced by the relatively highly conductive region 86.
In carrying out the a~ove invention, it .
should be noted that any type of contact material can be used to make the source and gate contacts. By way of example, aluminum could be used for the source electrodes while a polysilicon material can be used for the conductive gate 80 in ~igure 8 or the conductive gate 24 in ~i~ure 2.
Nu~erous other geometries can be used to make the device of the învention~ including a plul-ality of pairs of straight, parallel source elements with respectivel~ interposed gates and the like.
9 ~ 3~%~
The source electrodes 22 and 23 have been sho~n as separate electrodes which can be connected to separate leads. Clearly, the sources 22 and 23 could be directly connected as shown in Figure 8a where compollents s;.milar to those of ~igurc 2 have been given similar identiying numerals; In ~igure 8a, hol~ever, the gate electrode is a polysilicon layer 101 ~in place of aluminum~ deposited atop gate oxide 25. The gate 25 is then covered Wit}l oxide layer 102 and a conductive 10 layer 103 connects the two sources 22 and 23 together to form a single source conductor wh;ch is insulated from gate 101. Connection is made to the gate at some sultabl.e edge portion o~ the ~afer.
Figures 9 and 10 show the shape of measured curvas wh;ch demonstrate~ the reduction in for~Yard : resistance when the region 40 is made highly conductive ~; (n~). In Figure ~, the devlce tested had a region 40 which had the n~-) resistivity oE the apitaxial region.
Thus~ the forward resistance is characteristicàlly high ~0 at di~ferent gate biases as sho~Yn in ~igure ~.
In the device of the invention ~Yhere region 40 is of n(~) conductivity,: there is a dramatic decrease in the on-resistAnce as sho~n in Pigure 10 -for all gate voltages before velocity saturation o the electrons occurs.
, :
~3~
I'he polygon configuration of the source regions o the present invention is best shown in Figures 13, 14 and 15 wIIich are first described.
Referring irst to Figures 13 and 14, t}Ie de~ice is shown prior to the application o:E th~ gate, source and drain electrodes. The manufacturing process can be of any desired type including the D-~IOS fabr;cation techniques and ion implantation techniques previously described for the formation of the junction and placement o the electrodes in the most advantageous way.
The device IS described as an N channel enhancement type device. It will be apparent that the in~ention will also apply to P channel devices and to depletion mode devices.
The devIce of Figures 13 and 14 has a plurality o~ polygonal source regions on one sur~ace of the device~
where thes_ polygonal regions are preferably hexagonal in shape. Other shapes such as squares could have been used but the hexagonal shape provides better uniformity of spacing between adjacent source region peri~eters.
In Figures 13 and 14, the hexagonal source regions are formed in a ~asic semiconductor body or wafer which can be an N type wafer 120 of monocrystalline silicon which has a thIn N~-) epitaxial region 121 deposited thereon as ~est s~Iown in ~igure 14. All junctions are formed in epitaxial region 121. By using suitable masks, a plurali-ty of P type regions such as regions 122 ~3~
and 123 in Figures 13 and 14 are formed in one surface of the semiconductor wafer region 121, where these regions are generally polygonal in configuration and, preferably~
are hexagonal.
A very large number of SUC]I polygonal reg;ons are formed. For example, in a device having a surface dimensions of 100 by 14~ mils, approximately 6600 poly-gonal regions are ormed to produce a ~otal channel width of about 22,000 mils. Each of the polygonal regions may have a ~idth measured perpendicular to t~o opposing sides of khe polygon o about 1 mil or less. The regions are spaced from one another by a distance of about 0.6 mil when measured perpendicularly bet~een the adjacent straight sides of adjacent polygonal regions.
The P+ regions 122 and 123 will have a depth d which is prcferably about 5 microns to produce a high and reliable field characteristic. Each of th~ P regions has an outer~shelf region shown as shalf regions 124 and 125 for P reglons 122 and 123, respectiYely, having a depth s of about l.S microns. This distance should be as small as poss;ble to reduce the capacitance of the deYice. :
Each of ~he polygon regions including polygonal ~`
regions 122 and 123 receive Nt polygonal ring regions 126 and 127, respective]y. Shelves 124 and lZ5 are located beneath regions 126 and 127, respectively. N~
L13~
regions 126 and 127 coopcrate with a relatively conductive N~ region 128 which is the N~ region disposed between adjacent P type polygons to define the various c~lannels bet~een the source regions and a drain contact ~hich will be later described.
The hIghly conductive N~ regions 128 are formed in the manner described or the precedin~ embodi~ents and produce a very lo~ forward resistance for the device.
In Pigures 13 and 14, it will be noted that the entire surface of the wafer is covered with an oxide layer or combined conventional oxide and nitride layers which are produced for the formation of the various junctions. Thls layer is shown as the insulation layer 130, The insulation layer 130 is provided with polygonal shaped openings such as openings 131 and 132 immediately above polygonal regions 122 and 123. Openings 131 and 132 have boundarles overlying the N~ type source rings 126 20 and 127 for the ragions 122 and 123, respectively. The o~lde strips 130, which remain after the formation of the polygonal shaped openings, de~ine the gate oxide for the device.
Electrodes may then be applied to the device as sho~n in Figure 15. These include a polysilicon grid ~hich includes polysilicon sections 140, 141 and 142 ~hich overlie the oxide sections 130.
, - 23 - . . .
A silicon dioxide coating ls then deposited .
atop the polysilicon grid 140 shown as coating sections 145, 146 and 147 in Figure 15 which.insulates the poly~
sili.con control electrode and the source electrode which is subsequently deposlted over the entire upper sur-face of the wafer. In F;gure 15 the source electrode is sllo~n as conductive coating 150 which may be of any desired material, such as aluminum. A drain electrode 151 is also applied to the device.
The resulting device o~ Figure 15 is an N
channel type de~ice wherein channel regions are formed between each of the individual sources and the body of the semiconductor material which ultimately leads to the drain ele~ctrode 151. Thus, a channel region 160 is `.
formed between the source ring 126, ~rhich is connected to source elec-trode 150, and the ~+ region 128 which ~:
ultimately leads to the drain electrode 151. Channel 160 is inverted to the N type conductivity upon the application of a suitable control voltage to the gate 140.
In a similar manner, chann~ls 161 and 162 are ormed between the source region l26, whic]l is connected to the conductor 150, and the surrounding N+ region 128 which leads to the drain 151. Thus, upon application of a suitable control voltage -to the polysilicon gate (including finger 141 in Figure 15~ cha~nels 161 and 162 become conductive to permit majority carrier conduction from .
the source electrode 150. to the drain 151.
~,~,3~?
Each of the sources form parallel conduction paths wllere, for example, channels 163 and 164 beneath gate element 142 permit conduction from the source ring 127 and an N type source strip 170 to the Nf region 128 and then to the drain electrode 151.
It is to be noted that Figures 14 and 15 illus-trate an end P type region 17] which encloses the edge of the wa~er.
The contact 150 of Figure lS is preferably an aluminum contact. It ~ill be noted that the contact region for the contact 150 lies entirely over and in alignment with the deeper portion of the P type region 122. This is done since it was found that aluminum used for the electrode 150 might spike through very thin regions of the P type material. Thus, one feature of the present invention is to ensure that the contact 150 lies principally over the deeper portions of the P
regions such as P regions 122 and 123. This then permits the active channel regions defined by the annular 2~ shelves 124 and 125 to be as thin as desired :;n order to substantially reduce the device capacîtance.
Figure 11 illustrates one completed device using the polygonal source pattern of Figure 15. The completed device shown in Figure 11 is contained within 25 the scribe regions 180~ 181, 182 and 183 which enable the breaking out of a plurality o~ unitary devices each having a di-nension of 100 by 14Q mils from the body of the wafer.
.~.. . .
: .. : . :. . . .
.. ... , . : . . : :
L3~
The polygonal regions described are contained in a plurality of columns and rows. By way o:E example, the dimension A contains 65 columns of polygonal regions -.
and may bs about 83 mils. The dimallsion B may contain 100 rows of polygonal regions and may be about 148 mils. Dim2nsion C, WhiC}l is vdisposed bet~een a source connec-tion pad 190 and a gate connection pad 19l, may contain 82 ro~s of polygonal elements.
The source pad 1~0 is a relati~ely heavy metal sec~ion which is directly connected to the alum;num source electrode 150 and permits conveniant lead connection for the sourca.
The gate connection pad 191 is electrically connectGd to a plurality of extending fingers 192, 193, lS 194 and 195 which extend symmetrically over the outer surface of the area contain~ng the ~olygonal regions and make electrical connection to the polysillcon gate as ~ill be described in connection with Figure 12.
Fina~ly the outer circum~er~nce of the device contains the P~ deep diffusion ring 171 which may be connected to a fiald plate 201 sho~n in Figure 11.
Figure 12 S]lOWS a ~ortion o~ the gate pad 191 and tho gate fingars 194 and 195. It is desirable to make a plurality of contacts to the polysilicon gate in ordar to reduca the R-C delay constant o-f the device.
The polysilicon gate has a plurality of regions including regions 210, 211, 212 and the like ~hich extend out-~ardly ~3~
. ~ ;
and receive extensions of t]le gate pad and the gate pad elements 194 and 195. The polysil;con gate regions may be left exposed during the formation of the oxide coating 145-1~6-1~7 i.n Figure 15 and are not coated by the source electrode 50. Note that in Figure 12 the axis 220 is the axis o:E symmetry 220 which is that shown in Figure 11.
Although the present invention has been described in connection with a preferred embodi~ent thereof, many ~ariations and modifications will now become apparent to those skilled in the art. It is preferredS
therefore, that the present invention be limited not by .
the specific disclosure herein, but only by the appended claims~
- ' . ' ;
Claims (12)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A high power MOSFET device; said device comprising a wafer of semiconductor material of one of the conductivity types and having a first surface and a parallel second surface; said first surface having a large plurality of highly packed, equally spaced symme-trically disposed polygonal base regions of the opposite conductivity type to said one of the conductivity types therein; each of said base regions having respective polygonal source regions of said one of the conductivity types disposed therein and extending to said first surface; a gate insulation layer on said first surface and disposed between said source regions; and a gate electrode on said gate insulation layer; a drain electrode on said second surface; a single, continuous source electrode means connected to said polygonal source regions; a respective ring-shaped channel means disposed between the outer periphery of each of said polygonal source regions and the outer periphery of its said respective base region and beneath said gate insulation layer; each of said polygonal base regions having outer sides which are parallel to respective sides of adjacent ones of said plurality of polygonal base regions; said parallel sides being laterally spaced from one another by respective common regions which are centrally disposed beneath said gate insulation layer and which are of said one of the conductivity types; a relatively high resistivity region of said one of the conductivity types underlying said common regions and being continuous with said common regions; said common regions having a substantially higher conductivity than said underlying region; said common regions and said underlying region being in series in the current path from said continuous source electrode means to said drain electrode; said parallel outer sides of said polygonal base regions being as close to one another as possible to produce a high packing density.
2. The device of claim 1, wherein the outer peripheries of each of said base regions and each of said source regions are hexagonal.
3. The device of claim 1 or 2, wherein each of said polygonal base regions has a relatively deep central region and a relatively shallow outer region;
each of said polygonal source regions being ring-shaped; each of said relatively shallow outer regions underlying their said respective ring-shaped source region.
each of said polygonal source regions being ring-shaped; each of said relatively shallow outer regions underlying their said respective ring-shaped source region.
4. A MOSFET device formed by D-MOS manufactur-ing techniques comprising, in combination:
a semiconductor chip;
a large plurality of highly packed, symmetri-cally disposed, polygonal source regions disposed on one surface of said chip and source electrode means connected to said source regions;
said chip having a bottom surface; said bottom surface having a drain electrode connected thereto;
a gate electrode disposed between said spaced source regions and disposed on an insulating layer on top of said chip;
each of the sides of each of said polygonal source regions being parallel to a respective side of an adjacent one of said polygonal source regions; said sides being as close to one another as possible to produce a high packing density;
a plurality of pairs of first and second channels disposed between said adjacent sides of each of said source regions; said pairs of first and second channels being of a first conductivity type and being capable of inversion to a second conductivity type by a gate bias;
said pairs of first and second channels having spaced outer sides which extend into respective common semiconductor regions beneath said gate insulation layer; the inner sides of said first and second channels connected to respective source electrode means; said common semiconductor region defining a current path across the thickness of said chip and having a high conductivity adjacent said surface of said chip and a low conductivity, necessary for reverse voltage withstand ability, extending to a depth greater than about 1 micron below said surface, whereby said high conductivity region of said common region substantially decreases the on-resistance of said device.
a semiconductor chip;
a large plurality of highly packed, symmetri-cally disposed, polygonal source regions disposed on one surface of said chip and source electrode means connected to said source regions;
said chip having a bottom surface; said bottom surface having a drain electrode connected thereto;
a gate electrode disposed between said spaced source regions and disposed on an insulating layer on top of said chip;
each of the sides of each of said polygonal source regions being parallel to a respective side of an adjacent one of said polygonal source regions; said sides being as close to one another as possible to produce a high packing density;
a plurality of pairs of first and second channels disposed between said adjacent sides of each of said source regions; said pairs of first and second channels being of a first conductivity type and being capable of inversion to a second conductivity type by a gate bias;
said pairs of first and second channels having spaced outer sides which extend into respective common semiconductor regions beneath said gate insulation layer; the inner sides of said first and second channels connected to respective source electrode means; said common semiconductor region defining a current path across the thickness of said chip and having a high conductivity adjacent said surface of said chip and a low conductivity, necessary for reverse voltage withstand ability, extending to a depth greater than about 1 micron below said surface, whereby said high conductivity region of said common region substantially decreases the on-resistance of said device.
5. The MOSFET device of claim 4, wherein said first and second channels are the end regions of respective, relative-ly deep regions which extend away from one another and which have large outer radii of curvature.
6. The device of claim 4 or 5, wherein said source regions are hexagonal.
7. The device of claim 1, wherein there are in excess of about 1,000 polygonal source regions each having a width of about 1 mil.
8. The device of claim 7, wherein there are in excess of about 1,000 hexagonal source regions each having a width of about 1 mil.
9. A high power MOSFET device having a large number of parallel-connected individual FET devices closely packed into a relatively small area comprising: a thin wafer of monocrystalline semiconductor material having first and second spaced, parallel surfaces; at least a first portion of the thickness of said water which extends from said first surface having a resistivity of a value characterized by a lightly doped epitaxially deposited region of one of the conductivity types;
a plurality of symmetrically disposed, laterally distributed hexagonal regions having a conductivity type opposite that of said one type, each extending into said first portion of said wafer for given depths and extending to said first surface; said hexagonal regions spaced from one another by a symmetric hexagonal lattice of the material of said first portion;
each side of each of said hexagonal regions being parallel to and adjacent the side of another of said hexagonal regions;
a respective hexagonal annular source region of said one of the conductivity types formed in the outer peripheral regions of said each of said hexagonal regions and extending downwardly from said first surface;
the outer rim of each of said annular source regions being annularly spaced from the outer periphery of its said respective hexagonal region to form an annular channel between each of said annular source regions and the adjacent said hexagonal lattice of the material of said first portion of said wafer which is disposed between said hexagonal regions;
a single common source electrode formed in said first surface and connected to each of said source regions;
a single drain electrode connected to said second surface of said wafer;
an insulation layer means on said first surface and overlying said hexagonal lattice of material disposed between said hexagonal regions and said annular channels; and a gate electrode atop said insulation layer means and operable to control the formation of an inversion layer in said annular channels.
a plurality of symmetrically disposed, laterally distributed hexagonal regions having a conductivity type opposite that of said one type, each extending into said first portion of said wafer for given depths and extending to said first surface; said hexagonal regions spaced from one another by a symmetric hexagonal lattice of the material of said first portion;
each side of each of said hexagonal regions being parallel to and adjacent the side of another of said hexagonal regions;
a respective hexagonal annular source region of said one of the conductivity types formed in the outer peripheral regions of said each of said hexagonal regions and extending downwardly from said first surface;
the outer rim of each of said annular source regions being annularly spaced from the outer periphery of its said respective hexagonal region to form an annular channel between each of said annular source regions and the adjacent said hexagonal lattice of the material of said first portion of said wafer which is disposed between said hexagonal regions;
a single common source electrode formed in said first surface and connected to each of said source regions;
a single drain electrode connected to said second surface of said wafer;
an insulation layer means on said first surface and overlying said hexagonal lattice of material disposed between said hexagonal regions and said annular channels; and a gate electrode atop said insulation layer means and operable to control the formation of an inversion layer in said annular channels.
10. The MOSFET device of claim 9, wherein said gate electrode is of polysilicon material.
11. The MOSFET device of claim 9, which includes more than 1,000 individual parallel-connected devices formed in said wafer, each of which occupies a total lateral area having a diameter less than about 1 mil. and are spaced from one another by about 0.6 mil.
12. The MOSFET device of claim 9, 10 or 11, wherein the portions of said hexagonal lattice which extend from said first surface for a depth less than the depth of said hexagonal regions have a relatively high conductivity compared to the conductivity of said first portion of said wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000389973A CA1136291A (en) | 1978-10-13 | 1981-11-12 | Plural polygon source pattern for mosfet |
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US95131078A | 1978-10-13 | 1978-10-13 | |
| US951,310 | 1978-10-13 | ||
| US3866279A | 1979-05-14 | 1979-05-14 | |
| US38,662 | 1979-05-14 | ||
| CA337,182A CA1123119A (en) | 1978-10-13 | 1979-10-09 | Plural polygon source pattern for mosfet |
| CA000389973A CA1136291A (en) | 1978-10-13 | 1981-11-12 | Plural polygon source pattern for mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1136291A true CA1136291A (en) | 1982-11-23 |
Family
ID=26715426
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA337,182A Expired CA1123119A (en) | 1978-10-13 | 1979-10-09 | Plural polygon source pattern for mosfet |
| CA000389973A Expired CA1136291A (en) | 1978-10-13 | 1981-11-12 | Plural polygon source pattern for mosfet |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA337,182A Expired CA1123119A (en) | 1978-10-13 | 1979-10-09 | Plural polygon source pattern for mosfet |
Country Status (19)
| Country | Link |
|---|---|
| JP (2) | JP2622378B2 (en) |
| AR (1) | AR219006A1 (en) |
| BR (1) | BR7906338A (en) |
| CA (2) | CA1123119A (en) |
| CH (2) | CH660649A5 (en) |
| CS (1) | CS222676B2 (en) |
| DE (2) | DE2954481C2 (en) |
| DK (3) | DK157272C (en) |
| ES (1) | ES484652A1 (en) |
| FR (1) | FR2438917A1 (en) |
| GB (1) | GB2033658B (en) |
| HU (1) | HU182506B (en) |
| IL (1) | IL58128A (en) |
| IT (1) | IT1193238B (en) |
| MX (1) | MX147137A (en) |
| NL (1) | NL175358C (en) |
| PL (1) | PL123961B1 (en) |
| SE (2) | SE443682B (en) |
| SU (1) | SU1621817A3 (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5592026A (en) * | 1993-12-24 | 1997-01-07 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Integrated structure pad assembly for lead bonding |
| US5631476A (en) * | 1994-08-02 | 1997-05-20 | Sgs-Thomson Microelectronics S.R.L. | MOS-technology power device chip and package assembly |
| US5663080A (en) * | 1991-11-29 | 1997-09-02 | Sgs-Thomson Microelectronics, S.R.L. | Process for manufacturing MOS-type integrated circuits |
| US5723349A (en) * | 1994-01-27 | 1998-03-03 | Consorzio Pre La Ricerca Sulla Microelettronica Nel Mezzogiorno | Process for manufacturing a high conductivity insulated gate bipolar transistor integrater structure |
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| US4593302B1 (en) * | 1980-08-18 | 1998-02-03 | Int Rectifier Corp | Process for manufacture of high power mosfet laterally distributed high carrier density beneath the gate oxide |
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| US4532534A (en) * | 1982-09-07 | 1985-07-30 | Rca Corporation | MOSFET with perimeter channel |
| DE3346286A1 (en) * | 1982-12-21 | 1984-06-28 | International Rectifier Corp., Los Angeles, Calif. | High-power metal-oxide field-effect transistor semiconductor component |
| JPS59167066A (en) * | 1983-03-14 | 1984-09-20 | Nissan Motor Co Ltd | Vertical type metal oxide semiconductor field effect transistor |
| JPS6010677A (en) * | 1983-06-30 | 1985-01-19 | Nissan Motor Co Ltd | Vertical mos transistor |
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| IT1247293B (en) * | 1990-05-09 | 1994-12-12 | Int Rectifier Corp | POWER TRANSISTOR DEVICE PRESENTING AN ULTRA-DEEP REGION, AT A GREATER CONCENTRATION |
| US5404040A (en) * | 1990-12-21 | 1995-04-04 | Siliconix Incorporated | Structure and fabrication of power MOSFETs, including termination structures |
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| JP4845293B2 (en) * | 2000-08-30 | 2011-12-28 | 新電元工業株式会社 | Field effect transistor |
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| US10115815B2 (en) | 2012-12-28 | 2018-10-30 | Cree, Inc. | Transistor structures having a deep recessed P+ junction and methods for making same |
| JP5907097B2 (en) * | 2013-03-18 | 2016-04-20 | 三菱電機株式会社 | Semiconductor device |
| US9508596B2 (en) | 2014-06-20 | 2016-11-29 | Vishay-Siliconix | Processes used in fabricating a metal-insulator-semiconductor field effect transistor |
| US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
| CN106575666B (en) | 2014-08-19 | 2021-08-06 | 维西埃-硅化物公司 | Super junction metal oxide semiconductor field effect transistor |
| US11489069B2 (en) | 2017-12-21 | 2022-11-01 | Wolfspeed, Inc. | Vertical semiconductor device with improved ruggedness |
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| US4015278A (en) * | 1974-11-26 | 1977-03-29 | Fujitsu Ltd. | Field effect semiconductor device |
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- 1979-08-28 IL IL58128A patent/IL58128A/en unknown
- 1979-09-25 AR AR278193A patent/AR219006A1/en active
- 1979-09-28 MX MX179453A patent/MX147137A/en unknown
- 1979-09-28 CS CS796589A patent/CS222676B2/en unknown
- 1979-10-02 ES ES484652A patent/ES484652A1/en not_active Expired
- 1979-10-02 BR BR7906338A patent/BR7906338A/en not_active IP Right Cessation
- 1979-10-08 DE DE19792954481 patent/DE2954481C2/en not_active Expired - Lifetime
- 1979-10-08 DE DE2940699A patent/DE2940699C2/en not_active Expired
- 1979-10-09 CA CA337,182A patent/CA1123119A/en not_active Expired
- 1979-10-09 GB GB7935059A patent/GB2033658B/en not_active Expired
- 1979-10-09 NL NLAANVRAGE7907472,A patent/NL175358C/en not_active IP Right Cessation
- 1979-10-09 FR FR7925070A patent/FR2438917A1/en active Granted
- 1979-10-11 HU HU79IE891A patent/HU182506B/en not_active IP Right Cessation
- 1979-10-11 PL PL1979218878A patent/PL123961B1/en unknown
- 1979-10-11 IT IT26435/79A patent/IT1193238B/en active
- 1979-10-11 SU SU792835965A patent/SU1621817A3/en active
- 1979-10-12 CH CH7696/81A patent/CH660649A5/en not_active IP Right Cessation
- 1979-10-12 SE SE7908479A patent/SE443682B/en not_active IP Right Cessation
- 1979-10-12 CH CH923279A patent/CH642485A5/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5663080A (en) * | 1991-11-29 | 1997-09-02 | Sgs-Thomson Microelectronics, S.R.L. | Process for manufacturing MOS-type integrated circuits |
| US5696399A (en) * | 1991-11-29 | 1997-12-09 | Sgs-Thomson Microelectronics S.R.L. | Process for manufacturing MOS-type integrated circuits |
| US5888889A (en) * | 1993-12-24 | 1999-03-30 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Integrated structure pad assembly for lead bonding |
| US5798287A (en) * | 1993-12-24 | 1998-08-25 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Method for forming a power MOS device chip |
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| US5592026A (en) * | 1993-12-24 | 1997-01-07 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Integrated structure pad assembly for lead bonding |
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| US5817546A (en) * | 1994-06-23 | 1998-10-06 | Stmicroelectronics S.R.L. | Process of making a MOS-technology power device |
| US5874338A (en) * | 1994-06-23 | 1999-02-23 | Sgs-Thomson Microelectronics S.R.L. | MOS-technology power device and process of making same |
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| US5798554A (en) * | 1995-02-24 | 1998-08-25 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS-technology power device integrated structure and manufacturing process thereof |
| US6111297A (en) * | 1995-02-24 | 2000-08-29 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS-technology power device integrated structure and manufacturing process thereof |
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| US6030870A (en) * | 1995-10-30 | 2000-02-29 | Sgs-Thomson Microelectronics, S.R.L. | High density MOS technology power device |
| US5985721A (en) * | 1995-10-30 | 1999-11-16 | Sgs-Thomson Microelectronics, S.R.L. | Single feature size MOS technology power device |
| US5981343A (en) * | 1995-10-30 | 1999-11-09 | Sgs-Thomas Microelectronics, S.R.L. | Single feature size mos technology power device |
| US6064087A (en) * | 1995-10-30 | 2000-05-16 | Sgs-Thomson Microelectronics, S.R.L. | Single feature size MOS technology power device |
| US6566690B2 (en) | 1995-10-30 | 2003-05-20 | Sgs Thomson Microelectronics S.R.L. | Single feature size MOS technology power device |
| US6468866B2 (en) | 1995-10-30 | 2002-10-22 | Sgs-Thomson Microelectronics S.R.L. | Single feature size MOS technology power device |
| US5981998A (en) * | 1995-10-30 | 1999-11-09 | Sgs-Thomson Microelectronics S.R.L. | Single feature size MOS technology power device |
| US6548864B2 (en) | 1995-10-30 | 2003-04-15 | Sgs Thomson Microelectronics | High density MOS technology power device |
| US6228719B1 (en) | 1995-11-06 | 2001-05-08 | Stmicroelectronics S.R.L. | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
| US6051862A (en) * | 1995-12-28 | 2000-04-18 | Sgs-Thomson Microelectronics S.R.L. | MOS-technology power device integrated structure |
| US5841167A (en) * | 1995-12-28 | 1998-11-24 | Sgs-Thomson Microelectronics S.R.L. | MOS-technology power device integrated structure |
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