JP4845293B2 - Field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect transistor, and more particularly, to a high withstand voltage low resistance field effect transistor.
[0002]
[Prior art]
Conventionally, a field effect transistor that allows current to flow in the thickness direction of a substrate has been used as a power control element.
[0003]
Referring to FIG. 26, reference numeral 105 is an example of a conventional field effect transistor, and includes a silicon single crystal substrate 111. A drain region 112 formed by epitaxial growth is disposed on the surface of the single crystal substrate 111.
[0004]
The silicon single crystal substrate 111 is doped with N-type impurities at a high concentration, and a drain electrode film 148 is formed on the back surface thereof. The drain region 112 is doped with an N-type impurity at a low concentration, and a P-type base region 154 is formed in the vicinity of the surface thereof.
[0005]
In the base region 154, an N-type impurity is further diffused from the surface to form a source region 161.
[0006]
Reference numeral 110 denotes a channel region located between the edge portion of the source region 161 and the edge portion of the base region 154. A gate insulating film 126 and a gate electrode film 127 are arranged in this order on the channel region 110.
[0007]
An interlayer insulating film 141 is formed on the surface and side surfaces of the gate electrode film 127, and a source electrode film 144 is disposed on the surface.
[0008]
The base region 154 as described above is arranged in an island shape in the vicinity of the surface of the drain region 112, and includes one base region 154, and a source region 161 and a channel region 110 disposed in the base region 154. One cell 101 is formed.
[0009]
FIG. 27 is a plan view showing the surface of the drain region 112, in which a plurality of rectangular cells 101 are arranged in a matrix.
[0010]
When this field effect transistor 105 is used, when the source electrode film 144 is placed at the ground potential, a positive voltage is applied to the drain electrode film 148, and a gate voltage (positive voltage) higher than the threshold voltage is applied to the gate electrode film 127, An N-type inversion layer is formed on the surface of the P-type channel region 110, the source region 161 and the conductive region 112 are connected by the inversion layer, and the field-effect transistor 105 becomes conductive.
[0011]
When a voltage lower than the threshold voltage (for example, ground potential) is applied to the gate electrode film 127 from this state, the inversion layer disappears and the field effect transistor 105 is cut off.
[0012]
However, when a large number of the cells 101 are arranged as described above, if the breakdown voltage is increased, the distance between the cells 101 is reduced and the gate electrode width is reduced, so that the conduction resistance is increased.
[0013]
Further, the withstand voltage is determined at the corners of the cells 101, and there is a problem that the withstand voltage is not improved as expected even if the distance between the cells 101 is reduced.
[0014]
[Problems to be solved by the invention]
The present invention was created in order to solve the above-described disadvantages of the prior art, and an object thereof is to provide a field effect transistor having a high breakdown voltage and a low resistance.
[0015]
[Means for Solving the Problems]
  In order to solve the above-mentioned problem, the invention according to claim 1 is characterized in that the second conductivity type main diffusion region formed in the first resistance type high resistance layer and disposed on the surface side of the high resistance layer, A source region of a first conductivity type formed in the main diffusion region and disposed on a surface thereof; a part of the main diffusion region; an edge of the main diffusion region and an edge of the source region An annular channel region formed in an annular shape, a drain region surrounded by the annular channel region, a gate insulating film disposed at least on the surface of the annular channel region, and a surface of the gate insulating film The source region is disposed on the outer periphery of the annular channel region, and when the surface of the annular channel region is inverted to the first conductivity type by a voltage applied to the gate electrode film, the source region Area and said drain A field effect transistor region and is electrically connectedThe drain region has at least one elongated trunk and a plurality of elongated branches having one ends connected to the trunk, and the annular channel region includes the trunk and the branches. A trunk that surrounds the trunk and is located between the branches is bulged in a circular shape toward the inside of the trunk itself, and the main diffusion region includes a base region of a second conductivity type, A second conductivity type ohmic region having a diffusion depth deeper than that of the base region, and the portion of the trunk that is bulged in a circular shape has an inner circumference of the ohmic region rather than an inner circumference of the base region. Enters the drain region, and the ohmic region and the drain region form a pn junction.It is a field effect transistor.
  Claim2The described invention is claimed.1The field effect transistor according to claim 1, wherein the annular channel region at the tip of the branch isBend almost at right angles to form three sides of the rectangleThis is a configured field effect transistor.
  Claim3The invention described in claim 1 has a conductive layer of a first conductivity type having a resistance lower than that of the high resistance layer on the surface side inside the drain region.OrClaim2The field effect transistor according to any one of the above.
  Claim4The invention according to any one of claims 1 to 3, wherein a floating potential region of a second conductivity type that is not in contact with the channel region is disposed on a surface side inside the drain region.3The field effect transistor according to any one of the above.
  Claim5In the described invention, a low resistance layer having a first conductivity type and lower resistance than the high resistance layer is disposed on a back surface side of the high resistance layer, and the surface of the low resistance layer includes the low resistance layer and the low resistance layer. The drain electrode film for forming an ohmic junction is disposed.4The field effect transistor according to any one of the above.
  Claim6In the described invention, an anode electrode film that forms a Schottky junction with the high-resistance layer is disposed on the back surface of the high-resistance layer, and a diode having the anode electrode film as an anode and the high-resistance layer as a cathode is provided. Claims 1 to Claims formed4The field effect transistor according to any one of the above.
  Claim7In the described invention, a collector layer of a second conductivity type is disposed on the back side of the high resistance layer, and a collector electrode film that forms an ohmic junction with the collector layer is disposed on the surface of the collector layer. Claims 1 to4The field effect transistor according to any one of the above.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
The field effect transistor of the present invention will be described with reference to the drawings.
Referring to FIGS. 20A and 20B, reference numeral 1 denotes a field effect transistor according to a first example of the present invention. FIG. 20A and FIG. 20B are cross-sectional views of the field effect transistor 1 in directions perpendicular to each other.
[0017]
The field effect transistor 1 has a substrate 9 which is a silicon wafer. The substrate 9 includes a low resistance layer 11 made of a silicon single crystal to which impurities are added at a relatively high concentration, and a high resistance layer 12 that is grown on the low resistance layer 11 by an epitaxial method and has a relatively high resistance. It is configured.
[0018]
A relatively high concentration N-type conductive layer 26 is disposed on the surface side of the substrate 9 in the high resistance layer 12 as shown in FIG. The planar shape of the conductive layer 26 is comb-like, and a P-type channel region 40 is located in the vicinity of the outer peripheral surface.
[0019]
An N-type source region 39 is located on the surface side inside the substrate 9 on the outer periphery of the channel region 40. The source region 39 is formed in a P-type region communicating with the channel region 40. When the vicinity of the surface of the channel region 40 is inverted to N-type, the source region 39 and the conductive layer 26 are electrically connected. It has become so. The source region 39 is in contact with the channel region 40 and surrounds the channel region 40.
[0020]
The manufacturing process of this field effect transistor will be described. Referring to FIGS. 1A to 1C, first, a substrate 9 in which an N-type low resistance layer 11 and an N-type high resistance layer 12 are laminated is prepared. After partially injecting P-type impurities and diffusing to form P-type first and second guard ring regions 13 and 14 and a floating potential region 15, a silicon oxide film is formed on the surface, The field insulating film 16 is formed by patterning. FIGS. 1A to 1C show the substrate 9 in that state. FIG. 1A is a plan view of the surface of the high resistance layer 12 of the substrate 9, and FIG. 9 is a cross-sectional view taken along the line AA of FIG. 9, and FIG. 1C is a cross-sectional view taken along the line BB.
[0021]
The first and second guard ring regions 13 and 14 and the floating potential region 15 are diffused to the same depth, and their bottom surfaces are not in contact with the low resistance layer 11. The second guard ring region 14 is connected to a source electrode film, which will be described later, and has the same potential as that of the source region. The first guard ring region 13 and the floating potential region 15 are formed of a source electrode film or a gate electrode film. Is not connected to, but is placed at a floating potential.
[0022]
The first and second guard ring regions 13 and 14 each have a ring shape, the first guard ring region 13 is disposed on the outer periphery of the substrate, and the second guard ring region 14 is the first guard ring. It is arranged inside the region 13.
[0023]
Reference numeral 17 denotes an edge portion of a region in which one field effect transistor is formed in the substrate 9. A plurality of field effect transistors are formed in the substrate 9 and are separated from each other at positions outside the edge portion 17 in the dicing process.
[0024]
The first and second guard ring regions 13 and 14 are disposed in the vicinity of the edge portion 17, and the inner side of the second guard ring region 14 is an active region in which a base region, a source region, and the like, which will be described later, are disposed. It has become.
[0025]
The floating potential region 15 has an elongated rectangular shape, and the floating potential region 15 is disposed in the active region inside the second guard ring region 14. Here, two floating potential regions 15 are provided, and are arranged in parallel at positions separated from each other.
[0026]
The field insulating film 16 is divided into a portion that covers the surface of the floating potential region 15 and a portion that covers the surface of the first guard ring region 13 and the partial surface of the second guard ring region 14.
[0027]
The field insulating film 16 has a pad portion 27 formed in a large area, and a gate pad described later is formed on the pad portion 27.
[0028]
Next, when the field insulating film 16 is used as a mask and the surface of the substrate 9 is irradiated with an N-type impurity, the impurity is implanted into the surface of the high resistance layer 12. FIG. 2A is a plan view of the surface of the high-resistance layer 12 in this state, and reference numeral 18 indicates a high-concentration impurity layer formed by implantation of N-type impurities. Since the field insulating film 16 is disposed on the surfaces of the first guard ring diffusion region 13 and the floating potential region 15, the high concentration impurity layer 18 is not formed there.
[0029]
FIGS. 2B and 2C are a cross-sectional view taken along line AA and a cross-sectional view taken along line BB in FIG. 2A, respectively.
[0030]
Since the concentration of the N-type impurity is lower than the surface concentration of the second guard ring region 14, the surface of the second guard ring region 14 is not N-type. Therefore, the high concentration impurity layer 18 is located in the active region inside the second guard ring region 14.
[0031]
Next, when the surface of the substrate 9 is oxidized by a thermal oxidation method, as shown in FIGS. 3A to 3C, the inner peripheral surface portion of the second guard ring region 14 and the surface of the high concentration impurity layer 18 are formed. A gate insulating film 19 made of an oxide film is formed.
[0032]
3B and 3C are a cross-sectional view taken along line AA and a cross-sectional view taken along line BB in FIG. 3A, respectively.
[0033]
A polysilicon thin film is formed on the entire surface of the substrate 9 in this state by CVD, followed by patterning to form a gate electrode film. Reference numerals 21a and 21b in FIGS. 4A to 4C denote the gate electrode films, which are separated into two.
[0034]
Of the two gate electrode films 21 a and 21 b, one gate electrode film 21 a is located in the active region inside the second guard ring region 14 and is disposed on the gate insulating film 19. This portion of the gate electrode film 21a has two elongated portions 22 each formed in an elongated shape.₁, 22₂And one connecting portion 23 and a plurality of branch portions 24.
[0035]
Two executives 22₁, 22₂Are arranged in parallel to each other, and a connecting portion 23 is connected to one end thereof. Each executive 22₁, 22₂The ends of the plurality of branch portions 24 are connected to the. The connecting portion 23 and each branch portion 24 are the trunk portion 22.₁, 22₂Is perpendicular to.
[0036]
Executive 22₁, 22₂Is disposed on the field insulating film 16 located in the active region inside the second guard ring region 14. Therefore, executive 22₁, 22₂The floating potential regions 15 are located below the respective regions.
[0037]
The other gate electrode film 21 b is disposed on the field insulating film 16 near the outer periphery, and is formed in a ring shape so as to surround the active region inside the field insulating film 16. The gate electrode film 21 b is formed on a large area on the pad portion 27 of the field insulating film 16.
[0038]
Next, when the gate insulating film 19 is etched using the gate electrode film 21a disposed on the gate insulating film 19 as a mask, the gate insulating film 19 becomes a gate as shown in FIGS. 5 (a) and 5 (b). It is patterned in the same planar shape as the electrode film 21a. The plan view is omitted in FIG. 5 and FIGS.
[0039]
Next, when the high-concentration impurity layer 18 is diffused by heat treatment, a conductive layer 26 as shown in FIGS. 6A and 6B is formed. The conductive layer 26 has the same conductivity type as the high resistance layer 12, but has a lower resistance than the high resistance layer 12 because the impurity concentration is higher than that of the high resistance layer 12.
[0040]
Since the high-concentration impurity layer 18 is also disposed below the gate insulating film 19, the conductive layer 26 excludes the portion where the floating potential region 15 in the active region inside the second guard ring region 14 is located. Formed in the region.
[0041]
After the formation of the conductive layer 26, the surface of the substrate 9 is irradiated with P-type impurities. Since impurities do not pass through the gate electrode films 21a and 21b and the field insulating film 16, the gate electrode film 21a serves as a mask inside the field insulating film 16, and the surface of the inner peripheral portion of the second guard ring region 14 and the conductive layer The impurity is implanted into the portion where 26 is exposed.
[0042]
As a result, as shown in FIGS. 7A and 7B, a P-type high concentration impurity layer 28 is formed around the gate insulating film 19. That is, the gate insulating film 19, the gate electrode film 21 a on the surface thereof, and the conductive layer 26 immediately below the gate insulating film 19 are surrounded by the high concentration impurity layer 28.
[0043]
Next, when the high-concentration impurity layer 28 is diffused by heat treatment, as shown in FIGS. 8A and 8B, a P-type base region 29 is formed. The outer peripheral portion of the base region 29 is connected to the second guard ring layer 14.
[0044]
Since the high-concentration impurity layer 28 also diffuses in the lateral direction, the inner peripheral end portion of the base region 29 sinks below the outer peripheral end portion of the gate insulating film 19.
[0045]
Next, as shown in FIGS. 9A to 9C, a patterned resist film 31 is formed on the surface of the substrate, and on the surfaces of the gate electrode films 21a and 21b and in the vicinity of the gate electrode film 21a in the active region. The surface of the base region 29 is covered.
[0046]
In this state, the surface of the base region 29 is partially exposed on the substrate, and when the surface of the substrate 9 in that state is irradiated with P-type impurities, as shown in FIGS. Then, impurities are implanted into the exposed portion of the base region 29, and a P-type high concentration impurity layer 32 is formed.
[0047]
Next, after removing the resist film 31 and performing a heat treatment to diffuse the P-type high concentration impurity layer 32, a P-type ohmic region 33 is formed as shown in FIGS. 11 (a) and 11 (b). The The ohmic region 33 is of the second conductivity type, like the base region 29, is connected to the base region 29, and the base region 29 and the ohmic region 33 constitute a main diffusion region.
[0048]
The ohmic region 33 is separated from the gate electrode film 21 a and the gate oxide film 19 by substantially the width of the resist film 31.
[0049]
The bottom of the ohmic region 33 is located in the conductive layer 26, but is diffused to a position deeper than the bottom of the base region 29.
[0050]
The surface concentration of the ohmic region 33 is higher than the surface concentration of the base region 29, and a source electrode film, which will be described later, is ohmically connected to the ohmic region 33. As a result, the base region 29 has a low resistance and a source electrode. It is designed to be connected to the membrane.
[0051]
Next, as shown in FIGS. 12A to 12C, a patterned resist film 35 is formed on the surface of the substrate 9, and a gate electrode film disposed on the gate insulating film 19 in the window portion 36. The surface of 21a and the region separated from the gate electrode film 21a by a predetermined distance are exposed. That is, the shape of the window 36 is a similar shape that is slightly larger than that of the gate electrode film 21a.
[0052]
The symbol w is the distance between the end portion of the gate electrode film 21 a exposed in the window portion 36 and the edge portion of the window portion 36.
[0053]
In the range of this distance w, the surface of the base region 29 and a partial surface of the ohmic region 33 are exposed.
[0054]
In this state, when the substrate is irradiated with N-type impurities, the resist film 35 and the gate electrode film 21a serve as a mask, and N-type impurities are implanted into portions not covered with them. Reference numeral 38 in FIGS. 13A and 13B denotes an N-type high concentration impurity layer formed by the impurity implantation.
[0055]
The N-type high concentration impurity layer 38 is disposed in the vicinity of the surfaces inside the base region 29 and the ohmic region 33.
[0056]
Next, after removing the resist film 35 and performing heat treatment to diffuse the high-concentration impurity layer 38, an N-type source region 39 is formed as shown in FIGS. 14 (a) and 14 (b). The gate electrode film 21 a on the gate insulating film 19 is formed of the trunk portion 22.₁, 22₂And the connecting portion 23 and the branch portion 24 are connected to each other, and the N-type high concentration impurity layer 38 is formed around the gate electrode film 21a. The source electrode 39 surrounds the gate electrode film 21a disposed on the surface. Therefore, the entire source region 39 is continuously formed in a ring shape. In this state, the central portion of the ohmic region 33 is exposed.
[0057]
Further, due to the lateral diffusion, the end of the source region 39 on the gate insulating film 19 side, that is, the end on the inner peripheral side of the ring-shaped source region, is buried under the gate insulating film 19. It stops at a position inside 29.
[0058]
Therefore, the entire N-type source region 39 is located inside the P-type region formed by the base region 29 and the ohmic region 33.
[0059]
An outer peripheral portion of the base region 29 exists between an end portion on the inner peripheral side of the source region 39 and an edge portion of the base region 29, and the gate insulating film 19 and the gate electrode are formed on the surface of this portion. A membrane 21a is disposed.
[0060]
Reference numeral 40 denotes a base region 29 between an inner peripheral end of the source region 39 and an edge portion of the base region 29. When a positive voltage is applied to the gate electrode film 21a, the surface is inverted to N-type. Since the source region 39 and the conductive layer 26 are electrically connected, it is called a channel region.
[0061]
The channel region 40 is disposed along the edge portion of the gate electrode film 21a in the active region. Therefore, the channel region 40 has a ring shape having irregularities according to the shape of the gate electrode film 21a.
[0062]
The portion of the conductive layer 26 surrounded by the channel region 40 is the trunk portion 22 of the gate electrode film 21a.₁, 22₂, The lower position of the connecting portion 23, and the lower positions of the plurality of branch portions 24 are respectively the trunk portion 22.₁, 22₂The connection portion 23 and the branch portion 24 have the same shape as the trunk portion, the connection portion, and the branch portion. However, the size of the gate electrode is equivalent to the amount of lateral diffusion of the channel region 40 below the gate insulating film 19. It is smaller than the film 21a.
[0063]
Next, after a silicon oxide film is formed on the substrate surface by the CVD method, patterning is performed by etching to form an interlayer insulating film. Reference numeral 41 in FIGS. 15A and 15B denotes the interlayer insulating film, and three types of openings 42a, 42b, and 42c are formed.
[0064]
The three types of openings 42a, 42b, and 42c are separated from each other, and the first opening 42a is disposed in the active region inside the field insulating film 16, and the bottom surface of the ohmic region 33 is formed on the bottom surface thereof. The surface and the surface of the source region 39 are exposed.
[0065]
The second opening 42b is disposed on the gate electrode film 21b on the field insulating film 16, and the surface of the gate electrode film 21b disposed on the field insulating film 16 is exposed at the bottom surface.
[0066]
Further, the third opening 42c is formed by the trunk portion 22.₁, 22₂The surface of the gate electrode film 21a located in the active region is exposed on the bottom surface of the gate electrode film 21a.
[0067]
Next, an aluminum thin film is formed on the entire surface of the substrate 9 and patterned to form a source electrode film 45 and a gate connection film 46 as shown in FIG. The source electrode film 45 and the gate connection film 46 are separated from each other during patterning, and are electrically insulated. The surface of the interlayer insulating film 41 is exposed between the source electrode film 45 and the gate connection film 46.
[0068]
17A and 17B are cross-sectional views taken along lines AA and BB in FIG. As shown in FIGS. 17A and 17B, the source electrode film 45 is connected to the ohmic region 33 and the source region 39. Therefore, the P-type main diffusion region including the base region 29 including the channel region 40 and the ohmic region 33 and the N-type source region 39 are electrically short-circuited.
[0069]
The source electrode film 45 is disposed so as to avoid the third opening 42c, and is constricted at a portion where the opening 42c is located. The source electrode film 45 is not in contact with the gate electrode film 21a.
[0070]
A gate connection film 46 projects from the constricted portion and fills the third opening 42c. Therefore, the gate connection film 46 is formed by the trunk portion 22.₁, 22₂Is connected to the gate electrode film 21a. Reference numeral 51 denotes the executive 22.₁, 22₂A portion of the gate connection film 46 protruding upward is shown.
[0071]
The gate connection film 46 is also filled in the second opening 42b and is also connected to the gate electrode film 21b located on the bottom surface thereof. Therefore, the gate electrode films 21 a and 21 b are connected to each other by the gate connection film 46.
[0072]
The gate connection film 46 is formed in a large area on the pad portion 27 formed in a large area of the field insulating film 16, and this portion is used as a gate pad.
[0073]
Next, a silicon oxide thin film is formed on the surface of the substrate 9 (surfaces of the source electrode film 45, the gate connection film 46, and the interlayer insulating film 41) by CVD, and patterned to obtain FIGS. As shown in (b), a protective film 48 is formed. The protective film 48 has two openings. The source electrode film 45 is exposed on the bottom surface of one opening 53 to serve as a source pad, and the surface of the gate connection film 46 is exposed on the bottom surface of the other opening 54. When the gate pad is used, in a later step, one end of a thin metal wire is connected to the source pad and the gate pad respectively, and the other end is connected to the lead so that the source electrode film 45 and the gate electrode film 21a can be connected to an external circuit. become.
[0074]
After the formation of the protective film 48, a metal film that forms an ohmic junction with the low resistance layer 11 is formed on the surface of the low resistance layer 11 exposed on the back side of the substrate 9, and FIGS. 20 (a) and 20 (b). As shown, when the drain electrode film 49 is used, the field effect transistor 1 of the present invention is obtained.
[0075]
A plurality of field effect transistors 1 are formed in one silicon wafer, and each field effect transistor 1 is separated in a dicing process, which is a subsequent process.
[0076]
FIG. 21A shows the relative positional relationship between the source region 39, the channel region 40, and the conductive layer 26 of the field effect transistor 1 of the present invention. A portion surrounded by the channel region 40 is a drain region, and the trunk portion 22 in the drain region.₁, 22₂As shown in FIG. 21 (b), the floating potential region 15 is disposed at a lower position of.
[0077]
In the field effect transistor 1, when a positive voltage higher than the threshold voltage is applied to the gate electrode film 21a in a state where the source electrode film 45 is connected to the ground potential and a positive voltage is applied to the drain electrode film 49, the P-type An N-type inversion layer is formed on the surface of the channel region 40, the drain region and the source region 39 are connected by the inversion layer, and the field effect transistor 1 becomes conductive.
[0078]
When the gate electrode film 21a is connected to the ground potential from the conductive state, the inversion layer disappears and the field effect transistor 1 is cut off.
[0079]
In a state where the source electrode film 45 is connected to the ground potential and a positive voltage is applied to the drain electrode film 49, the channel region 40, the base region 29, the ohmic region 33, and the second guard ring region 14 are included. The PN junction between the P-type main diffusion region and the N-type conductive layer 26 and the high resistance layer 12 is reverse-biased, and the depletion layer extends toward the conductive layer 26 side. That is, the depletion layer extends toward the inside of the drain region surrounded by the channel region 40.
[0080]
As described above, the trunk portion 22 of the gate electrode film 21a.₁, 22₂A floating potential region 15 is disposed at the lower position as shown in FIG. Both ends of the floating potential region 15 are not in contact with the channel region 40 and are placed at a floating potential.
[0081]
The first guard ring region 13 is also placed at a floating potential, and the floating potential diffusion layer 15 extends the surface of the depletion layer in which the first guard ring region 13 is formed in the high resistance layer 12. Similarly, the depletion layer formed in the conductive layer 26 is extended to improve the breakdown voltage.
[0082]
In the above embodiment, the N-type impurity for forming the conductive layer 26 is formed on the entire surface of the substrate 9 except for the portion where the field insulating film 16 is disposed, as shown in FIGS. The high concentration impurity layer 18 was formed, and the conductive layer 26 was formed by diffusion of the high concentration impurity layer 18.
[0083]
Therefore, in the field effect transistor 1 of the above embodiment, the conductive layer 26 is entirely disposed on the inner surface side of the drain region inside the channel region 40. However, the field effect transistor of the present invention has the same Without being limited thereto, the conductive layer 26 can be partially disposed on the surface side inside the drain region.
[0084]
For example, when an N-type high-concentration impurity is implanted, a patterned resist mask is placed and selectively implanted on the surface of the high-resistance layer 12, so that the N-type high-concentration impurity layer 18 is transferred to the channel region 40. Can be partially formed in the drain region surrounded by the ring.
[0085]
FIG. 22 is a diagram showing the positional relationship between the channel region 40 and the conductive layer 26 in that case. In the vicinity of the corner portion 55 of the channel region 40 protruding inside the drain region, the conductive layer 26 is not disposed, and the surface of the high resistance layer 12 is exposed. Accordingly, since a PN junction is formed between the channel region 40 and the high resistance layer 12 at the corner portion 55, when the PN junction is reverse-biased, the corner portion 55 faces into the high resistance layer 12. The depletion layer is easy to grow. Therefore, the breakdown voltage is increased in the field effect transistor having this structure.
[0086]
Next, a field effect transistor having a higher breakdown voltage will be described.
The field effect transistor has the same structure as the field effect transistor 1 as shown in FIG. 23, and the difference is the planar shape of the gate insulating film in the active region and the gate electrode film.
[0087]
Each diffusion layer and thin film is formed in the same process as the above process. Therefore, when the same reference numeral is given, the reference numeral 70 is surrounded by the source region 39 and the channel region 40 that form a double ring, and the channel region 40. The planar shape formed by the high resistance layer 12, the conductive layer 26, and the floating potential region 15 is shown.
[0088]
The planar shape of the portion surrounded by the channel region 40 in the N-type region formed by the high-resistance layer 12 and the conductive layer 26 is the same as that of the above-described embodiment.₁, 22₂And a single connection portion 23 and a plurality of branch portions 24. Executive 22₁, 22₂Among these, between the branch portions 24, the channel region 40 bulges toward the inside of the N-type region surrounded by the channel region 40, and a bulge portion 71 is formed.
[0089]
Therefore, the pn junction formed by the channel region 40 and the N-type region is bent more gently than the spherical junction in this portion 71, and a breakdown voltage larger than the avalanche breakdown voltage of the spherical junction can be obtained. Yes.
[0090]
On the other hand, at the distal end portion 72 of the branch portion 24, the three sides 75a, 76, 75b of the surface of the conductive layer 26 constituting the branch portion 24 intersect at right angles. That is, at the tip portion 72, the channel region 40 is bent at a right angle, and therefore the surface portion of the pn junction formed by the channel region 40 and the conductive layer 26 is also bent at a right angle.
[0091]
In the tip portion 72, the depletion layer extends inside the conductive layer 26. Therefore, the avalanche breakdown voltage is larger than that of the cylindrical junction even at the two apexes 77a and 77b formed by the intersections of the three sides 75a, 76, and 75b. It has become.
[0092]
The conductive layer 26 is disposed from the distal end portion 72 of each branch portion 24 to the vicinity of the bulging portion 71, and is not disposed near the bulging portion 71. Accordingly, since the channel region 40 and the high resistance layer 12 form a pn junction in the bulging portion 71, the depletion layer tends to spread toward the high resistance layer 12 and the avalanche breakdown voltage is high.
[0093]
Further, in the planar shape 70, the tip portion 72 of the branch portion 24 protruding toward the inside of the region surrounded by the source region 39 is not semi-circular but rectangular, so that the length of the channel region 40 is increased. However, it is longer than the semicircular shape and the conduction resistance is low.
[0094]
Reference numeral 80 in FIG. 24 denotes the surface of the substrate 9 in a state where thin films such as a source electrode film, a gate electrode film, and a silicon oxide film are omitted, and shows a planar shape when the tip of the branch portion 24 is made semicircular. ing. Reference numeral 73 denotes a circular portion. If the radius of the circular portion 73 is R, the channel width of the circular portion 73 is π × R, whereas the channel length is 4 × R at the tip portion 72 of the planar shape 70 in FIG. The tip of the branch part 24 is better if it is rectangular.
[0095]
In the above embodiment, the distance between the inner peripheral edge of the base region 33 and the inner peripheral edge of the ohmic region 33 is constant, but the present invention is not limited thereto. For example, a field effect transistor having a structure in which a part of the inner peripheral edge of the ohmic region 33 projects beyond the inner periphery of the base region 32 and protrudes into an N-type region surrounded by the channel region 40 is also included.
[0096]
Reference numeral 81 in FIG. 28 denotes a planar shape of the example, and thin films such as a source electrode film, a gate electrode film, and a silicon oxide film, and the first and second guard ring regions 13 and 14 are omitted. In the planar shape 81, the structure in the depth direction of the substrate 9 is the same as in each of the above embodiments except that the ohmic region 33 has a different planar shape. The same reference numerals are attached.
[0097]
Reference numeral 88 in FIG. 28 denotes a bulging portion protruding toward the inside of the N-type region surrounded by the channel region 40. The bulging portion is formed into a semicircular shape, and the semicircular bulging portion. The ohmic region 33 which is a part of 88 is wider than the width of the ohmic region 33 of the other part.
[0098]
That is, in this planar shape, the ohmic region 33 of the bulging portion 88 is more inside the N-type region surrounded by the channel region 40 than the ohmic region 33 located between the straight portions of the branch portions 24. The edge of the ohmic region 33 of the bulging portion 88 extends toward the inside of the N-type region at least beyond the inner peripheral edge of the source region 39.
[0099]
The shape other than the bulging portion 88 is the same as that of the field effect transistor 1 of the first embodiment. Accordingly, the drawings for explaining the manufacturing process of the CC line disconnection surface of the side portion of the branch portion 24 constituting the planar shape 81 are the manufacture of the portion of the AA line sectional view of FIGS. It is the same as the drawing for explaining the process.
[0100]
The procedure for forming the planar shape 81 will be described. First, the state in which the P-type first and second guard ring regions 13 and 14 are formed on the surface side of the high resistance layer 12 of the substrate 9 is C−. A section taken along the line C is shown in FIG. 1 (b), and a section taken along the line DD is shown in FIG. 34 (a). In this state, a floating potential region 15 is formed in a portion corresponding to the portion of FIG.
[0101]
34 to 39 are process diagrams for explaining a part of the sectional view taken along the line DD.
From this state, as shown in FIGS. 2B and 34B, an N-type high concentration impurity layer 18 is formed in the vicinity of the surface inside the high resistance layer 12, and FIGS. 3B and 34B are formed. As shown in c), a gate insulating film 19 is formed by a thermal oxidation method.
[0102]
Next, as shown in FIGS. 4B and 35A, gate electrode films 21a and 21b made of a patterned polysilicon thin film are formed on the surface of the gate insulating film 19, and then the gate electrode film 21a is formed. 21b as masks, as shown in FIGS. 5A and 35B, after the gate insulating film 19 is etched, the high-concentration impurity layer 18 is diffused, and FIGS. 6A and 35B are diffused. As shown in (c), an N-type conductive layer 26 is formed. The depth of the conductive layer 26 is formed shallower than the depths of the first and second guard ring regions 13 and 14 as in the above embodiments.
[0103]
Next, using the gate electrode films 21a and 21b as a mask, a P-type impurity is implanted into the surface of the conductive layer 26, and as shown in FIGS. 7A and 36A, the surface side inside the conductive layer 26 is formed. After the P-type high concentration impurity layer 28 is formed, the high-concentration impurity layer 28 is diffused to form a P-type base region 29 as shown in FIGS. 8A and 36B. .
[0104]
Next, as shown in FIGS. 9B and 36C, a patterned resist film 31 is formed on the gate electrode films 21a and 21b. At this time, the resist film 31 is disposed only on the gate electrode film 21a in the portion that becomes the bulging portion 88, and does not protrude from the base region 29 exposed to the side position of the gate electrode film 21a. .
[0105]
In the first embodiment, as shown in FIG. 9C, the width D of the resist film 31 located on the base region 29 from the end of the gate electrode film 21a.₁It is covered with the resist film 31 up to a position far away.
[0106]
In this state, a P-type impurity is implanted inside the base region 29, and as shown in FIGS. 10B and 37A, a P-type high-concentration impurity layer is formed near the surface in the base region 29. When 32 is formed and the resist film 31 is removed and then diffused, an ohmic region 33 is formed as shown in FIGS. 11 (a) and 37 (b).
[0107]
Due to the lateral diffusion of the ohmic region 33, the end portion of the ohmic region 33 sinks to a position below the gate insulating film 19 located under the gate electrode film 21a. In the first embodiment, however, the P-type high concentration The end of the impurity layer 32 has a width D of the resist film 31 on the base region 29.₁Therefore, the end of the ohmic region 33 has a width D from the distance of the lateral diffusion.₁Only the distance subtracted is submerged below the gate insulating film 19.
[0108]
On the other hand, in the bulging portion 88, the width D of the resist film 31 on the base region 29.₂Is the width D₁Since it is smaller and close to zero, the end portion of the ohmic region 33 sinks below the gate insulating film 19 by the distance of the lateral diffusion.
[0109]
In this state, the ohmic region 33 and the base region 29 are connected to form a main diffusion region having a single comb pattern.
[0110]
In this state, a patterned resist film 35 is formed on the surface of the ohmic region 33 as shown in FIGS. 12 (b) and 37 (c). The end of the resist film 35 is separated from the end of the gate electrode film 21a by a predetermined distance, and the surface of the ohmic region 33 or the base region 29 is between the end of the resist film 35 and the gate electrode film 21a. Is exposed.
[0111]
In this state, when an N-type impurity is implanted, as shown in FIGS. 13A and 38A, the N-type high-concentration impurity layer 38 is formed between the resist film 35 and the gate electrode film 21a. Then, after the resist film 35 is removed and diffused, as shown in FIGS. 14A and 38B, the P-type region formed by the ohmic region 33 and the base region 29 is formed. Then, a source region 39 is formed.
[0112]
The source region 39 has a comb-shaped ring shape along the inner peripheral edge of the gate electrode film 21a. The inner edge of the ring-shaped source region 39 is embedded in a position below the gate insulating film 19 below the gate electrode film 21a.
[0113]
Further, the branch portion 24 and the trunk portion 22 excluding the bulging portion 88 are used.₁, 22₂In the connection portion 23, the base region 29 is located on the surface side inside the substrate 9 inside the inner edge of the source region 39, and the inner edge of the source region 39 and the inner edge of the base region 29 are arranged. The channel region 40 is between the two.
[0114]
In the bulging portion 88, the ohmic region 33 is laterally diffused beyond the inner peripheral edge of the base region 29 on the surface of the substrate 9 inside the inner edge of the source region 39. Therefore, in the bulging portion 88, the position between the inner edge of the P-type region formed by the ohmic region 33 and the base region 29 and the inner edge of the source region 39 is near the surface inside the substrate 9. The ohmic region 33 exists.
[0115]
Reference numeral 52 denotes a channel region formed in the vicinity of the surface of the ohmic region 33 between the inner peripheral edge of the source region 39 of the bulging portion 88 and the inner peripheral edge of the ohmic region 33. If the surface of the channel region 52 is inverted to N-type, the source region 39 and the portion of the N-type region 26 surrounded by the channel regions 40 and 52 are connected to each other in the bulging portion 88 by the inversion layer.
[0116]
In the channel region 52 of the bulging portion 88, the ohmic region 33 and the channel region 29 at least partially overlap, but the surface concentration of the ohmic region 33 is higher than the surface concentration of the base region 29. The surface concentration of the region 29 can be ignored. Accordingly, the threshold voltage of the channel region 52 of the bulging portion 88 is determined by the surface concentration of the laterally diffused portion of the ohmic region 33, and the threshold voltage of the channel region 52 of the bulging portion 88 is the lateral diffusion of the base region 29. This is higher than the threshold voltage of the channel region 40 of the other part determined by the surface concentration of the part.
[0117]
FIG. 29 is a drawing for explaining the shape of the ohmic region 33. Reference numeral 33 in FIG.₁Indicates the inner edge of the ohmic region 33. FIG. 30 is a diagram for explaining the planar shape and positional relationship between the two types of channel regions 40 and 52, and FIG. 31 is a diagram for explaining the planar shape of the source region 39.
[0118]
Reference 39₁, 39₂Denote the inner and outer peripheral edges of the surface of the source region 39, respectively.₁Indicates the inner peripheral edge of the surface of the base region 29.
[0119]
A channel region 40 composed of a portion in the vicinity of the surface of the base region 29 has an inner peripheral edge 39 of the source region 39.₁And an inner peripheral edge 29 of the base region 29₁The channel region 52 constituted by the portion in the vicinity of the surface of the ohmic region 33 is defined by the inner peripheral edge 33 of the ohmic region 33 of the bulging portion 88.₁And the inner peripheral edge 39 of the source region 39.₁And will be confirmed.
[0120]
The two types of channel regions 40 and 52 are arranged on the inner peripheral edge 39 of the source region 39.₁The ring-shaped one comb-shaped region is formed by the two types of channel regions 40 and 52.
[0121]
As described above, after the source region 39 is formed, an interlayer insulating film is formed on the surface, and then the interlayer insulating film is patterned. As shown in FIGS. 15A and 38C, the source region 39 is formed. Inside edge 39₁And its edge 39₁A portion of the ohmic region 33 surrounded by is exposed. Reference numeral 41 in the figure indicates an interlayer insulating film in that state.
[0122]
Next, as shown in FIGS. 17 (a), 19 (a), 20 (a), and FIGS. 39 (a) to 39 (c), the patterned source electrode film 45 and protective film 48, and the substrate 9 are formed. When the drain electrode film 49 on the back surface is formed, the field effect transistor 5 of the present invention is obtained.
[0123]
In this field effect transistor 5, the conductive layer 26 is disposed inside the channel regions 40 and 52, and the pn junction at the position of the bulging portion 88 is formed by the ohmic region 33 and the conductive region 26.
[0124]
Since the depth of the ohmic region 33 is greater than the diffusion depth of the base region 29, the breakdown voltage of the bulging portion 88 is as high as the breakdown voltage of other portions. If the conductive region 26 is not disposed around the bulging portion 88, the withstand voltage is further increased. However, even when the conductive region 26 is disposed inside the channel regions 40 and 52, the withstand voltage is significantly reduced by the bulging portion. There is no such thing. Therefore, when an N-type impurity for forming the conductive region 26 is implanted, it is not necessary to dispose a resist film on the surface of the portion inside the channel regions 40 and 52. Compared with the case where the shapes 70 and 80 are formed, the photographic process can be reduced once.
[0125]
The bulging portion 88 has a semicircular shape, but the branch portion 24 and the trunk portion 22.₁, 22₂Alternatively, the ohmic region 33 in the straight portion of the connecting portion 23 may gradually swell, and a channel region 52 constituted by a portion near the surface of the ohmic region 33 may be formed.
[0126]
32 shows a planar shape when the ohmic region 33 gradually bulges. The ohmic region 33 extends beyond the inner peripheral edge of the base region 29 at the tip of the bulging portion 89. The inner edge of the ohmic region 33 gradually recedes toward the inner side of the base region 29 as it goes toward the base portion of the bulging portion 89. The shape of the ohmic region 33 having the planar shape 82 is shown in FIG.
[0127]
41 (a) to 41 (c) show E as a tip portion of the bulging portion 89 of FIG.₁-E₁E, where the line and the bulge of the ohmic region change₂-E₂E, the part of the line and the root position_Three-E_ThreeIt is sectional drawing of a line. The ohmic region 33 of the bulging portion 89 is largely diffused in the lateral direction in the conductive region 26 at the tip portion, and in the root portion, the straight portion of the branch portion 24 and the trunk portion 22 are spread.₁, 22₂The distance between the inner peripheral edge of the ohmic region 33 and the inner peripheral edge of the base region 29 in the connection portion 23 is the same.
[0128]
As described above, when forming the bulging portion 89 in which the ohmic region 33 gradually bulges, when forming the P-type high concentration region 32 serving as a diffusion source of the ohmic region 33, The amount of protrusion of the resist film 31 from the gate electrode film 21a may be changed.
[0129]
40 (a) to (c) are illustrated in FIG.₁-E₁Line, E₂-E₂Line and E_Three-E_ThreeThe amount of protrusion D of the resist film 31 when forming a cross section corresponding to the line_Three~ D_FiveFIG. Here, D_Three<D_Four<D_FiveIt has become.
[0130]
In this way, by gradually reducing the amount of protrusion of the resist film 31 from the root direction to the tip direction of the bulging portion 89, a shape in which the ohmic region 33 is gradually swollen can be formed.
[0131]
In this case, the channel region 40 is formed by the base region 29 at the base portion of the bulging portion 89, and the channel region 52 is formed by the ohmic region 33 at the tip portion. At the position between the root portion and the tip portion, the channel region 52 formed by the ohmic region 33 is in contact with the source region 39, and the channel region 40 formed by the base region 29 is disposed between the channel region 52 and the conductive region 26.
[0132]
Moreover, in the field effect transistor of the present invention, the ohmic region 33 does not necessarily extend beyond the base region 29 in the lateral direction at the tip of the bulging portion as described above.
[0133]
The ohmic region 33 having the planar pattern indicated by reference numeral 90 in FIG. 42 has the same shape as the planar pattern 81 illustrated in FIG. 28, and bulges toward the inside of the N-type region surrounded by the channel region 40. 91 is protruded. The ohmic region 33 of the bulging portion 91 is wider than the width of the ohmic region 33 other than the bulging portion 91 and is semicircular.
[0134]
The ohmic region 33 of the bulging portion 91 in FIG. 42 does not extend beyond the base region 29 into the N-type region, unlike the bulging portion 88 of the planar pattern 81 in FIG.
[0135]
F of the bulging portion 91₁-F₁A line sectional view is shown in FIG. Further, as a portion other than the bulging portion 91, the portion F located between the branch portions 24 and the portion in which the base region 29 and the ohmic region 33 extend linearly is provided.₂-F₂A line sectional view is shown in FIG.
[0136]
As can be seen from FIG. 44 (b), the branch portion 24 and the trunk portion 22.₁, 22₂The distance between the inner peripheral edge portion of the straight portion of the base region 29 included in the connecting portion 23 and the inner peripheral edge portion of the straight portion of the ohmic region 33 is S₀And the distance between the inner peripheral edge portion of the base region 29 in the bulging portion 91 and the inner peripheral edge portion of the ohmic region 33 is S₁Then, in this planar pattern 90, S₁<S₀Has been.
[0137]
In particular, the distance S₁Is negative (S₁In the case of <0>, as shown in FIGS. 39A to 39C and FIG. 41A, the ohmic region 33 extends beyond the inner peripheral edge of the base region 29 to the N-type region. It is.
[0138]
In order to form such a bulging portion 91, when the P-type high-concentration impurity layer 32 serving as a diffusion source of the ohmic region 33 is formed, as shown in FIG. The protruding distance D of the resist film 31 from the gate electrode film 21a₇Is a protrusion distance D in a straight portion of the resist film 31 as shown in FIG.₈Smaller than that.
[0139]
As a typical method for forming the base region 29 and the source region 39 of the present invention, a P-type impurity and an N-type impurity are implanted using the gate electrode film 21a as a mask, and a P-type high concentration impurity layer 32 and an N-type impurity are implanted. Since the high-concentration impurity layer 38 is used as a diffusion source for the base region 29 and the source region 39, respectively, the sinking amount of the base region 29 and the source region 39 below the gate electrode film 21a extends over the entire outer periphery of the drain region. It is constant.
[0140]
On the other hand, in the present invention, the P-type high-concentration impurity layer 32 serving as the diffusion source of the ohmic region 33 is formed by ion implantation using the resist film 31 as a mask. The relative positional relationship with the edge portion of the gate electrode film 21a is that the protrusion distance S of the resist film 31 from the gate electrode film 21a is as follows.₁Can be adjusted by.
[0141]
As described above, the field effect transistor of the present invention has the protruding distance S of the bulged portion of the resist film 31.₁The distance between the inner peripheral edge portion of the ohmic region 33 and the inner peripheral edge portion of the base region 29 can be adjusted.
[0142]
In the present invention, of the inner peripheral edge portion of the ohmic region 33, the edge portion of the bulging portion 91 that forms the spherical joint is used as the trunk portion 22 that forms the cylindrical joint.₁, 22₂And a wide range of field effect transistors having a planar pattern extending inward from the edge portions of the connecting portion 23 and the branch portion 24.
[0143]
In the above description, the case of manufacturing a field effect transistor has been described. However, as shown in FIG. 25A, the high resistance layer 12 is replaced with the N-type thin diode constituent layer 34 instead of the low resistance layer 11. When a metal film that is formed on the back surface of the diode constituent layer 34 and is Schottky-connected to the diode constituent layer 34 is formed as an anode electrode film 50, an IGBT field effect transistor 2 using a Schottky junction is obtained. can get.
[0144]
In this case, in the Schottky diode formed between the anode electrode film 50 and the diode constituent layer 34, the drain electrode film 50 serves as an anode and the diode constituent layer 34 serves as a cathode. When the single crystal silicon wafer formed by the pulling method is used for the high resistance layer 34 instead of the epitaxially grown silicon single crystal layer, the diode component layer 34 is not provided and the anode electrode is formed on the back surface of the high resistance layer 34. The film 50 may be formed to constitute a Schottky diode.
[0145]
Further, as shown in FIG. 25B, the collector layer 20 is formed by using a P-type silicon single crystal substrate instead of the N-type silicon single crystal layer 11 and is ohmically connected to the collector layer 20. When the collector electrode 56 is formed, an IGBT field effect transistor 3 using a PN junction is obtained. This field effect transistor 3 is also included in the present invention.
Each of the field effect transistors 1, 2 and 3 has one source region 39 and one channel region 40.
[0146]
The high resistance layer 12 is epitaxially grown on the low resistance layer 11, but the high resistance silicon wafer itself is used to form the high resistance layer 12, and the high resistance layer 12 has a high resistance from the back side. An impurity having the same conductivity type as that of the resistance layer 12 may be diffused to form the low resistance layer 11 having a lower resistance than the high resistance layer 12.
[0147]
In the above description, the n-type is the first conductivity type and the p-type is the second conductivity type. Conversely, the p-type is the first conductivity type and the n-type is the second conductivity type. It may be. In this case, for example, the high resistance layer and the source region are p-type, and the base region is n-type.
[0148]
【The invention's effect】
  A field effect transistor having low conduction resistance and high breakdown voltage can be obtained.
  Since the depth of the ohmic region is deeper than that of the base region, the breakdown voltage of the bulging portion can be increased to the same level as the breakdown voltage of other portions.
[Brief description of the drawings]
FIGS. 1A to 1C are diagrams for explaining a manufacturing process of a field effect transistor according to an example of the present invention.
FIGS. 2A to 2C are diagrams (2) for explaining a manufacturing process of a field effect transistor according to an example of the present invention;
FIGS. 3A to 3C are diagrams (3) for explaining a manufacturing process of a field effect transistor according to an example of the present invention;
FIGS. 4A to 4C are views for explaining a manufacturing process of a field effect transistor according to an example of the present invention.
FIGS. 5A and 5B are views for explaining a manufacturing process of a field effect transistor according to an example of the present invention.
FIGS. 6A and 6B are diagrams (6) for explaining the manufacturing process of the field effect transistor of the example of the present invention;
FIGS. 7A and 7B are views for explaining a manufacturing process of a field effect transistor according to an example of the present invention. FIG.
FIGS. 8A and 8B are views for explaining a manufacturing process of a field effect transistor according to an example of the present invention. FIG.
FIGS. 9A to 9C are diagrams (9) for explaining the manufacturing process of the field effect transistor according to the example of the present invention;
FIGS. 10A to 10C are views for explaining a manufacturing process of a field effect transistor according to an example of the present invention.
FIGS. 11A and 11B are views for explaining a manufacturing process of a field effect transistor according to an example of the present invention.
FIGS. 12A to 12C are views for explaining a manufacturing process of a field effect transistor according to an example of the present invention.
FIGS. 13A and 13B are diagrams (13) for explaining the manufacturing process of the field effect transistor of the example of the present invention;
FIGS. 14A and 14B are views for explaining a manufacturing process of a field effect transistor according to an example of the present invention.
FIGS. 15A and 15B are views for explaining a manufacturing process of a field effect transistor according to an example of the present invention.
FIG. 16 is a view (16) for explaining the manufacturing process of the field effect transistor of the example of the present invention;
FIGS. 17A and 17B are cross-sectional views of FIG. 16, and are views (17) for explaining the manufacturing process of the field effect transistor of the example of the present invention;
FIG. 18 is a view (18) for explaining the manufacturing process of the field effect transistor according to the example of the invention;
FIGS. 19A and 19B are cross-sectional views of FIG. 18, and are diagrams (19) for explaining a manufacturing process of a field effect transistor according to an example of the present invention;
FIGS. 20A and 20B are diagrams for explaining the manufacturing process of the field effect transistor according to the example of the present invention.
21A is a diagram for explaining a positional relationship among a conductive layer, a channel region, and a source region. FIG. 21B is a partial enlarged view thereof, and is a diagram for explaining a position of a floating potential region.
FIG. 22 is a diagram for explaining a state in which a conductive layer is partially formed in the drain region;
FIG. 23 shows an example of the planar shape of the channel region and the diffusion layer inside the field effect transistor of the present invention.
FIG. 24 shows an example of the planar shape of the channel region and the diffusion layer inside the field effect transistor of the present invention.
25A is another example of the present invention and is a diagram for explaining an IGBT type field effect transistor using a Schottky junction. FIG. 25B is another example of the present invention and is a PN junction. FIG. 6 is a diagram for explaining an IGBT type field effect transistor using a TFT
FIG. 26 is a diagram for explaining a conventional field effect transistor;
FIG. 27 is a diagram for explaining the cell arrangement of the field-effect transistor;
FIG. 28 is a diagram for explaining a pattern in a case where an ohmic region is partially expanded in the field effect transistor of the present invention.
FIG. 29 is a diagram for explaining the pattern of the ohmic region;
FIG. 30 is a diagram for explaining the pattern of the channel region;
FIG. 31 is a diagram for explaining the pattern of the source region;
FIG. 32 is a diagram for explaining a pattern in which a part of the ohmic region gradually bulges among the field effect transistors of the present invention.
FIG. 33 is a diagram for explaining the pattern of the ohmic region;
FIGS. 34A to 34C are diagrams (1) for explaining a manufacturing process of a field effect transistor having a pattern in which an ohmic region is partially expanded;
FIGS. 35A to 35C are diagrams (2) for explaining the continuation of the process.
36A to 36C are diagrams for explaining the continuation of the process (3).
FIGS. 37A to 37C are diagrams for explaining the continuation of the process (4);
38A to 38C are diagrams for explaining the continuation of the process (5).
FIG. 39A to FIG. 9C are diagrams for explaining the continuation of the process (6).
FIGS. 40A and 40B are diagrams for explaining a method for creating a pattern in which the ohmic region of the bulging portion gradually bulges, wherein (a): a tip portion, (b): an intermediate portion, and (c): a root portion.
41A is a cross-sectional view of a tip portion, FIG. 41B is a cross-sectional view of an intermediate portion, and FIG. 41C is a cross-sectional view of a root portion.
FIG. 42 is a view for explaining another plane pattern of the present invention.
FIGS. 43A and 43B are cross-sectional views thereof.
FIGS. 44A and 44B are diagrams for explaining a method of forming the bulge portion;
[Explanation of symbols]
1, 2, 3, ... Field effect transistor
11 ... Low resistance layer of the first conductivity type
12 …… High resistance layer of the first conductivity type
19 …… Gate insulation film
20 …… Collector layer
21a …… Gate electrode film
26 …… First conductive type conductive layer
29 …… Base region of second conductivity type
34 …… Diode component layer
39 …… Source region of the first conductivity type
40 …… Channel area
45 …… Source electrode film
49 …… Drain electrode film
50 …… Anode electrode membrane
56 …… Collector electrode film

Claims (7)

A second conductivity type main diffusion region formed in the first conductivity type high resistance layer and disposed on the surface side of the high resistance layer;
A source region of a first conductivity type formed in the main diffusion region and disposed on the surface thereof;
An annular channel region that is part of the main diffusion region and is located between the edge of the main diffusion region and the edge of the source region, and is formed in an annular shape;
A drain region surrounded by the annular channel region;
A gate insulating film disposed at least on the surface of the annular channel region;
A gate electrode film disposed on the surface of the gate insulating film,
The source region is disposed on an outer periphery of the annular channel region;
A field effect transistor in which the source region and the drain region are electrically connected when the surface of the annular channel region is inverted to the first conductivity type by a voltage applied to the gate electrode film ;
The drain region has at least one elongated trunk,
A plurality of elongated branches having one end connected to the trunk,
The annular channel region is disposed surrounding the trunk and the branch;
The trunk located between the branches is bulged in a circular shape toward the inside of the trunk itself,
The main diffusion region has a second conductivity type base region and a second conductivity type ohmic region having a diffusion depth deeper than the base region,
In the portion of the trunk that bulges in a circular shape, the inner periphery of the ohmic region penetrates into the drain region rather than the inner periphery of the base region, and the ohmic region and the drain region form a pn junction Field effect transistor to be formed . 2. The field effect transistor according to claim 1 , wherein the annular channel region at the tip of the branch portion is bent at a substantially right angle so as to form three sides of a quadrangle . It said drain region in the interior of the surface, the field effect transistor of any one of claims 1 or claim 2 having a conductive layer resistance is lower the first conductivity type than the high resistance layer. Said drain region within the surface-side field effect transistor according to any one of the channel region and the first to third aspects floating potential region of the second conductivity type of the non-contact is placed. On the back side of the high resistance layer, a low resistance layer having a first conductivity type and lower resistance than the high resistance layer is disposed,
The field effect transistor according to any one of claims 1 to 4 , wherein a drain electrode film that forms an ohmic junction with the low resistance layer is disposed on a surface of the low resistance layer. An anode electrode film that forms a Schottky junction with the high resistance layer is disposed on a back surface of the high resistance layer, and a diode having the anode electrode film as an anode and the high resistance layer as a cathode is formed. 1 to the field effect transistor of any one of claims 4. On the back side of the high resistance layer, a collector layer of the second conductivity type is disposed,
The field effect transistor according to any one of claims 1 to 4 , wherein a collector electrode film that forms an ohmic junction with the collector layer is disposed on a surface of the collector layer.

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