JP3913043B2 - Field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect transistor, and more particularly, to a high withstand voltage low resistance field effect transistor.
[0002]
[Prior art]
Conventionally, a field effect transistor that allows current to flow in the thickness direction of a substrate has been used as a power control element.
[0003]
Figure 46 Reference numeral 105 denotes an example of a conventional field effect transistor, which includes a silicon single crystal substrate 111. A drain layer 112 formed by epitaxial growth is disposed on the surface of the single crystal substrate 111.
[0004]
The silicon single crystal substrate 111 is doped with N-type impurities at a high concentration, and a drain electrode film 148 is formed on the back surface thereof. The drain layer 112 is doped with N-type impurities at a low concentration, and a P-type base region 154 is formed in the vicinity of the surface thereof.
In the base region 154, an N-type impurity is further diffused from the surface to form a source region 161.
[0005]
Reference numeral 110 denotes a channel region located between the edge portion of the source region 161 and the edge portion of the base region 154. A gate insulating film 126 and a gate electrode film 127 are arranged in this order on the channel region 110.
An interlayer insulating film 141 is formed on the surface and side surfaces of the gate electrode film 127, and a source electrode film 144 is disposed on the surface.
[0006]
The base region 154 as described above is arranged in an island shape in the vicinity of the surface of the drain region 112, and includes one base region 154 and the source region 161 and the channel region 110 disposed in the base region 154. One cell 101 is formed.
[0007]
FIG. FIG. 5 is a plan view showing the surface of the drain region 112, in which a plurality of rectangular cells 101 are arranged in a matrix.
When this field effect transistor 105 is used, when the source electrode film 144 is placed at the ground potential, a positive voltage is applied to the drain electrode film 148, and a gate voltage (positive voltage) higher than the threshold voltage is applied to the gate electrode film 127, An N-type inversion layer is formed on the surface of the P-type channel region 110, the source region 161 and the conductive region 111 are connected by the inversion layer, and the field effect transistor 105 becomes conductive.
When a voltage lower than the threshold voltage (for example, ground potential) is applied to the gate electrode film 127 from this state, the inversion layer disappears and the field effect transistor 105 is cut off.
[0008]
In the field effect transistor 105 having the above structure, when the voltage applied to the drain electrode film 148 is increased, an avalanche breakdown occurs at the PN junction interface between the base region 154 and the drain region 112. In this case, the current flows to the side portion of the cell 101 arranged in the peripheral portion of one element, and the current tends to concentrate on a portion having a small area, so that the element is easily broken. .
[0009]
[Problems to be solved by the invention]
The present invention was created in order to solve the above-described disadvantages of the prior art, and an object thereof is to provide a field effect transistor having a high breakdown voltage and a low resistance.
[0010]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention according to claim 1 is a first conductivity type drain layer, and a second conductivity type body region disposed in the drain layer and forming a PN junction with the drain layer. A source region of a first conductivity type disposed in the body region and forming a PN junction with the body region, a part of the body region, and an edge of the body region and an edge of the source region A channel region located in between, a gate insulating film disposed on the surface of the channel region, and a second conductivity type disposed at a position surrounding the body region in the drain layer and forming a PN junction with the drain layer A first conductivity type first buried region which is disposed at a position in contact with the bottom surface of the ring diffusion region in the drain layer and forms a PN junction with the ring diffusion region. A source electrode film electrically connected to the source diffusion region and the ring diffusion region, wherein the first buried region has a higher concentration than the drain layer, and the ring diffusion region and the drain A field effect transistor in which the PN junction formed by the ring diffusion region and the first buried region has a lower breakdown voltage than the PN junction formed by the layer.
The field effect transistor according to claim 2 is the field effect transistor according to claim 1, wherein the field insulating film is disposed on the surface of the drain layer, and the pad is disposed on the field insulating film and to which the bonding wire is fixed. A pad diffusion region of a second conductivity type disposed in the drain layer below the pad electrode film and forming a PN junction with the drain layer; and a pad contacting the bottom surface of the pad diffusion region A diffusion region and a second buried region of a first conductivity type forming a PN junction, wherein the second buried region has a higher concentration than the drain layer, and the pad diffusion region and the drain layer are The PN junction formed by the pad diffusion region and the second buried region is a field effect transistor having a lower breakdown voltage than the PN junction formed.
The invention according to claim 3 is the field effect transistor according to claim 2, wherein the pad diffusion region is disposed outside the ring diffusion region.
The invention according to claim 4 is the field effect transistor according to claim 3, wherein the field effect transistor is disposed at a position surrounding the pad diffusion region in the drain layer, forms a PN junction with the drain layer, and the ring diffusion region. And a ring-shaped small ring diffusion region electrically connected to the field effect transistor.
The invention according to claim 5 is the field effect transistor according to any one of claims 1 to 4, wherein the first conductivity type semiconductor substrate disposed on the back side of the drain layer, and the semiconductor substrate The field effect transistor is disposed on a surface opposite to the drain layer and includes a drain electrode that is ohmically connected to the semiconductor substrate.
A sixth aspect of the present invention is the field effect transistor according to any one of the first to fourth aspects, wherein the second conductivity type collector layer disposed on the back side of the drain layer, and the collector layer The field effect transistor is disposed on a surface opposite to the drain layer and includes a collector electrode that is ohmically connected to the collector layer.
A seventh aspect of the present invention is the field effect transistor according to any one of the first to fourth aspects, wherein the Schottky electrode is disposed on the back side of the drain layer and forms a Schottky junction with the drain layer. Is a field effect transistor.
[0011]
The field effect transistor of the present invention has a first conductivity type buried region, and the buried region is deeper than the bottom surface of the second conductivity type pad diffusion region below the pad electrode film to which the bonding wire is fixed. It is located inside the drain layer at the position and is in contact with the bottom surface of the pad diffusion region. For this reason, a PN junction is formed between the buried region and the pad diffusion region.
[0012]
When the second conductive type ring diffusion region having a ring shape in the vicinity of the pad diffusion region is provided and the buried region of the first conductivity type is disposed at the bottom of the ring diffusion region, the pad diffusion region Similarly to the above, a PN junction is formed between the ring diffusion region and the buried region.
[0013]
When a high voltage is applied to the field effect transistor having such a configuration, a high voltage is applied to the PN junction between the ring diffusion region connected to the source electrode film and the buried region, and the ring diffusion region and the buried region are An avalanche breakdown occurs, and a current flows through the PN junction.
[0014]
When the area of the PN junction formed by the buried region and the ring diffusion region is increased in this way, even if an avalanche breakdown occurs in the PN junction and the current flows, the current spreads over the entire large area PN junction. The current is less likely to be concentrated in one place, and element breakdown due to current concentration is less likely to occur. Therefore, current concentration is likely to occur due to avalanche breakdown in the vicinity of the base region, and element breakdown is less likely to occur as compared with a conventional element that tends to be destroyed.
[0015]
In the present invention, when a high-concentration buried region that forms a PN junction with the body region is provided at the bottom of the body region of the cell, the avalanche break also occurs at the PN junction between the body region and the buried region. Down occurs, and current flows through both the PN junction between the body region and the buried region and the PN junction between the buried region and the ring diffusion region.
[0016]
In this case, if the area of the PN junction between the buried region and the pad diffusion region is larger than the area of the PN junction between the body region and the buried region in the cell, most of the current flowing due to the avalanche breakdown is Since the current flows through the PN junction between the buried region and the pad diffusion region, the current flowing through the PN junction in the cell can be reduced. Therefore, a large current does not flow intensively in the cell and the device is not destroyed.
[0017]
Note that the pad diffusion region may affect the electric field distribution around the pad diffusion region due to the arrangement relationship with other diffusion layers, and as a result, the withstand voltage may decrease. For example, if the ring diffusion region enters the inside of the element to avoid the pad diffusion region, the distance between the ring diffusion region and the guard ring region disposed outside the device becomes non-constant. The electric field distribution with respect to the guard ring region disposed in the region becomes non-uniform, and the withstand voltage decreases.
[0018]
Therefore, in the present invention, a small ring diffusion region having a rectangular ring shape connected to the ring diffusion region and formed by diffusing impurities of the second conductivity type is formed, and pad diffusion is performed in the region surrounded by the small ring diffusion region. An area may be arranged, and a small ring buried area formed by diffusing impurities of the first conductivity type may be arranged along the bottom surface of the small ring diffusion area and having a planar shape in a ring shape.
[0019]
With this configuration, the small ring diffusion region is surrounded by the ring diffusion region, and its presence hardly affects the surrounding electric field distribution. Therefore, the breakdown voltage of the element does not decrease due to the influence. For example, even if the ring diffusion region has entered the inside of the element to avoid the pad diffusion region as described above, the small penetration region that surrounds the pad diffusion region is formed by connecting the part that has entered the inside, When the distance between the outer edge portion of the ring diffusion region and the small ring diffusion region and the guard ring region arranged outside thereof is constant, the outer edge portion of the ring diffusion region and the small ring diffusion region having the same potential, Since the electric field distribution with the guard ring region becomes uniform, the breakdown voltage of the element does not decrease.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
Below, the manufacturing method of MOSFET which is a field effect transistor which concerns on one Embodiment of this invention is demonstrated. In the following, the first conductivity type impurity is an N-type impurity, and the second conductivity type impurity is a P-type impurity.
[0021]
First, N made of silicon ⁺ Mold substrate body and N formed on its surface ^- A substrate provided with a type epitaxial layer is prepared. A plurality of elements to be described later can be formed on the substrate. Cross-sectional views illustrating the manufacturing process of one element among these plural elements are shown in FIGS. 1A to 37A and FIGS. 1B to 37B. 1A to 37A show cross-sectional views in a pad region described later, and FIGS. 1B to 37B show cross-sectional views in a cell region and a peripheral region described later. ing. In FIGS. 1A and 1B, reference numeral 10 denotes a substrate, reference numeral 11 denotes a substrate body, and reference numeral 12 denotes an epitaxial layer.
[0022]
Next, when the substrate 10 is subjected to thermal oxidation treatment, a thermal oxide film 13 made of a silicon oxide film is formed on the surface of the epitaxial layer 12 as shown in FIGS.
[0023]
Next, a resist solution is applied to the surface of the thermal oxide film 13 to form a resist film, and then patterned. Reference numeral 61 in FIGS. 3A and 3B shows a patterned resist film.
[0024]
FIG. 38 is a plan view of the element in the state of FIGS. 3 (a) and 3 (b). 3A shows a cross-sectional view taken along line AA in FIG. 38, and FIG. 3B shows a cross-sectional view taken along line BB in FIG.
As shown in FIG. 38, the patterned resist film 61 has a plurality of openings 51, each opening 51 is formed in a square ring shape, and is arranged concentrically with each other. Here, four openings 51 are formed. Among these, the outermost periphery opening 51 is disposed so that the outer edge portion thereof is positioned in the vicinity of the edge that defines one element, and the innermost periphery opening 51 is disposed so as to surround the central portion of one element. ing.
[0025]
Next, using the resist film 61 as a mask, the thermal oxide film 13 exposed on the bottom surface of the opening 51 of the resist film 61 is etched to remove the resist film 61. The state is shown in FIGS. 4 (a) and 4 (b). Reference numeral 52 in the figure indicates an opening of the thermal oxide film 13 formed by etching the thermal oxide film 13, and the epitaxial layer 12 is exposed from the bottom of the opening 52.
[0026]
Next, when the surface of the thermal oxide film 13 is irradiated with a P-type impurity such as boron (B), the P-type impurity is implanted into the bottom surface of the opening 52 of the thermal oxide film 13, as shown in FIGS. As shown, the P-type high concentration layer 14 is formed at the bottom of the opening 52.
[0027]
Next, when the substrate 10 is heat-treated, as shown in FIGS. 6A and 6B, the P-type high-concentration layer 14 is diffused to form four square ring-shaped guard rings composed of P-type diffusion regions. Region 15 is formed and the surface of guard ring region 15 is covered with a thermal oxide film. The planar shape of these guard ring regions 15 is the same as the opening 51 of the resist film 61 described above.
[0028]
Next, as shown in FIGS. 7A and 7B, a patterned resist film 66 is formed on the surface of the thermal oxide film 13. The resist film 66 is disposed on the guard ring region 15 and covers the guard ring region 15.
[0029]
When the thermal oxide film 13 is etched using the resist film 66 as a mask, the thermal oxide film 13 on the guard ring region 15 is covered with the resist film 66 and is not etched. On the other hand, in another region where the guard ring region 15 is not formed, the thermal oxide film 13 is removed, and the surface of the epitaxial layer 12 is exposed. Thereafter, the resist film 66 is removed. The state is shown in FIGS. 8 (a) and 8 (b).
[0030]
Next, when the substrate 10 is thermally oxidized, a thermal oxide film 16 made of a silicon oxide film is formed on the exposed surface of the epitaxial layer 12 as shown in FIGS. 9A and 9B.
[0031]
Next, as shown in FIGS. 10A and 10B, a resist film is formed on the surface of the thermal oxide films 16 and 13 and patterned to form grooves and openings described later in the resist film. The planar shape of the resist film is shown in FIG. 10 (a) and 10 (b) correspond to the CC line sectional view and the DD line sectional view of FIG. 39, respectively.
[0032]
This groove is a groove formed in a square ring shape and having a constant width, and its outer end is located inside a certain distance from the inner end of the guard ring region 15 arranged on the innermost side. A part of the groove goes inside. The groove is indicated by reference numeral 251 in FIGS.
[0033]
The groove 251 separates the resist film into two. Of these, a resist film located inside the groove 251 (hereinafter referred to as an inner resist film) is indicated by reference numeral 62, and a resist film located outside (referred to as an outer resist film hereinafter) is indicated by reference numeral 262.
[0034]
The inner resist film 62 has an outer end coincident with the inner end of the groove 251. On the other hand, the outer resist film 262 has an inner end coincident with the outer end of the groove 251, and the outer end is located on the inner side of the edge defining one element. The surface of the thermal oxide film 13 is exposed between the demarcating edge and the outer edge portion of the outer resist film 262.
[0035]
The outer resist film 262 has a rectangular opening 252 in a part of the portion bulged inward. Note that the groove 251 and the opening 252 have substantially the same size in FIGS. 10A and 10B, but the opening 252 is actually larger.
[0036]
On the other hand, the inner resist film 62 has a comb-like opening 53 therein. The opening 53 has two stem-shaped openings 73 each formed in an elongated shape. ₁ 73 ₂ And one connection opening 75 and a plurality of branch openings 74.
[0037]
Two stem openings 73 ₁ 73 ₂ Are connected to the ends of a plurality of branch openings 74. The connection opening 75 and each branch-shaped opening 74 have a trunk-shaped opening 73. ₁ 73 ₂ Is perpendicular to. The surface of the thermal oxide film 16 is exposed at the bottom of the opening 53.
[0038]
Next, the thermal oxide films 16 and 13 are etched using the inner resist film 62 and the outer resist film 262 as a mask.
Then, as shown in FIG. 11 (a), the thermal oxide film 16 where the groove 251 is formed is removed, and a square ring-shaped groove 253 is formed at the same position as the square ring-shaped groove 251. The portion of the outer resist film 262 where the rectangular opening 252 is formed is removed, and a rectangular opening 254 is formed at the same position as the opening 252.
[0039]
Hereinafter, a region outside the outer end of the groove 253 is referred to as a peripheral region 72, and a region inside the inner end of the groove 251 is referred to as a cell region 71. Further, as described above, since a part of the groove 251 enters the inside, a part of the outer resist film 262 bulges inward. This bulged portion is referred to as a pad region 77 below.
[0040]
In the cell region 71, as shown in FIG. 11B, an opening 54 having the same pattern as the comb-like opening 53 of the inner resist film 62 is formed, and in the peripheral region 72, a portion near the edge that defines one element. The thermal oxide film 13 is removed.
[0041]
The epitaxial layer 12 is exposed at the bottoms of the comb-shaped openings 54, the rectangular openings 254, and the square ring-shaped grooves 253, and at the vicinity of the edge that defines one element.
[0042]
Next, the resist films 62 and 262 are removed, and the element formation surface is irradiated with N-type impurities using the thermal oxide films 16 and 13 as a mask. Here, phosphorus is used as the N-type impurity, and the dose amount is 2 × 10. ¹³ cm ^-2 It is said.
[0043]
Then, the N-type impurities are exposed to the bottoms of the comb-shaped opening 54, the rectangular opening 254, and the square ring-shaped groove 253, and the portion of the epitaxial layer 12 exposed in the vicinity of the edge defining one element. As shown in FIGS. 12A and 12B, N-type impurities are respectively introduced into the bottoms of the comb-shaped opening 54, the rectangular opening 254, and the square ring-shaped groove 253, as shown in FIGS. Comb-shaped first implantation region 18, a rectangular first implantation region 264, and a square ring-shaped first implantation region 263 are formed.
[0044]
Next, the substrate 10 is heat-treated. Here, heat treatment is performed at a temperature of 1100 ° C. for 200 minutes. Then, as shown in FIGS. 13A and 13B, the impurities in the first implantation regions 263, 264, and 18 are diffused, respectively, and the rectangular first implantation region 264 and the first ring in the shape of a square ring are formed. A rectangular low-resistance region 221, a square ring-shaped low-resistance region 220, and a comb-shaped low-resistance region 20 are formed in the portions where the implantation region 263 and the comb-shaped first implantation region 18 are formed, respectively. A thermal oxide film is formed, and these low resistance regions 221, 220, and 20 are both covered with the thermal oxide film.
[0045]
Thereafter, as shown in FIGS. 14A and 14B, a patterned resist film 67 is formed on the surface of the thermal oxide films 16 and 13.
The planar shape of the resist film 67 is shown in FIG. FIGS. 14A and 14B correspond to the EE line cross-sectional view and the FF line cross-sectional view of FIG. 40, respectively. The resist film 67 has an opening 59. The opening 59 is located inside the cell region 71, and the outer end portion thereof is arranged so as to be located on the inner side by a certain distance from the inner end portion of the square ring-shaped low resistance layer 220.
[0046]
When the thermal oxide film 16 is etched using the resist film 67 as a mask, the thermal oxide films 16 and 13 located on the bottom surface of the opening 59 and the bottom surface of the groove 43 are removed, and in the peripheral region 72, the outermost peripheral conductive region 5 is removed. In the cell region 71, the epitaxial layer 12 and the comb-like low resistance region 20 are exposed. Thereafter, the resist film 67 is removed. FIGS. 15A and 15B are cross-sectional views with the resist film 67 removed.
[0047]
Next, the element formation surface is irradiated with an N-type impurity. Here, phosphorus is used as the N-type impurity, and the dose amount is 2 × 10. ¹² cm ^-2 It is said. As shown in FIGS. 16A and 16B, the pad ring 77 and the guard ring region 15 in the peripheral region 72 are covered with thick thermal oxide films 16 and 13, respectively, so that the irradiated N-type impurity is not implanted. . On the other hand, in the cell region 71, an N-type impurity is implanted into the exposed comb-like low-resistance region 20 and the epitaxial layer 12, and the N-type impurity is introduced into the comb-like low-resistance region 20 and the epitaxial layer 12 in the surrounding region. A comb-like second injection region 23 formed by implanting impurities is formed.
[0048]
Next, the substrate 10 is heat-treated under conditions that do not form a thermal oxide film. Here, heat treatment is performed for 500 minutes in a nitrogen atmosphere at a temperature of 1100 ° C. Then, impurities contained in the second implantation region 23 diffuse into the epitaxial layer 12 and the comb-like low resistance region 20.
[0049]
By the way, the impurity contained in the second implantation region 23 is N-type, and the epitaxial layer 12 and the comb-like low-resistance region 20 are also N-type. Are of the same conductivity type. Even when the comb-shaped low resistance region 20 is formed, the impurity diffused from the comb-shaped first implantation region 18 is N-type, and the epitaxial layer 12 is also N-type. The impurity to be diffused and the impurity of the object to be diffused have the same conductivity type.
[0050]
In these cases, since the PN junction is not formed between the diffusion region formed by the diffused impurity and the object to be diffused, the diffusion impurity and the diffusion region have the same conductivity type. Cannot originally define its diffusion depth.
Therefore, in this case, the depth position where the impurity concentration of the diffusion region is twice the impurity concentration of the object to be diffused is defined as the diffusion depth of the diffusion region.
[0051]
At this time, when the second implantation region 23 is diffused, a first high concentration region 24 is formed on the comb-like low resistance region 20 as shown in FIG. A second high concentration region 25 is formed on the side.
[0052]
If the diffusion depth of the comb-like low resistance region 20 is defined at a position where the impurity concentration of the comb-like low resistance region 20 is twice that of the epitaxial layer 12, the diffusion depth is The depth from the surface of the epitaxial layer 12 to the boundary surface between the epitaxial layer 12 and the substrate body 11 is shallower, and the bottom surface of the low resistance region 20 is located above the bottom surface of the epitaxial layer 12.
[0053]
Further, if the diffusion depth of the second high concentration region 25 is defined at a position where the impurity concentration of the second high concentration region 25 is twice the impurity concentration of the epitaxial layer 12, the diffusion depth is defined. Is shallower than the diffusion depth of the low resistance region 20, and the bottom surface of the second high concentration region 25 is located above the bottom surface of the low resistance region 20.
[0054]
Assuming that the diffusion depth of the first high concentration region 24 is the same as the diffusion depth of the second high concentration region 25, the N-type impurity has already been diffused in the first high concentration region 24. Since the N-type impurity is further diffused from the second implantation region 23 in the comb-shaped low resistance region 20, the impurity concentration of the first high concentration region 24 is the second high concentration region. The concentration is higher than 25.
[0055]
Next, when the substrate 10 is thermally oxidized, a gate insulating film 27 made of a thermal oxide film is formed on the surfaces of the first and second high concentration regions 24 and 25 as shown in FIGS. 18 (a) and 18 (b). At the same time, the thermal oxide films 16 and 13 respectively disposed in the pad region 77 and the peripheral region 72 are both thickened.
[0056]
Next, polysilicon previously doped with impurities is deposited by CVD. Then, as shown in FIGS. 19A and 19B, on the surfaces of the gate oxide film 27 in the cell region 71, the peripheral region 72, and the thermal oxide films 13 and 16 respectively disposed in the pad region 77, A gate electrode film 28 is formed.
[0057]
Next, after forming a resist film on the surface of the gate electrode film 28, patterning is performed to form grooves and openings described later in the resist film. The planar shape of the resist film in this state is shown in FIG. 20A and 20B correspond to the GG line cross-sectional view and the HH line cross-sectional view of FIG. 41, respectively.
[0058]
This groove is a groove having a constant width formed in a square ring shape, and is arranged so that the outer end portion thereof is located outside by a certain distance from the outer end portion of the above-described square ring-shaped low resistance layer 221. Has been. The groove is indicated by reference numeral 255 in FIGS.
[0059]
The groove 255 separates the resist film into two. Of these, the inner resist film positioned inside the groove 255 is indicated by reference numeral 63, and the outer resist film positioned outside is indicated by reference numeral 263.
[0060]
The outer resist film 263 has an inner end coincident with the outer end of the groove 255, and the inner resist film 63 has an outer end coincident with the inner end of the groove 255 and includes the guard ring region 15. The surface of the gate electrode film 28 is exposed between the peripheral region 72 and the outer edge portion of the outer resist film 263. A part of the outer resist film 263 bulges inward, and a rectangular opening 256 is provided in a part of the bulged part, and the surface of the gate electrode film 28 is exposed from the surface of the opening 256. Yes.
[0061]
On the other hand, the inner resist film 63 has an opening 55. The opening 55 is comb-shaped in the same manner as the first high-concentration region 24 described above, and the end thereof is outside a certain distance from the outer edge of the comb-shaped first high-concentration region 24. It is arranged to be located. The gate electrode film 28 is also exposed at the bottom of the comb-shaped opening 55.
[0062]
When the gate electrode film 28 is etched using the resist films 63 and 263 as a mask, as shown in FIGS. 21A and 21B, a rectangular opening 256, a comb-shaped opening 55, and a square ring-shaped groove are formed. The gate electrode film 28 at the bottom of 255 is removed, and the gate insulating film 27 and the thermal oxide film 16 are exposed. Next, after the resist films 63 and 263 are peeled off, the gate insulating film 27 is etched using the gate electrode film 28 as a mask to expose the rectangular opening 256, the comb-shaped opening 55, and the bottom of the square ring-shaped groove 255. The gate insulating film 27 and the thermal oxide film 16 are removed.
[0063]
Next, the element formation surface is irradiated with a P-type impurity using the gate electrode film 28 and the gate insulating film 27 as a mask. Here, boron is used as the P-type impurity, and the dose amount is 2 × 10. ¹³ cm ^-2 It is said. As shown in FIGS. 22A and 22B, in the cell region 71, the irradiated P-type impurities are exposed at the bottoms of the rectangular opening 256, the comb-shaped opening 55, and the square ring-shaped groove 255. The first high-concentration region 24 and the second high-concentration region 25 surrounding the first high-concentration region 24 and the first and second high-concentration regions 24 and 25 are comb-shaped made of P-type impurities. A third implantation region 31 is formed. In the pad region 77, the rectangular opening 256 and the rectangular ring-shaped groove are implanted into the rectangular opening 256, the first high-concentration regions 220 and 221 exposed at the bottom of the groove 255, and the surrounding epitaxial layer 12. The third implantation region 231 is made of a P-type impurity at the bottom of the H.sub.255 and has a square ring shape and a rectangular shape in plan view. ₁ 231 ₂ Is formed.
On the other hand, since the peripheral region 72 is covered with the thick thermal oxide film 13, no P-type impurity is implanted into the outermost peripheral conductive region 5 and the guard ring region 15.
[0064]
Next, the substrate 10 is heat-treated under the condition that the thermal oxide film is not formed. Here, heat treatment is performed at a temperature of 1135 ° C. for 400 minutes. Then, each of the third implantation regions 31 and 231 is performed. ₁ 231 ₂ P-type impurities are diffused, and as shown in FIGS. 23A and 23B, in the cell region 71, a comb-shaped body region 32 is formed at the position of the comb-shaped third implantation region 31, On the other hand, in the pad region 77, a rectangular ring-shaped, rectangular third implantation region 231 is formed. ₁ 231 ₂ The ring diffusion regions 232 each having a square ring shape ₁ And a rectangular pad diffusion region 232 ₂ Is formed.
[0065]
Among these, the P-type impurity in the third implantation region 31 of the cell region 71 diffuses into both the first and second high concentration regions 24 and 25, but the body region 32 in the second high concentration region 25. The diffusion depth is shallower than the diffusion depth of the second high concentration region 25. In addition, since the N-type impurity concentration of the first high-concentration region 24 is larger than the N-type impurity concentration of the second high-concentration region 25, the diffusion depth in the first high-concentration region 24 is the body region 32. It becomes shallower than the diffusion depth in the second high concentration region 25.
[0066]
Therefore, in the first high concentration region 24, even if the P-type impurity is diffused to form the body region 32, the first high concentration region remains below the body region 32. The edge portion of the body region 32 is buried under the gate insulating film 27 by lateral diffusion. The body region 32 is shaped like a comb in the same way as the opening 55 of the resist film 63 described above, and only one body region 32 is arranged in one element. For this reason, the area which the body region 32 occupies in one element is large.
[0067]
In FIG. 23 (b), reference numeral 22 denotes an embedded region that is a remaining portion of the first high-concentration region 24, and the embedded region 22 has an edge inside the edge of the body region 32. It is located and is buried under the body region 32.
The embedded region 22 is arranged along the bottom of the body region 32 having a planar shape in a comb shape, and the planar shape is comb-like like the body region 32.
[0068]
On the other hand, a square ring-shaped ring diffusion region 232 ₁ And a rectangular pad diffusion region 232 ₂ The first high-concentration region also remains below. Reference numerals 222 and 223 denote buried regions that are the remaining portions of the first high-concentration region 20, and the edges of these buried regions 222 and 223 are ring diffusion regions 232. ₁ And pad diffusion region 232 ₂ Are located inside the edges of the ring diffusion regions 232, respectively. ₁ And pad diffusion region 232 ₂ It is embedded in the bottom.
[0069]
The buried regions 222 and 223 are respectively connected to the ring diffusion regions 232. ₁ And pad diffusion region 232 ₂ The ring diffusion regions 232 are arranged in a rectangular shape and a rectangular ring shape, respectively. ₁ , Pad diffusion region 232 ₂ Is the same.
[0070]
In this state, the body region 32 and the ring diffusion region 232 ₁ And pad diffusion region 232 ₂ The exposed body region 32 and ring diffusion region 232 are exposed as shown in FIGS. ₁ And pad diffusion region 232 ₂ Patterned resist films 64 and 264 are respectively formed on the surface. The planar shapes of the resist films 64 and 264 are shown in FIG. 24A and 24B correspond to the KK line cross-sectional view and the LL line cross-sectional view of FIG. 42, respectively.
[0071]
Of these resist films 64, 264, the resist film 64 disposed on the surface of the body region 32 has a comb shape like the body region 32, as shown in FIG. The outer edge portion is disposed so as to be located on the inner side by a certain distance from the outer edge portion of the body region 32.
[0072]
A gap 57 is formed between the outer edge of the comb-like resist film 64 and the inner end of the gate electrode film 28. The gap 57 has a ring shape in plan, and the outer peripheral edge coincides with the edge portion of the gate electrode film 28, and the inner peripheral edge coincides with the edge of the resist film 64. In the cell region 71, the body region 32 is exposed on the bottom surface of the gap 57. In contrast, the pad diffusion region 232 ₂ The resist film 264 disposed on the thermal oxide film 13 and the outermost peripheral conductive region 5 covers the thermal oxide film 13 and the outermost peripheral conductive region 5.
[0073]
Next, when the element formation surface is irradiated with the N-type impurities using the resist films 64 and 264 as masks, as shown in FIGS. N-type impurity implantation region 35 is formed by implantation on the surface side of body region 32 exposed at the bottom surface. Here, As is used as the N-type impurity, and the dose amount is 5 × 10 5. ¹⁵ cm ^-2 It is said.
[0074]
Next, after removing the resist films 64 and 264, the substrate 10 is heat-treated under the condition that the thermal oxide film is not formed. Here, heat treatment is performed in a nitrogen atmosphere at a temperature of 1000 ° C. for 10 minutes. Then, the N-type impurity in the impurity implantation region 35 is diffused, and an N-type source region 36 is formed on the surface side of the body region 32 as shown in FIGS.
[0075]
As described above, the body region 32 and the source region 36 have their respective edges buried under the gate insulating film 27 by lateral diffusion. The lateral diffusion amount of the body region 32 is larger than the lateral diffusion amount of the source region 36, and the edge of the source region 36 does not protrude from the edge of the body region 32. A body region 32 remains between the edges of 32. Reference numeral 80 denotes a channel region which is a body region located between the edge of the source region 36 and the edge of the body region 32. The channel region 80 sinks to a position below the gate insulating film 27, and the gate insulating film 27 and the gate electrode film 28 are disposed above the channel region 80.
Next, as shown in FIGS. 27A and 27B, the gate electrode film 28, the source region 36, the body region 32, and the ring diffusion region 232. ₁ And pad diffusion region 232 ₂ An insulating film 38 is formed on the surface of the substrate by CVD. Here, a silicon oxide film is formed as the insulating film 38.
[0076]
Next, as shown in FIGS. 28A and 28B, a patterned resist film 65 is formed on the surface of the insulating film 38. The resist film 65 has openings 58 and 258 in the cell region 71 and the pad region 77, respectively.
[0077]
Of these, the opening 58 disposed in the cell region 71 is provided on the surface of the source region 36 and the body region 32 located inside thereof. In addition, the opening 258 disposed in the pad region 77 has a ring diffusion region 232. ₁ The insulating films 38 are exposed at the bottoms of the openings 58 and 258, respectively.
[0078]
Next, when the insulating film 38 is etched using the resist film 65 as a mask, the insulating film 38 exposed on the bottom surfaces of the openings 58 and 258 is removed as shown in FIGS. The source region 36 and the body region 32 are exposed on the bottom surface, and the ring diffusion region 232 is formed on the bottom surface of the opening 258. ₁ Is exposed.
Next, the resist film 65 is removed, and a metal film 46 is formed on the entire element formation surface as shown in FIGS. 30 (a) and 30 (b).
[0079]
Next, as shown in FIGS. 31A and 31B, a patterned resist film 66 is formed on the metal film 46. The resist film 66 has openings 259 and 260 in the peripheral region 72 and the pad region 77, respectively. Among these, the opening 260 in the peripheral region 72 is disposed in a region where the outermost peripheral conductive region 5 is not formed, and the opening 259 in the pad region 77 is formed in the ring diffusion region 232. ₁ And pad diffusion region 232 ₂ Is located in the area between.
[0080]
When the metal film 46 is etched using the resist film 66 as a mask, the metal film 46 at the bottom of the openings 259 and 260 is removed, and the metal film 46 is formed in the pad region 77 as shown in FIGS. 46 is separated into two of a source electrode film 45a and a gate electrode film 45b. On the other hand, in the peripheral region 72, the outermost peripheral conductive material separated from the source electrode film 45a and the gate electrode film 45b is formed on the outermost peripheral conductive region 5. A film 98 is formed.
[0081]
Next, after removing the resist film 66 as shown in FIGS. 33A and 33B, as shown in FIGS. 34A and 34B, the source electrode film 45a, the gate electrode film 45b, A protective film 99 made of a silicon oxide film is formed on the surface of the peripheral conductive film 98 by a CVD method.
[0082]
Next, as shown in FIGS. 35A and 35B, a patterned resist film 67 is formed on the surface of the protective film 99. The resist film 67 has a rectangular opening 68. ₁ 68 ₂ And these openings 68 ₁ 68 ₂ Are respectively disposed on the source electrode film 45a and the gate electrode film 45b.
[0083]
When the protective film 99 is etched using the resist film 67 as a mask, the protective film 99 at the bottom of the opening 68 is removed, and the opening 68 is removed. ₁ 68 ₂ The source electrode film 45a and the gate electrode film 45b are exposed at the bottom of each. Of these openings 68 ₂ The gate electrode film 45b exposed from is referred to as a pad electrode film 45c. Thereafter, the resist film 67 is peeled off. The state is shown in FIGS. 36 (a) and 36 (b).
[0084]
Next, when a metal film is formed on the surface opposite to the element formation surface of the substrate 10 to form the drain electrode film 91, a MOSFET as shown by reference numeral 1 in FIGS. 37A and 37B is formed.
[0085]
In the MOSFET 1, when a positive voltage higher than the threshold voltage is applied to the gate electrode film 28 with the source electrode film 45 a connected to the ground potential and a positive voltage applied to the drain electrode film 91, An N-type inversion layer is formed on the surface, the surface portion of the second high-concentration region 25 serving as the drain region and the source region 39 are connected by the inversion layer, and the MOSFET 1 becomes conductive.
[0086]
Then, a current flows from the source region 39 through the inversion layer to the second high concentration region 25 serving as the drain region. At this time, as described above, the edge of the buried region 22 is located inside the edge of the body region 32, and the buried region 22 is located at the bottom of the body region 32. Is not connected to.
When the gate electrode film 28 is connected to the ground potential from the conductive state, the inversion layer disappears and the MOSFET 1 is cut off.
[0087]
In the MOSFET 1 of the present embodiment described above, the ring diffusion region 232 is formed in the pad region 77 as described above. ₁ , Pad diffusion region 232 ₂ The buried regions 222 and 223 are disposed at the bottom of the ring diffusion region 232, respectively. ₁ And the buried region 222, the planar shape is a ring-shaped PN junction 285. ₁ On the other hand, pad diffusion region 232 ₂ And the buried region 223, the PN junction 285 having a rectangular planar shape ₂ Is formed.
[0088]
The impurity concentration of the buried regions 222 and 223 is higher than that of the epitaxial layer 12, and the ring-shaped PN junction 285. ₁ Or rectangular PN junction 285 ₂ The withstand voltage of the ring diffusion region 231 ₁ Between the epitaxial layer 12 and the pad diffusion region 231 ₂ The breakdown voltage of the PN junction 286 formed between the epitaxial layer 12 and the epitaxial layer 12 is lower.
[0089]
Similarly, in the cell region 71, a PN junction 85 having a comb shape between the one body region 32 arranged in a comb shape and the one buried region 22 arranged along the bottom surface thereof. Is formed. As described above, the impurity concentration of the buried region 22 is higher than that of the second high concentration region 25, and the withstand voltage of the comb-like PN junction 85 between the buried region 22 and the body region 32 is the second high concentration region. The breakdown voltage of the PN junction 86 formed between the concentration region 25 and the body region 32 is lower.
[0090]
When a high voltage is applied to the MOSFET 1, the ring diffusion region 232 ₁ And a ring-shaped PN junction 285 formed between the first and second buried regions 222 ₁ In addition, the comb-like PN junction 85 formed between the body region 32 and the buried region 22 is both avalanche broken down.
[0091]
At this time, the pad diffusion region 232 ₂ Is not connected to any electrode and is placed at a floating potential, so that the pad diffusion region 232 ₂ Rectangular PN junction 285 between the gate and the buried region 221 ₂ No voltage is applied to and no avalanche breakdown occurs. Further, the ring diffusion region 232 ₁ Between the epitaxial layer 12 and the pad diffusion region 232 ₂ PN junction 286 formed between the epitaxial layer 12 and the epitaxial layer 12 ₁ 286 ₂ Moreover, since the breakdown voltage of the PN junction 86 formed between the second high concentration region 25 and the body region 32 is high, these PN junctions 286 ₁ 286 ₂ 86, no avalanche breakdown occurs.
[0092]
The PN junction 285 thus formed into a ring shape and a comb shape ₁ , 85 becomes avalanche breakdown, comb-like PN junction 285 ₁ 85, current flows.
Of these, ring-shaped PN junction 285 ₁ Are arranged so as to surround the entire comb-shaped body region in the cell region 71, and the ring-shaped PN junction 285. ₁ Is longer than the comb-like PN junction 85 in the cell region 71 and has a larger width. Therefore, the ring-shaped PN junction 285 ₁ Is larger than the area of the comb-like PN junction 85. For this reason, most of the current that flows due to the avalanche breakdown is largely caused by the ring-shaped PN junction 285. ₁ Flowing into.
[0093]
Ring-shaped PN junction 285 ₁ Because of the large area, even if a large current flows due to avalanche breakdown, the current flows in the ring-shaped PN junction 285. ₁ It flows uniformly throughout, and no large current flows intensively. For this reason, the device is less likely to be destroyed as compared with the conventional device in which current concentration has occurred due to the avalanche breakdown.
[0094]
In the above-described embodiment, one ring-shaped embedded region 222 is replaced with the ring diffusion region 232. ₁ Of the ring diffusion region 232. ₁ However, the present invention is not limited to this, and for example, a plurality of buried regions are provided, and each buried region has a ring diffusion region 232. ₁ You may arrange | position so that it may be scattered on the bottom face of this at predetermined intervals. With this configuration, the area of the PN junction between the ring diffusion region and the buried region is smaller than when the buried region is arranged in a ring shape along the bottom surface of the ring diffusion region. Since it becomes small, it is preferable to arrange the embedded region in a ring shape.
[0095]
By the way, in general, the breakdown voltage of the element depends on the ring diffusion region 232. ₂ However, in the case of a high breakdown voltage element, the electric field distribution in the vicinity of the guard ring region 15 has a large influence on the breakdown voltage, and cannot be ignored.
[0096]
In the above-described embodiment, the ring diffusion region 232 ₁ A part of the ring diffusion region 232 is disposed inside the ring diffusion region 232. ₁ , And the inner end of the guard ring region 15 arranged on the innermost side is not constant, the ring diffusion region 232 ₁ And the guard ring region 15 become non-uniform in electric field distribution, the breakdown voltage is lowered, and the effect of improving the breakdown resistance is reduced.
[0097]
Therefore, FIG. Shows a plan view, FIG. You may comprise MOSFET8 which shows sectional drawing in (a), (b). FIG. (a), (b) FIG. Respectively correspond to the P-P line sectional view and the Q-Q line sectional view.
[0098]
This MOSFET 8 is FIG. As shown in FIG. ₁ Are connected by a linear connection region 270 formed by diffusing P-type impurities. As a result, the connection region 270 and the ring diffusion region 232 are connected. ₁ Are arranged in a straight line with the outer peripheral portion of the ring diffusion region 232. ₁ A large rectangular ring-shaped P-type diffusion region composed of an outer peripheral portion and a connection region 270 is formed, and an outer edge portion of the rectangular ring-shaped P-type diffusion region and the innermost guard ring region 15 are arranged. The distance from the inner end is constant. For this reason, the ring diffusion region 232 ₁ And the guard ring region 15, the electric field distribution is uniform, the withstand voltage is increased, and the breakdown resistance is improved.
[0099]
Moreover, the connection region 270 and the ring diffusion region 232 described above. ₁ A small ring diffusion region 275 having a rectangular ring shape with a small planar shape is formed with the portion that enters the inside of the inner ring, and the inner end portion of the small ring diffusion region 275 is a pad diffusion region 232. ₂ A buried region 271 is formed by diffusing N-type impurities along the bottom surface of the connection region 270.
[0100]
Thus, the pad diffusion region 232 ₂ Is the ring diffusion region 232 ₁ Are surrounded by a small ring diffusion region 270 having the same potential as the pad diffusion region 232. ₂ Does not affect the surrounding electric field distribution and the like, and therefore the ring diffusion region 232 is not affected. ₁ And the guard ring region 15 have a uniform electric field distribution and no breakdown voltage.
[0101]
When a high voltage is applied to the MOSFET 8 configured in this way, the ring diffusion region 232 ₁ A ring-shaped PN junction 285 formed between the small ring diffusion region 275 having the same potential as that of the buried region 271 and the buried region 271. _Three And ring diffusion region 232 ₁ Avalanche breakdown and pad diffusion region 232 ₂ Current also flows through the small ring diffusion region 270 and the small ring buried region 271 around the periphery of the small ring.
[0102]
In the above-described embodiment, the buried region 22 is provided below the body region 32, and the avalanche breakdown is generated at the PN junction 85 between the body region 32 and the buried region 22 so that current flows. The present invention is not limited to this, and the buried region 22 may not be provided below the body region 32. In this case, the ring diffusion region 232 ₁ And a ring-shaped PN junction 285 formed between the first and second buried regions 222 ₁ Only avalanche breakdown and ring-shaped PN junction 285 ₁ Current flows only through the ring, but the current does not concentrate, and the ring-shaped PN junction 285 ₁ The ring-shaped PN junction 285 ₁ If the area is large, no element breakdown occurs due to current concentration.
[0103]
In the above, the case where a MOSFET is manufactured as a field effect transistor has been described. However, as indicated by reference numeral 2 in FIGS. ⁺ In place of the substrate body 11 made of silicon, a collector layer 95 is formed using a P-type silicon single crystal substrate, and when a collector electrode 96 that is in ohmic contact with the collector layer 95 is formed on the collector layer 95, a PN junction is used. An IGBT (Insulated gate bipolar transistor) type field effect transistor can be obtained. This field effect transistor 2 is also included in the present invention.
[0104]
Further, a Schottky junction type IGBT element as indicated by reference numeral 3 in FIGS. 44A and 44B is also included in the present invention.
In this Schottky junction type IGBT element 3, the substrate body 11 is not provided, and a Schottky electrode film 97 is disposed on the back side of the epitaxial layer 12.
[0105]
The Schottky electrode film 97 forms a Schottky junction with the epitaxial layer 12, and a Schottky diode is formed in which the Schottky electrode film 97 serves as an anode and the epitaxial layer 12 side serves as a cathode.
[0106]
When a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode film 28 with the source electrode film 45a connected to the ground potential and a positive voltage applied to the Schottky electrode film 97, a portion close to the surface of the channel region 80 becomes N Invert to mold.
[0107]
The second high concentration region 25 is in contact with the epitaxial layer 12, and when the surface portion of the channel region is inverted to N-type, the source region 36 and the epitaxial layer 12 are connected by the inversion layer. In this state, since the Schottky junction is forward-biased, a current flows from the epitaxial layer 12 side toward the source region 36, and the Schottky junction type IGBT element 3 becomes conductive.
[0108]
In the above-described embodiment, the ring diffusion region 232 connected to the source electrode film 45a. ₁ And the pad diffusion region 232 placed at the floating potential. ₂ And each diffusion region 232 ₁ 232 ₂ However, the present invention is not limited to this. , Only the ring diffusion region 232 having a large area may be provided, and the pad diffusion region placed at the floating potential may not be formed.
[0109]
FIG. Shows a plan view of the substrate surface in a state where all of the thin film formed on the substrate surface has been removed. . In this case, the width of the ring diffusion region 232 can be made wider and the area of the ring diffusion region 232 can be made larger than when the pad diffusion region is provided. If the buried region 220a is arranged along the bottom of the large ring diffusion region 232, the area of the ring-shaped PN junction 285 formed between the ring diffusion region 232 and the buried region 220a is increased, and the avalanche breakdown is caused. Even if a considerably large current flows, element destruction does not occur.
[0110]
Further, in the above-described embodiment, the comb-shaped body region 32 and the embedded region 22 are formed in the cell region 71, but the present invention is not limited to this, for example, FIG. As shown in the plan view of the cell region, a plurality of cells 205 may be arranged in the vicinity of the surface of the drain region 25 so as to be separated from each other, thereby constituting one element 7.
[0111]
Each cell 205 has a body region 32, a source region 36, a channel region 80, and a buried region 22. In each cell 205, the diffusion depth and impurity concentration of the body region 32, the source region 36, the channel region 80, and the buried region 22 are the same as those of an element having a comb-shaped body region in plan view.
[0112]
The source region 36 is formed in a ring shape, and the outer edge thereof is spaced apart from the edge of the body region 32, and the channel region 80 is located between the outer edge of the source region 36 and the edge of the body region 32. Yes. The embedded region 22 has the same shape as the body region 32 and is disposed inside the body region 32.
[0113]
Also FIG. Although the case where the planar shapes of the body region 32 and the embedded region 22 are rectangular has been shown, the planar shape of the body region 32 and the embedded region 22 when a plurality of cells 205 are arranged is not limited to this, for example, a circle or a triangle Or a hexagonal shape.
[0114]
Moreover, in the said embodiment, although the 1st conductivity type in this invention was N type and the 2nd conductivity type was P type, the 1st, 2nd conductivity type of this invention is not restricted to this, reversely Alternatively, the first conductivity type may be a P-type and the second conductivity type may be an N-type.
[0115]
【The invention's effect】
Device breakdown due to avalanche breakdown is less likely to occur.
[Brief description of the drawings]
FIG. 1A is a first cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention.
(b): First cross-sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention
2A is a second cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): Second sectional view for explaining a manufacturing process in the cell region and the peripheral region of the field effect transistor of the example of the present invention.
3A is a third cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention. FIG.
(b): Third sectional view for explaining a manufacturing process in the cell region and the peripheral region of the field effect transistor of the example of the present invention.
4A is a fourth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): Fourth sectional view for explaining a manufacturing process in the cell region and the peripheral region of the field effect transistor of the example of the present invention.
5A is a fifth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): 5th sectional view explaining the manufacturing process in the cell region and the peripheral region of the field effect transistor of an example of the present invention
6A is a sixth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): A sixth cross-sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention
7A is a seventh cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): Seventh cross-sectional view for explaining a manufacturing process in the cell region and the peripheral region of the field effect transistor of an example of the present invention
8A is an eighth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): An eighth cross-sectional view illustrating a manufacturing process in the cell region and the peripheral region of the field effect transistor of the example of the present invention.
9A is a ninth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): A ninth cross-sectional view illustrating a manufacturing process in the cell region and the peripheral region of the field effect transistor of the example of the present invention.
10A is a tenth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): Tenth cross-sectional view for explaining a manufacturing process in the cell region and the peripheral region of the field effect transistor of one example of the present invention
11A is an eleventh cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): An eleventh cross-sectional view illustrating a manufacturing process in the cell region and the peripheral region of the field effect transistor of one example of the present invention.
12A is a twelfth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): A twelfth cross-sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention.
13A is a thirteenth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): A thirteenth cross-sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor according to an example of the present invention.
14A is a fourteenth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): 14th sectional view explaining the manufacturing process in the cell region and the peripheral region of the field effect transistor of one example of the present invention
15A is a fifteenth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): A fifteenth cross-sectional view illustrating a manufacturing process in the cell region and the peripheral region of the field effect transistor of one example of the present invention.
FIG. 16A is a sixteenth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): Sixteenth sectional view for explaining a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention.
FIG. 17A is a seventeenth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): Seventeenth sectional view for explaining a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention.
18A is an eighteenth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): An eighteenth cross-sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention
19A is a nineteenth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): 19th sectional view explaining the manufacturing process in the cell region and the peripheral region of the field effect transistor of the example of the present invention
20A is a twentieth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): A twentieth cross-sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention.
FIG. 21A is a twenty-first cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): 21st sectional view explaining the manufacturing process in the cell area | region and peripheral region of the field effect transistor of an example of this invention
22A is a twenty-second cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): 22nd sectional view explaining the manufacturing process in the cell region and peripheral region of the field effect transistor of an example of this invention
FIG. 23A is a twenty-third cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): 23rd sectional view explaining the manufacturing process in the cell region and the peripheral region of the field effect transistor of an example of the present invention
FIG. 24A is a twenty-fourth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): A twenty-fourth cross-sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention
FIG. 25A is a twenty-fifth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): 25th sectional view for explaining the manufacturing process in the cell region and the peripheral region of the field effect transistor of one example of the present invention
FIG. 26A is a twenty-sixth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): A twenty-sixth sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention.
FIG. 27A is a twenty-seventh cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): 27th sectional view for explaining the manufacturing process in the cell region and the peripheral region of the field effect transistor of one example of the present invention
FIG. 28A is a twenty-eighth sectional view for explaining a manufacturing process in a pad region of a field effect transistor according to an example of the present invention;
(b): 28th sectional view for explaining the manufacturing process in the cell region and the peripheral region of the field effect transistor of one example of the present invention;
FIG. 29A is a 29th cross-sectional view illustrating the manufacturing process in the pad region of the field effect transistor according to the example of the invention;
(b): 29th sectional view for explaining the manufacturing process in the cell region and the peripheral region of the field effect transistor of one example of the present invention
30A is a thirtieth cross-sectional view illustrating the manufacturing process in the pad region of the field effect transistor according to the example of the invention. FIG.
(b): 30th sectional view for explaining the manufacturing process in the cell region and the peripheral region of the field effect transistor of one example of the present invention
FIG. 31A is a thirty-first cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): A thirty-first cross-sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor according to an example of the present invention.
FIG. 32A is a thirty-second cross sectional view illustrating the manufacturing process in the pad region of the field effect transistor according to the example of the invention;
(b): A thirty-second cross-sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor according to an example of the present invention.
FIG. 33A is a thirty-third cross sectional view illustrating the manufacturing process in the pad region of the field effect transistor according to the example of the invention;
(b): A thirty-third cross-sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor according to an example of the present invention.
34A is a thirty-fourth cross sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention; FIG.
(b): A thirty-fourth cross-sectional view illustrating a manufacturing step in a cell region and a peripheral region of a field effect transistor according to an example of the present invention.
FIG. 35A is a thirty-fifth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): A thirty-fifth cross-sectional view illustrating a manufacturing step in a cell region and a peripheral region of a field effect transistor according to an example of the present invention.
FIG. 36A is a thirty-sixth cross-sectional view illustrating a manufacturing step in a pad region of a field effect transistor according to an example of the present invention;
(b): A thirty-sixth sectional view illustrating a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention.
FIG. 37A is a cross-sectional view showing a structure in a pad region of a field effect transistor according to an example of the present invention;
(b): Cross-sectional view showing the structure of the cell region and the peripheral region of the field effect transistor of one example of the present invention
FIG. 38 is a first plan view illustrating the manufacturing process of the field effect transistor according to the example of the present invention;
FIG. 39 is a second plan view for explaining the manufacturing process for the field-effect transistor according to the example of the invention;
FIG. 40 is a third plan view for explaining the manufacturing process for the field effect transistor according to the example of the present invention;
FIG. 41 is a fourth plan view illustrating the manufacturing process for the field effect transistor according to the example of the present invention;
FIG. 42 is a fifth plan view illustrating the manufacturing process for the field effect transistor according to the example of the present invention;
43A is a cross-sectional view illustrating a structure in a pad region of an IGBT field effect transistor which is another example of the present invention. FIG.
(b): A cross-sectional view illustrating a structure in a cell region and a peripheral region of an IGBT field effect transistor which is another example of the present invention
44A is a cross-sectional view illustrating a structure in a pad region of an IGBT field effect transistor using a Schottky junction as another example of the present invention. FIG.
(b) is a cross-sectional view illustrating a structure of a cell region and a peripheral region of an IGBT field effect transistor using a Schottky junction, which is another example of the present invention.
FIG. 45 The figure for demonstrating the field effect transistor which is another example of this invention, and in which the several cell was arrange | positioned at matrix form
FIG. 46 Sectional drawing explaining the structure of the conventional field effect transistor
FIG. 47 Plan view for explaining the arrangement state of a conventional field effect transistor
FIG. 48 The top view explaining the state of the substrate surface of the field effect transistor which is another example of the present invention and has a structure in which only the ring diffusion region is provided
FIG. 49 (a) is a cross-sectional view illustrating a structure in a pad region of a field effect transistor which is another example of the present invention and has a structure in which a pad diffusion region is surrounded by a small ring diffusion region
(b): A cross-sectional view illustrating a structure of a cell region and a peripheral region of a field effect transistor having another structure of the present invention, in which a pad diffusion region is surrounded by a small ring diffusion region
FIG. 50 The top view for demonstrating the field effect transistor which is another example of this invention, and has a structure where the pad diffused region was enclosed by the small ring diffused region
[Explanation of symbols]
11 …… Board body
12 …… Epitaxial layer
22, 222, 223 ... Embedded region
27 …… Gate insulation film
28 …… Gate electrode film
32 …… Body area
45 …… Source electrode film
80 …… Channel area
91 …… Drain electrode film
232 ₁ …… Ring diffusion region
232 ₂ ...... Pad diffusion area
150 …… Surface protective film

Claims (7)

A drain layer of a first conductivity type;
A body region of a second conductivity type disposed in the drain layer and forming a PN junction with the drain layer;
A source region of a first conductivity type disposed within the body region and forming a PN junction with the body region;
A channel region that is part of the body region and is located between an edge of the body region and an edge of the source region;
A gate insulating film disposed on a surface of the channel region;
A ring-shaped ring diffusion region of a second conductivity type disposed at a position surrounding the body region in the drain layer and forming a PN junction with the drain layer;
A first buried region of a first conductivity type disposed at a position in contact with the bottom surface of the ring diffusion region in the drain layer and forming a PN junction with the ring diffusion region;
A source electrode film electrically connected to the source diffusion region and the ring diffusion region;
The first buried region has a higher concentration than the drain layer, and a PN formed by the ring diffusion region and the first buried region rather than a PN junction formed by the ring diffusion region and the drain layer. A field-effect transistor whose junction has a lower breakdown voltage. A field insulating film disposed on the surface of the drain layer;
A pad electrode film disposed on the field insulating film and to which a bonding wire is fixed;
A second conductive type pad diffusion region disposed in the drain layer below the pad electrode film and forming a PN junction with the drain layer;
A first conductivity type second buried region that forms a PN junction with the pad diffusion region in contact with the bottom surface of the pad diffusion region;
The second buried region has a higher concentration than the drain layer, and a PN formed by the pad diffusion region and the second buried region rather than a PN junction formed by the pad diffusion region and the drain layer. 2. The field effect transistor according to claim 1, wherein the junction has a lower breakdown voltage.   The field effect transistor according to claim 2, wherein the pad diffusion region is disposed outside the ring diffusion region.   4. A ring-shaped small ring diffusion region disposed at a position surrounding the pad diffusion region in the drain layer, forming a PN junction with the drain layer, and electrically connected to the ring diffusion region. The field effect transistor as described. A first conductivity type semiconductor substrate disposed on the back side of the drain layer;
5. The field effect transistor according to claim 1, further comprising: a drain electrode disposed on a surface of the semiconductor substrate opposite to the drain layer and ohmically connected to the semiconductor substrate. A collector layer of a second conductivity type disposed on the back side of the drain layer;
5. The field effect transistor according to claim 1, further comprising a collector electrode disposed on a surface of the collector layer opposite to the drain layer and ohmically connected to the collector layer. 6.   5. The field effect transistor according to claim 1, further comprising a Schottky electrode disposed on a back surface side of the drain layer and forming a Schottky junction with the drain layer.

Images