JP2003152181A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for improving the degree of avalanche destruction proof in a field effect transistor. SOLUTION: Buried regions 222 and 223 where PN junctions 2851 and 2852 are formed are arranged at the bases of an annular diffusion area 2321 and a pad diffusion area 2322 with them in a pad region 77 by MOSFET1. When high voltage is applied to MOSFET1, avalanche break-down occurs between the annular diffusion region 2321 connected to a ground potential and the buried region 222 positioned at the base. Current flows in the annular PN junction 2851 , but the area of annular PN junction is large and current flows to the whole junction even if large current flows. The concentration of current is difficult to occur and therefore element destruction due to the concentration of current is difficult to occur.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a field effect transistor having high breakdown voltage and low resistance.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor has been used as a power control element which allows a current to flow in the thickness direction of a substrate.

Referring to FIG. 47, reference numeral 105 is an example of a conventional field effect transistor, which has a silicon single crystal substrate 111. The drain layer 112 formed by epitaxial growth on the surface of the single crystal substrate 111.
Are arranged.

A silicon single crystal substrate 111 is heavily doped with N-type impurities, and a drain electrode film 148 is formed on the back surface thereof. Further, the drain layer 112 is lightly doped with N-type impurities, and a P-type base region 154 is formed near the surface thereof. In the base region 154, N type impurities are further diffused from the surface thereof to form a source region 161.

Reference numeral 110 is a channel region located between the edge portion of the source region 161 and the edge portion of the base region 154. A gate insulating film 126 and a gate electrode film 127 are arranged in this order above the channel region 110. An interlayer insulating film 141 is formed on the surface and side surfaces of the gate electrode film 127, and a source electrode film 144 is arranged on the surface.

The base region 154 as described above is arranged in an island shape near the surface of the drain region 112, and one base region 154 and the source region 161 and the channel region 110 arranged in the base region 154. And 1
Individual cells 101 are formed.

FIG. 48 is a plan view showing the surface of the drain region 112, in which a plurality of rectangular cells 101 are arranged in a matrix. When this field effect transistor 105 is used, the source electrode film 144 is placed at the ground potential,
A positive voltage is applied to the drain electrode film 148, and a gate voltage (positive voltage) higher than the threshold voltage is applied to the gate electrode film 127.
Is applied, an N-type inversion layer is formed on the surface of the P-type channel region 110, and the source region 161 and the conductive region 111 are formed.
And are connected by the inversion layer, and the field effect transistor 105 becomes conductive. From that state, the gate electrode film 127
When a voltage below the threshold voltage (eg, ground potential) is applied to the field effect transistor 10, the inversion layer disappears and the field effect transistor 10
5 is cut off.

In the field effect transistor 105 having the above structure, when the voltage applied to the drain electrode film 148 is increased, the PN of the base region 154 and the drain region 112 is increased.
Avalanche breakdown occurs at the bond interface. In this case, the current flows to the side of the cell 101 arranged in the peripheral portion of one element, and the current tends to concentrate in a portion having a small area, so that the element is easily broken. .

[0009]

SUMMARY OF THE INVENTION The present invention was created in order to solve the above-mentioned disadvantages of the prior art, and an object thereof is to provide a field effect transistor having a high breakdown voltage and a low resistance.

[0010]

In order to solve the above-mentioned problems, the invention according to claim 1 provides a drain layer of the first conductivity type, an insulating film disposed on one surface of the drain layer, and the insulating layer. A pad electrode film disposed on the film, to which a bonding wire is fixed, and a drain electrode located below the pad electrode film in the drain layer and having a conductivity opposite to that of the first conductivity type from one surface side of the drain layer. Field effect transistor having a pad diffusion region formed of a diffusion region formed by diffusing an impurity of the second conductivity type of the second conductivity type, the inside of the drain layer being deeper than a bottom surface of the pad diffusion region. The first conductivity type buried region is located and is in contact with the bottom surface of the pad diffusion region. The invention according to claim 2 is the field effect transistor according to claim 1, wherein the body region is a diffusion region formed by diffusing impurities of the second conductivity type from one surface side of the drain layer. And a diffusion region formed by diffusing an impurity of the first conductivity type from the surface side of the body region, the source region being inside the body region, and a part of the body region. A channel region located between an edge of the body region and an edge of the source region, a gate insulating film arranged at least on a surface of the channel region, and a gate electrode film arranged on a surface of the gate insulating film. And a cell having a source electrode film connected to the source region,
When the surface of the channel region is inverted by the voltage applied to the gate electrode film, the drain layer and the source region located outside the channel region are electrically connected. The invention according to claim 3 is the field-effect transistor according to any one of claims 1 and 2, wherein an outer peripheral edge portion of the embedded region is located inside an outer peripheral edge portion of the pad diffusion region. . The invention according to claim 4 is
The field effect transistor according to any one of claims 1 to 3, wherein an impurity concentration of the buried region is higher than an impurity concentration of the drain layer. According to a fifth aspect of the invention, a drain layer of the first conductivity type, a body region formed by diffusing impurities of the second conductivity type from one surface side of the drain layer, and a surface of the body region. A diffusion region formed by diffusing an impurity of the first conductivity type from the side, the source region disposed inside the body region, and a part of the body region and an edge of the body region. A channel region located between the edge of the source region, a gate insulating film disposed at least on the surface of the channel region, a gate electrode film disposed on the surface of the gate insulating film, and a surface of the source region. A cell having a source electrode film disposed on the gate electrode film, the drain located outside the channel region when the surface of the channel region is inverted by a voltage applied to the gate electrode film. Wherein a source region is a field effect transistor are electrically connected, from the one surface of the drain layer, the impurity of the second conductivity type is formed by being diffused,
A ring-shaped planar shape, a ring diffusion region connected to the source electrode film and having an inner end located outside the cell, and the drain at a position deeper than a bottom surface of the ring diffusion region. A first conductivity type buried region located inside the layer and in contact with the bottom surface of the ring diffusion region; an insulating film disposed on one surface of the drain layer; and a region outside the region surrounded by the ring diffusion region. And a pad electrode film on which the bonding wire is fixed. The invention according to claim 6 is the field-effect transistor according to claim 5, wherein the buried region is located at the center of the bottom surface of the ring diffusion region in the width direction. An invention according to claim 7 is the field effect transistor according to any one of claims 1 to 6, wherein the pad diffusion region is connected to the source region.
According to an eighth aspect of the present invention, a drain layer of the first conductivity type, a body region formed by diffusing impurities of the second conductivity type from one surface side of the drain layer, and a surface of the body region A diffusion region formed by diffusing an impurity of the first conductivity type from the side, the source region disposed inside the body region, and a part of the body region and an edge of the body region. A channel region located between the edge of the source region, a gate insulating film disposed at least on the surface of the channel region, a gate electrode film disposed on the surface of the gate insulating film, and a surface of the source region. A cell having a source electrode film disposed on the gate electrode film, the drain located outside the channel region when the surface of the channel region is inverted by a voltage applied to the gate electrode film. A field effect transistor in which a layer and the source region are electrically connected to each other, and the field effect transistor is formed by diffusing impurities of the second conductivity type from one surface side of the drain layer, and has a ring-shaped planar shape. A ring diffusion region connected to the source electrode film and located inside the drain layer at a position deeper than a bottom surface of the ring diffusion region. A first conductivity type buried region in contact with the bottom surface of the ring diffusion region, an insulating film disposed on one surface of the drain layer, and an insulating film located outside the region surrounded by the ring diffusion region. The pad electrode film, which is arranged and to which the bonding wire is fixed, and which is located in the drain layer below the pad electrode film and has a conductivity type opposite to the first conductivity type from one surface side of the drain layer. A pad diffusion region formed of a diffusion region formed by diffusing the second conductivity type impurity, and a second diffusion type impurity diffused from one surface side of the drain layer, and has a planar shape. A ring-shaped small ring diffusion region connected to the ring diffusion region and a first ring-shaped first ring located inside the drain layer at a position deeper than the bottom face of the small ring diffusion region and in contact with the bottom face of the small ring diffusion region. The pad diffusion region has a conductive type small ring embedded region and is arranged in a portion surrounded by the small ring diffusion region. A ninth aspect of the present invention is the field-effect transistor according to any one of the first to eighth aspects, wherein the surface of the drain layer opposite to the surface on which the insulating film is located has a first conductivity. Type semiconductor substrate, and a drain electrode ohmic-connected to the semiconductor substrate is provided on the surface of the semiconductor substrate. Claim 10
The present invention is the field-effect transistor according to any one of claims 1 to 8, wherein a second conductivity type collector is provided on a surface of the drain layer opposite to a surface on which the insulating film is located. A layer is provided, and a collector electrode ohmic-connected to the semiconductor substrate is provided on the surface of the collector layer. The invention according to claim 11 is the field-effect transistor according to any one of claims 1 to 8, wherein the drain layer is provided on a surface of the drain layer opposite to a surface on which the insulating film is located. A Schottky electrode is provided that forms a Schottky junction with the layer.

The field effect transistor of the present invention has the first conductivity type buried region, and the buried region is the bottom surface of the second conductivity type pad diffusion region below the pad electrode film to which the bonding wire is fixed. It is located inside the drain layer at a deeper position and is in contact with the bottom surface of the pad diffusion region. Therefore, a PN junction is formed between the embedded region and the pad diffusion region.

When a ring-shaped second conductivity type ring diffusion region is provided in the vicinity of the pad diffusion region and the first conductivity type buried region is arranged at the bottom of the ring diffusion region, Similar to the pad diffusion region, a PN junction is formed between the ring diffusion region and the buried region.

When a high voltage is applied to the field effect transistor having such a structure, the high voltage is applied to the PN junction between the ring diffusion region connected to the source electrode film and the buried region, and the ring diffusion region and the ring diffusion region are connected. Avalanche breakdown occurs between the buried region and the PN junction between which a current flows.

When the area of the PN junction formed by the buried region and the ring diffusion region is increased as described above, the P
Even if an avalanche breakdown occurs in the N-junction and a current flows, the current spreads over the large-area PN junction, so that the current is less likely to be concentrated in one place, and element breakdown due to the current concentration is less likely to occur. . Therefore, current concentration is likely to occur due to avalanche breakdown around the base region, and element breakdown is less likely to occur as compared with the conventional element that is apt to be destroyed.

In the present invention, when a high-concentration buried region forming a PN junction with the body region is provided at the bottom of the body region of the cell, the PN junction between the body region and the buried region is formed. Avalanche breakdown also occurs, and current flows through both the PN junction between the body region and the buried region and the PN junction between the buried region and the ring diffusion region.

In this case, if the area of the PN junction between the buried region and the pad diffusion region is made larger than the area of the PN junction between the body region and the buried region in the cell, the current flowing by the avalanche breakdown is large. Since a part flows to the PN junction between the buried region and the pad diffusion region, the current flowing to the PN junction in the cell can be reduced. Therefore, a large current does not flow intensively in the cell and the element is not destroyed.

The pad diffusion region may affect the electric field distribution around the pad diffusion region due to the arrangement relationship with other diffusion layers, and as a result, the breakdown voltage may decrease. For example, if the ring diffusion region enters the inside of the device to avoid the pad diffusion region, the distance between the ring diffusion region and the guard ring region arranged outside is not constant, so the ring diffusion region and the outside thereof The electric field distribution with the guard ring region arranged in the area becomes non-uniform, and the breakdown voltage decreases.

Therefore, in the present invention, a rectangular ring-shaped small ring diffusion region which is connected to the ring diffusion region and is formed by diffusing impurities of the second conductivity type is formed, and the small ring diffusion region is surrounded by the small ring diffusion region. , A pad diffusion region is arranged, the small ring buried region is arranged along the bottom surface of the small ring diffusion region, and the first conductivity type impurities are diffused so that the planar shape becomes a ring shape. Good.

According to this structure, the small ring diffusion region is surrounded by the ring diffusion region, and its existence has almost no influence on the electric field distribution in the surroundings, so that the breakdown voltage of the element does not decrease due to the influence. For example, as described above, even if the ring diffusion region has entered the inside of the element to avoid the pad diffusion region, the part that has entered the inside is connected to form a small ring diffusion region surrounding the pad diffusion region,
When the distance between the outer edge portions of the ring diffusion area and the small ring diffusion area and the guard ring area arranged outside the ring diffusion area is made constant, the outer edge portions of the ring diffusion area and the small ring diffusion area having the same electric potential, Since the electric field distribution with the guard ring region becomes uniform, the breakdown voltage of the device does not decrease.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. Hereinafter, a method for manufacturing a MOSFET that is a field effect transistor according to an embodiment of the present invention will be described. In the following, the first conductivity type impurities are N type impurities, and the second conductivity type impurities are P type impurities.

First, a substrate provided with an N ⁺ type substrate body made of silicon and an N ⁻ type epitaxial layer formed on the surface thereof is prepared. A plurality of elements described later can be formed on the substrate. Among the plurality of elements, cross-sectional views for explaining the manufacturing process of one element are shown in FIGS. 1 (a) to 37 (a) and 1 (b) to 37 (b). 1 (a) to 37 (a) are cross-sectional views of a pad region described later, and FIGS. 1 (b) to 37 (b)
Shows a cross-sectional view in a cell region and a peripheral region described later. In FIGS. 1A and 1B, reference numeral 10 indicates a substrate, reference numeral 11 indicates a substrate body, and reference numeral 12 indicates an epitaxial layer.

Next, when the substrate 10 is subjected to thermal oxidation treatment, as shown in FIG.
As shown in (a) and (b), a thermal oxide film 13 made of a silicon oxide film is formed on the surface of the epitaxial layer 12.

Next, a resist solution is applied to the surface of the thermal oxide film 13 to form a resist film, and then patterning is performed.
Reference numeral 61 in FIGS. 3A and 3B shows a patterned resist film.

FIG. 38 shows a plan view of the device in the states shown in FIGS. 3 (a) and 3 (b). 3A shows a sectional view taken along the line AA of FIG. 38, and FIG. 3B shows a sectional view taken along the line BB of FIG. As shown in the plan view of FIG. 38, the patterned resist film 61 has a plurality of openings 51, each opening 51 is formed in a square ring shape, and is arranged concentrically with each other. Here, four openings 51 are formed. Of these, the outermost peripheral opening 51 is arranged so that its outer edge portion is located in the vicinity of the edge defining one element, and the innermost peripheral opening 51 is arranged so as to surround the central portion of one element. ing.

Next, using the resist film 61 as a mask, the thermal oxide film 13 exposed on the bottom surface of the opening 51 of the resist film 61 is etched to remove the resist film 61. The state is shown in FIGS. 4 (a) and 4 (b). Reference numeral 52 in the drawing denotes an opening of the thermal oxide film 13 formed by etching the thermal oxide film 13, and the epitaxial layer 12 is exposed from the bottom of the opening 52.

Next, when the surface of the thermal oxide film 13 is irradiated with a P-type impurity such as boron (B), the P-type impurity is implanted into the bottom surface of the opening 52 of the thermal oxide film 13, and FIGS. As shown in b), the P-type high concentration layer 14 is formed at the bottom of the opening 52.

Next, when the substrate 10 is heat-treated, as shown in FIG.
As shown in (a) and (b), the P-type high-concentration layer 14 is diffused to form four square ring-shaped guard ring regions 15 composed of P-type diffusion regions, and the guard ring is also formed. The surface of the region 15 is covered with the thermal oxide film. The plan shape of these guard ring regions 15 is the resist film 61 described above.
The opening 51 is the same as the opening 51.

Next, as shown in FIGS. 7A and 7B, a patterned resist film 66 is formed on the surface of the thermal oxide film 13. The resist film 66 is arranged on the guard ring region 15 and covers the guard ring region 15.

When the thermal oxide film 13 is etched using the resist film 66 as a mask, the thermal oxide film 13 on the guard ring region 15 is covered with the resist film 66 and is not etched. On the other hand, the guard ring area 15
In the other regions where no is formed, the thermal oxide film 13 is removed and the surface of the epitaxial layer 12 is exposed. After that, the resist film 66 is removed. The state is shown in Fig. 8 (a), (b)
Shown in.

Next, when the substrate 10 is subjected to thermal oxidation treatment, the exposed epitaxial layer 1 as shown in FIGS. 9 (a) and 9 (b).
A thermal oxide film 16 made of a silicon oxide film is formed on the surface of 2.

Next, as shown in FIGS. 10 (a) and 10 (b), a resist film is formed on the surfaces of the thermal oxide films 16 and 13 and patterned to form a groove in the resist film and an opening described later. Form. The planar shape of the resist film is shown in FIG. Note that FIGS. 10A and 10B correspond to the sectional view taken along the line CC and the sectional view taken along the line DD of FIG. 39, respectively.

This groove is a square ring-shaped groove having a constant width, and its outer end portion is located inside by a certain distance from the inner end portion of the innermost guard ring region 15. And a part of the groove goes inside. The groove is shown by reference numeral 251 in FIG.

By this groove 251, the resist film is separated into two pieces. Of these, a resist film located inside the groove 251 (hereinafter referred to as an inner resist film) is indicated by reference numeral 62, and a resist film positioned outside (hereinafter referred to as an outer resist film) is indicated by reference numeral 262.

The outer end portion of the inner resist film 62 is aligned with the inner end portion of the groove 251. On the other hand, the outer resist film 262 has its inner end aligned with the outer end of the groove 251, and the outer end is located inside the edge defining one element, and as a result, one element is formed. Between the defining edge and the outer edge of the outer resist film 262, the thermal oxide film 13 is formed.
The surface of is exposed.

The outer resist film 262 has a rectangular opening 252 in a part of the portion that bulges inward. The groove 251 and the opening 252 have almost the same size in FIGS. 10A and 10B, but the opening 252 is actually larger.

On the other hand, the inner resist film 62 has a comb-shaped opening 53 therein. The opening 53 of the two formed in an elongated respective stem opening 73 _1, 73
₂ , one connection opening 75 and a plurality of branch openings 74
And have.

The ends of a plurality of branch-shaped openings 74 are connected to the two trunk-shaped openings 73 ₁ and 73 ₂ . The connection opening 75 and the respective branch opening 74, the stem opening 73 _1, 73 ₂
Is perpendicular to. The surface of the thermal oxide film 16 is exposed at the bottom of the opening 53.

Then, using the inner resist film 62 and the outer resist film 262 as masks, the thermal oxide films 16 and 13 are formed.
To etch. Then, as shown in FIG.
The thermal oxide film 16 at the portion where the groove 251 is formed is removed to form a rectangular ring-shaped groove 253 at the same position as the rectangular ring-shaped groove 251, and a rectangular opening 252 of the outer resist film 262 is formed. The thermal oxide film 16 at the exposed portion is removed and a rectangular opening 254 is formed at the same position as the opening 252.

Hereinafter, a region outside the outer end of the groove 253 will be referred to as a peripheral region 72, and a region inside the inner end of the groove 251 will be referred to as a cell region 71. Further, as described above, since a part of the groove 251 has entered the inside, a part of the outer resist film 262 bulges inward. The bulged portion will be referred to as a pad region 77 below.

As shown in FIG. 11B, in the cell region 71, the opening 54 having the same pattern as the comb-shaped opening 53 of the inner resist film 62 is formed, and in the peripheral region 72, the edge that defines one element is formed. The thermal oxide film 13 in the vicinity is removed.

These comb-shaped openings 54 and the rectangular openings 2
The epitaxial layer 12 is exposed at the bottoms of the groove 54 and the rectangular ring-shaped groove 253, and in the vicinity of the edge defining one element.

Next, the resist films 62 and 262 are removed, and the thermal oxidation films 16 and 13 are used as masks to irradiate the element formation surface with N-type impurities. Here, phosphorus is used as the N-type impurity, and the dose amount is 2 × 10 ¹³ cm ^-2 .

Then, the N-type impurity is formed in the comb-shaped opening 5.
4, the rectangular opening 254, the bottoms of the rectangular ring-shaped groove 253, and the inside of the epitaxial layer 12 exposed in the vicinity of the edge that defines one element, respectively, as shown in FIG. As shown in (b), the comb-shaped opening 54
And a comb-shaped first implantation region 18 made of an N-type impurity, a rectangular first implantation region 264, and a rectangular ring-shaped opening 254 and a rectangular ring-shaped groove 253, respectively. And a first implant region 263 is formed.

Next, the substrate 10 is heat-treated. here,
The heat treatment is performed at a temperature of 1100 ° C. for 200 minutes. Then, as shown in FIGS. 13A and 13B, the impurities in the first implantation regions 263, 264, and 18 are diffused, and the rectangular first implantation region 264 and the square ring-shaped first implantation region 264 are formed. A rectangular low-resistance region 221, a square ring-shaped low-resistance region 220, and a comb-shaped low-resistance region 20 are formed in the region where the implantation region 263 and the comb-shaped first implantation region 18 are formed, respectively. A thermal oxide film is formed and these low resistance regions 2
21, 220 and 20 are all covered with a thermal oxide film.

Thereafter, as shown in FIGS. 14A and 14B, a patterned resist film 67 is formed on the thermal oxide films 16 and 13.
Formed on the surface of. The plan shape of the resist film 67 is shown in FIG.
Shown in. 14 (a) and 14 (b) are respectively EE of FIG.
It corresponds to the line sectional view and the line FF sectional view. The resist film 67 has an opening 59. The opening 59 is located inside the cell region 71, and is arranged such that the outer end thereof is located inside the inner end of the square ring-shaped low resistance layer 220 by a certain distance.

When the thermal oxide film 16 is etched using the resist film 67 as a mask, the bottom surface of the opening 59 and the groove 43 are etched.
Of the thermal oxide films 16 and 13 respectively located on the bottom surface of the peripheral region 72 are removed, the surface of the outermost peripheral conductive region 5 is exposed in the peripheral region 72, and the epitaxial layer 12 and the comb-shaped low resistance region 20 are exposed in the cell region 71. To do. After that, the resist film 67 is removed. 15A and 15B are sectional views showing the state where the resist film 67 is removed.

Next, an N-type impurity is applied to the element formation surface. Here, phosphorus is used as the N-type impurity, and the dose amount is 2 × 10 ¹² cm ⁻² . As shown in FIGS. 16A and 16B, since the pad region 77 and the guard ring region 15 in the peripheral region 72 are covered with the thick thermal oxide films 16 and 13, respectively, the irradiated N-type impurities are not implanted. .
On the other hand, in the cell region 71, the exposed comb-shaped low resistance region 2 is formed.
0 and the inside of the epitaxial layer 12 are implanted with N-type impurities, and the N-type impurities are implanted into the epitaxial layer 12 in the comb-like low resistance region 20 and its peripheral region. Is formed.

Next, the substrate 1 is formed under the condition that a thermal oxide film is not formed.
0 is heat-treated. Here, the temperature in the nitrogen atmosphere is 1100.
Heat treatment is performed for 500 minutes under the condition of ° C. Then, the impurities contained in the second implantation region 23 are not included in the epitaxial layer 1
2 and the comb-shaped low resistance region 20.

By the way, since the impurities contained in the second implantation region 23 are N-type and the epitaxial layer 12 and the comb-like low resistance region 20 are also N-type, the diffused impurity and the diffused target object. The impurities have the same conductivity type. Even when the comb-shaped low resistance region 20 is formed, the impurity diffused from the comb-shaped first implantation region 18 is N-type and the epitaxial layer 12 is also N-type. The impurities to be diffused and the impurities to be diffused have the same conductivity type.

In these cases, since a PN junction is not formed between the diffused region formed by the diffused impurities and the diffused object, the diffused impurities and the diffused region have the same conductivity type. If, then the diffusion depth cannot be originally specified. Therefore, in this case, the position where the impurity concentration of the diffusion region is double the impurity concentration of the object to be diffused is defined as the diffusion depth of the diffusion region.

At this time, when the second implantation region 23 is diffused, a first high concentration region 24 is formed on the comb-like low resistance region 20 as shown in FIG. 17B, and the epitaxial layer is formed. A second high-concentration region 25 is formed on the surface side of 12.

Assuming that the diffusion depth of the comb-shaped low resistance region 20 is defined at a position where the impurity concentration of the comb-shaped low resistance region 20 is twice as high as that of the epitaxial layer 12, the diffusion depth is defined. That is, it is shallower than the depth from the surface of the epitaxial layer 12 to the boundary surface between the epitaxial layer 12 and the substrate body 11, and the bottom surface of the low resistance region 20 is located above the bottom surface of the epitaxial layer 12.

Further, assuming that the diffusion depth of the second high concentration region 25 is defined at the position where the impurity concentration of the second high concentration region 25 becomes twice the impurity concentration of the epitaxial layer 12, The diffusion depth is shallower than the diffusion depth of the low resistance region 20, and the bottom surface of the second high concentration region 25 is located above the bottom surface of the low resistance region 20.

The diffusion depth of the first high concentration region 24 is equal to the second
Assuming that the diffusion depth is the same as the diffusion depth of the high-concentration region 25, the first high-concentration region 24 is formed in the comb-shaped low-resistance region 20 in which the N-type impurity has already been diffused, and the second implantation region is formed. 23
Since it is configured by further diffusing N-type impurities, the impurity concentration of the first high concentration region 24 is higher than that of the second high concentration region 25.

Next, when the substrate 10 is thermally oxidized, as shown in FIGS. 18A and 18B, the gate insulating film made of a thermal oxide film is formed on the surfaces of the first and second high concentration regions 24 and 25. 27
Are formed, the pad region 77 and the peripheral region 72 are formed.
The film thicknesses of the thermal oxide films 16 and 13 respectively arranged in the above are increased.

Next, polysilicon pre-doped with impurities is deposited by the CVD method. Then, FIG.
As shown in (a) and (b), the gate electrode film 28 is formed on the surface of the gate insulating film 27 in the cell region 71, the peripheral region 72, and the thermal oxide films 13 and 16 arranged in the pad region 77, respectively. Is formed.

Next, after forming a resist film on the surface of the gate electrode film 28, patterning is performed to form a groove and an opening described later in the resist film. The planar shape of the resist film in this state is shown in FIG. 20 (a) and 20 (b) are shown in FIG.
The cross-sectional view taken along the line G-G and the cross-sectional view taken along the line H-H of FIG.

This groove is formed in a square ring shape and has a constant width, and its outer end portion is located outside the outer end portion of the square ring-shaped low resistance layer 221 by a certain distance. Are arranged as follows. The groove is shown in FIG.
Reference numeral 255 in FIG. 41 indicates.

The groove 255 separates the resist film into two pieces. Of these, the inner resist film located inside the groove 255 is indicated by reference numeral 63, and the outer resist film located outside is indicated by reference numeral 263.

The outer resist film 263 has its inner end aligned with the outer end of the groove 255, and the inner resist film 63 is
The outer end of the gate electrode film 28 is aligned with the inner end of the groove 255, and the surface of the gate electrode film 28 is exposed between the peripheral region 72 including the guard ring region 15 and the outer edge of the outer resist film 263. There is. A part of the outer resist film 263 bulges inward, a rectangular opening 256 is provided in a part of the bulged portion, and the surface of the gate electrode film 28 is exposed from the surface of the opening 256. There is.

On the other hand, the inner resist film 63 has an opening 55. The opening 55 has the first planar shape described above.
Like the high-concentration region 24 of FIG.
The comb-shaped first high-concentration region 24 is arranged so as to be positioned outside the outer edge portion by a certain distance. The gate electrode film 28 is exposed at the bottom of the comb-shaped opening 55.

When the gate electrode film 28 is etched by using the resist films 63 and 263 as masks, FIG.
As shown in (a) and (b), the rectangular opening 256, the comb-shaped opening 55, and the gate electrode film 28 at the bottom of the rectangular ring-shaped groove 255 are removed to remove the gate insulating film 27 and the thermal oxide film 16. Is exposed. Next, after removing the resist films 63 and 263, the gate insulating film 27 is formed using the gate electrode film 28 as a mask.
By etching, the rectangular opening 256, the comb-shaped opening 55, and the gate insulating film 27 and the thermal oxide film 16 exposed at the bottom of the square ring-shaped groove 255 are removed.

Next, with the gate electrode film 28 and the gate insulating film 27 as a mask, P-type impurities are applied to the element formation surface. Here, boron is used as the P-type impurity and the dose amount is 2 × 10 ¹³ cm ^-2 . 22 (a), (b)
As shown in FIG. 7, in the cell region 71, the irradiated P-type impurities are exposed to the bottom of the rectangular opening 256, the comb-shaped opening 55, and the square ring-shaped groove 255.
And the second high-concentration region 25 around it, and P is formed on both surface sides of the first and second high-concentration regions 24 and 25.
A comb-shaped third implantation region 31 made of a type impurity is formed. In the pad area 77, the rectangular opening 256 and the groove 2 are formed.
First high concentration regions 220, 221 exposed at the bottom of 55
And the epitaxial layer 12 around it, which is made of P-type impurities at the bottoms of the rectangular opening 256 and the square ring-shaped groove 255, respectively, and has a square ring-shaped planar shape and a rectangular third injection region 231. ₁ , 231 ₂ are formed. On the other hand, since the peripheral region 72 is covered with the thick thermal oxide film 13, no P-type impurities are implanted into the outermost peripheral conductive region 5 and the guard ring region 15.

Next, under the condition that a thermal oxide film is not formed,
The plate 10 is heat treated. Here, at a temperature of 1135 ° C,
It is heat-treated for 400 minutes. Then each third implant region
31, 231₁231₂P-type impurities of each diffuse
However, as shown in FIGS. 23A and 23B, in the cell region 71,
A comb-shaped body region is provided at the position of the comb-shaped third implantation region 31.
32 are formed, while in the pad area 77, square phosphorus is formed.
Box-shaped, rectangular third implantation region 231₁231₂Position of
And a ring diffusion region 232 in the shape of a square ring, respectively.
₁And a rectangular pad diffusion region 232₂Is formed.

Of these, the P-type impurities in the third implantation region 31 of the cell region 71 are the first and second high concentration regions 24,
25, but the diffusion depth of the body region 32 in the second high-concentration region 25 is equal to that of the second high-concentration region 25.
It is shallower than the diffusion depth of. Further, since the N-type impurity concentration of the first high-concentration region 24 is higher than the N-type impurity concentration of the second high-concentration region 25, in the body region 32, the diffusion depth in the first high-concentration region 24 is large. It becomes shallower than the diffusion depth in the second high concentration region 25.

Therefore, in the first high-concentration region 24, even if the P-type impurity is diffused to form the body region 32, the first high-concentration region remains below the body region 32. The edge portion of the body region 32 is laterally diffused,
It sunk into the position below the gate insulating film 27. The body region 32 has a resist film 63 whose planar shape is as described above.
Like the opening 55, it is formed in a comb shape, and only one is arranged in one element. Therefore, the area occupied by the body region 32 inside one element is large.

In FIG. 23 (b), reference numeral 22 indicates a buried region which is a remaining portion of the first high concentration region 24, and the edge of the buried region 22 is the body region 3.
It is located inside the edge of No. 2 and is buried under the body region 32. Such embedded region 22
Are arranged along the bottom of the body region 32 having a comb shape in a plan view, and have a comb shape like the body region 32 in a plan view.

On the other hand, a square ring-shaped ring diffusion region 23.
The first high-concentration region also remains under 2 ₁ and the rectangular pad diffusion region 232 ₂ . Reference numerals 222 and 223 denote embedded regions which are the remaining portions of the first high concentration region 20, and these embedded regions 222 and 22 are shown.
3, the edge ring diffusion region 232 _1, located inside the edge of the pad diffusion regions 232 _2, respectively ring diffusion region 232 _1, in the state embedded under the pad diffusion regions 232 ₂ There is.

The buried regions 222 and 223 are the ring diffusion region 232 ₁ and the pad diffusion region 23, respectively.
The ring diffusion regions 232 ₁ , which are arranged along the bottom of 2 ₂ and have a planar shape of a rectangular shape and a square ring shape, respectively.
It is the same as the pad diffusion regions 232 _2.

In this state, the surfaces of the body region 32, the ring diffusion region 232 ₁ and the pad diffusion region 232 ₂ are exposed, and as shown in FIGS. 24 (a) and 24 (b), the exposed body region is exposed. 32, patterned resist films 64, 264 are formed on the surfaces of the ring diffusion region 232 ₁ , the ring diffusion region 232 _1, and the pad diffusion region 232 ₂ , respectively. Resist film 64,
The planar shape of H.264 is shown in FIG. 24 (a), (b)
42 correspond to the sectional view taken along the line KK and the sectional view taken along the line LL of FIG. 42, respectively.

Of these resist films 64, 264,
As shown in the plan view of FIG. 42, the resist film 64 disposed on the surface of the body region 32 has a comb-like planar shape similar to that of the body region 32, and the outer edge portion thereof has the body region 3.
It is arranged so as to be located inside by a certain distance from the outer edge portion of 2.

A gap 57 is formed between the outer edge of the comb-shaped resist film 64 and the inner end of the gate electrode film 28. The gap 57 has a ring-shaped planar shape, and an outer peripheral edge portion coincides with an edge portion of the gate electrode film 28, and an inner peripheral edge portion coincides with an edge portion of the resist film 64. In the cell region 71, the body region 32 is formed on the bottom surface of the gap 57.
Is exposed. On the other hand, the pad diffusion region 232 ₂
The resist film 264 arranged on the thermal oxide film 13 is disposed on the thermal oxide film 13 and the outermost peripheral conductive region 5, and covers the thermal oxide film 13 and the outermost peripheral conductive region 5.

Next, using the resist films 64 and 264 as masks, the element formation surface is irradiated with N-type impurities.
As shown in (a) and (b), in the cell region 71, N-type impurities are implanted into the surface side of the body region 32 exposed at the bottom surface of the gap 57 to form an N-type impurity implantation region 35.
Here, As is used as the N-type impurity, and the dose amount is 5
It is set to × 10 ¹⁵ cm ^-2 .

Next, after removing the resist films 64, 264, the substrate 10 is heat-treated under the condition that the thermal oxide film is not formed. Here, heat treatment is performed for 10 minutes in a nitrogen atmosphere at a temperature of 1000 ° C. Then, the N-type impurities in the impurity-implanted region 35 are diffused, and the N-type source region 36 is formed on the front surface side of the body region 32, as shown in FIGS.

The edges of the body region 32 and the source region 36 are sunk to the position below the gate insulating film 27 by lateral diffusion as described above. Body area 3
The lateral diffusion amount of 2 is larger than the lateral diffusion amount of the source region 36, and the edge of the source region 36 does not protrude from the edge of the body region 32. A body region 32 remains between the edge. Reference numeral 80 indicates a channel region which is a body region located between the edge of the source region 36 and the edge of the body region 32. The channel region 80 is the gate insulating film 2
7, the gate insulating film 27 and the gate electrode film 28 are disposed above the channel region 80. Then, as shown in FIG. 27 (a), (b) , a gate electrode film 28, a source region 36, a body region 32, and the ring diffusion region 232 _1, CVD method on the surface of the pad diffusion regions 232 ₂ Then, the insulating film 38 is formed.
Here, a silicon oxide film is formed as the insulating film 38.

Next, as shown in FIGS. 28A and 28B, a patterned resist film 65 is formed on the surface of the insulating film 38. The resist film 65 has openings 58 and 258 in the cell region 71 and the pad region 77, respectively.

Of these, the opening 5 arranged in the cell region 71
8 is provided on the surface of the source region 36 and the body region 32 located inside thereof. In addition, the opening 258 disposed in the pad area 77 is formed in the ring diffusion area 232.
_The insulating film 38 is provided on the upper part of the first insulating film 38 and is exposed at the bottom of the openings 58 and 258.

Next, when the insulating film 38 is etched by using the resist film 65 as a mask, the insulating film 38 shown in FIGS.
, The insulating film 38 exposed on the bottom surfaces of the openings 58, 258 is removed, the source region 36 and the body region 32 are exposed on the bottom surface of the opening 58, and the ring diffusion region 232 ₁ is formed on the bottom surface of the opening 258. Is exposed. Next, the resist film 6
5 is removed, and as shown in FIGS. 30A and 30B, a metal film 46 is formed on the entire element formation surface.

Next, as shown in FIGS. 31A and 31B, a patterned resist film 66 is formed on the metal film 46. The resist film 66 has openings 259 and 260 in the peripheral region 72 and the pad region 77, respectively. Of these, the opening 260 of the peripheral region 72 is arranged in a region where the outermost peripheral conductive region 5 is not formed, and the opening 259 of the pad region 77 is formed in the ring diffusion region 232.
_1, is arranged in the region between the pad diffusion regions 232 _2.

When the metal film 46 is etched using the resist film 66 as a mask, the metal film 46 at the bottom of the openings 259 and 260 is removed, and as shown in FIGS. 32 (a) and 32 (b), the pad region 77 is formed. The metal film 46 is the source electrode film 45a
And the gate electrode film 45b, while the source electrode film 4 is formed on the outermost peripheral conductive region 5 in the peripheral region 72.
An outermost peripheral conductive film 98 separated from 5a and the gate electrode film 45b is formed.

Next, after removing the resist film 66 as shown in FIGS. 33 (a) and 33 (b), as shown in FIGS. 34 (a) and 34 (b), the source electrode film 45a and the gate electrode film 45b are removed. When,
A protective film 99 made of a silicon oxide film is formed on the surface of the outermost peripheral conductive film 98 by the CVD method.

Then, as shown in FIGS. 35 (a) and 35 (b),
A patterned resist film 6 is formed on the surface of the protective film 99.
Form 7. The resist film 67 has a rectangular opening 68.
₁ and 68 ₂ and these openings 68 ₁ and 68 ₂ are
They are arranged on the source electrode film 45a and the gate electrode film 45b, respectively.

When the protective film 99 is etched by using the resist film 67 as a mask, the protective film 9 at the bottom of the opening 68 is etched.
9 is removed, and the source electrode film 45a and the gate electrode film 45b are exposed at the bottoms of the openings 68 ₁ and 68 ₂ , respectively.
Of these, the gate electrode film 45b exposed from the opening 68 ₂
Is referred to as a pad electrode film 45c. After that, resist film 6
7 is peeled off. The state is shown in FIGS. 36 (a) and 36 (b).

Next, when a metal film is formed on the surface of the substrate 10 opposite to the element formation surface to form a drain electrode film 91, a MOSFET as shown by reference numeral 1 in FIGS. 37 (a) and 37 (b) is formed. To be done.

This MOSFET 1 has a source electrode film 45.
When a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode film 28 in the state where a is connected to the ground potential and the positive voltage is applied to the drain electrode film 91, the N type inversion layer is formed on the surface of the channel region 80 described above. Are formed, and the surface portion of the second high-concentration region 25 serving as the drain region and the source region 3 are formed.
9 is connected by an inversion layer, and the MOSFET 1 becomes conductive.

Then, a current flows from the source region 39 through the inversion layer to the second high-concentration region 25 serving as the drain region. At this time, since the edge of the buried region 22 is located inside the edge of the body region 32 and the buried region 22 is located at the bottom of the body region 32 as described above, the source region 39 is located in the buried region 22. Not connected to. When the gate electrode film 28 is connected to the ground potential in the conductive state, the inversion layer disappears and the MOSFET 1 is cut off.

The MOSFET 1 of this embodiment described above
In, as described above, in the pad area 77, ring diffusion region 232 _1, the bottom portion of the pad diffusion regions 232 _2, are buried regions 222 and 223 are arranged, the ring diffusion region 232 ₁ and the buried region 222 A ring-shaped PN junction 285 ₁ is formed between them, while the pad diffusion region 232 ₂ and the buried region 2 are formed.
Between 23, a PN junction 285 ₂ having a rectangular planar shape is formed.

The impurity concentration of the buried regions 222 and 223 is higher than that of the epitaxial layer 12, and the breakdown voltage of the ring-shaped PN junction 285 ₁ and the rectangular PN junction 285 ₂ is higher than that of the ring diffusion region 231 ₁ and the epitaxial layer 12. and between the pad diffusion regions 231 ₂ and the epitaxial layer 1
2 is lower than the withstand voltage of the PN junction 286 formed between the two.

Similarly, in the cell region 71, the planar shape is comb-shaped between one body region 32 arranged in a comb shape and one embedded region 22 arranged along the bottom surface thereof. A PN junction 85 is formed. As described above, the impurity concentration of the buried region 22 is higher than that of the second high concentration region 25, and the breakdown voltage of the comb-like PN junction 85 between the buried region 22 and the body region 32 is the second high concentration. P formed between the concentration region 25 and the body region 32
It is lower than the breakdown voltage of the N junction 86.

When a high voltage is applied to the MOSFET 1, the ring-shaped PN junction 285 ₁ formed between the ring diffusion region 232 ₁ and the buried region 222 and the body region 32 and the buried region 22 are formed. Avalanche breakdown occurs together with the formed comb-like PN junction 85.

At this time, since the pad diffusion region 232 ₂ is not connected to any electrodes and is placed at the floating potential, the pad diffusion region 232 ₂ is connected to the rectangular PN junction 285 ₂ between the pad diffusion region 232 ₂ and the buried region 221. No voltage is applied and no avalanche breakdown occurs. In addition, PN junctions 286 ₁ and 286 ₂ formed between the ring diffusion region 232 ₁ and the epitaxial layer 12 and between the pad diffusion region 232 ₂ and the epitaxial layer 12, the second high concentration region 25 and the body. PN junction 86 formed between region 32
Has a high breakdown voltage, these PN junctions 286 ₁ , 28
No avalanche breakdown occurs in 6 ₂ and 86.

Thus, the ring-shaped and comb-shaped PNs are formed.
When the junctions 285 ₁ and 85 are avalanche broken down, a current flows through the comb-shaped PN junctions 285 ₁ and 85. Of these, the ring-shaped PN junction 285 ₁ is connected to the cell region 71.
Is arranged so as to surround the entire comb-shaped body region, and the entire circumference of the ring-shaped PN junction 285 ₁ is longer and wider than the comb-shaped PN junction 85 in the cell region 71. Has also been made larger. Therefore, the ring-shaped PN junction 28
The area of 5 ₁ is larger than the area of the comb-shaped PN junction 85. Therefore, most of the current that flows due to the avalanche breakdown flows to the ring-shaped PN junction 285 ₁ .

Since the ring-shaped PN junction 285 ₁ has a large area, even if a large current flows due to the avalanche breakdown, the current flows uniformly throughout the ring-shaped PN junction 285 ₁ and the large current is concentrated. It doesn't flow. Therefore, the element is less likely to be destroyed as compared with the conventional element in which the current concentration occurs due to the avalanche breakdown.

In the above-described embodiment, one ring-shaped buried region 222 is arranged almost in the entire ring diffusion region 232 ₁ , and the plane shape thereof is the ring diffusion region 23.
It was made to have a ring shape like the planar shape of 2 ₁ ,
The present invention is not limited to this, and for example, a plurality of embedded regions may be provided and each embedded region may be arranged so as to be scattered on the bottom surface of the ring diffusion region 232 _{1 at} a predetermined interval. According to this structure, the area of the PN junction between the ring diffusion region and the buried region is smaller than that in the case where the buried region is arranged along the bottom surface of the ring diffusion region so that the planar shape is a ring shape. Because it gets smaller
It is preferable to arrange the embedded region in a ring shape.

By the way, the breakdown voltage of the element is generally determined by the ring diffusion region 232 ₂ and the buried region 222. In the case of a high breakdown voltage element in particular, the guard ring region 1
The electric field distribution in the vicinity of 5 has a great influence on the breakdown voltage, which is not negligible.

In the embodiment described above, the ring diffusion region 2
Although a part of 32 ₁ has entered the inside, when arranged in this manner, the ring diffusion region 232 ₁ and the inner end of the guard ring region 15 arranged on the innermost side are not constant, so that the ring diffusion region 232. The electric field distribution between the region 232 ₁ and the guard ring region 15 becomes non-uniform, the breakdown voltage decreases, and the effect of improving the breakdown withstand amount also decreases.

Therefore, FIG. 51 shows a plan view and FIG.
You may comprise MOSFET8 which shows a sectional drawing in (a), (b). 50A and 50B correspond to the sectional view taken along the line PP and the sectional view taken along the line QQ of FIG. 51, respectively.

As shown in FIG. 51, this MOSFET 8 has a linear connection region 27 in which a portion of the inside of the ring diffusion region 232 ₁ is diffused with P-type impurities.
As a result, the connection region 270 and the outer peripheral portion of the ring diffusion region 232 ₁ are arranged in a straight line, and a large rectangular ring shape constituted by the outer peripheral portion of the ring diffusion region 232 ₁ and the connection region 270 is formed. A P-type diffusion region is formed, and the interval between the outer edge portion of this rectangular ring-shaped P-type diffusion region and the inner end of the guard ring region 15 arranged at the innermost side becomes constant. Therefore, the ring diffusion region 232
The electric field distribution between ₁ and the guard ring region 15 becomes uniform, the breakdown voltage increases, and the breakdown withstand amount improves.

[0099] Moreover, the connection region 270 described above, with the intruding portion inside the ring diffusion region 232 _1, small rings are in planar shape smaller rectangular ring-shaped diffusion region 2
75 is formed, the inner end of the small ring diffusion region 275, by a predetermined distance from the edge portion of the pad diffusion regions 232 ₂ located inwardly along the bottom surface of the connection region 270,
A buried region 271 formed by diffusing N-type impurities is arranged.

As described above, the pad diffusion region 232 ₂ has a small ring diffusion region 270 having the same potential as the ring diffusion region 232 _1.
Because it is surrounded by the presence of the pad diffusion regions 232 _2, not affect the electric field distribution and the like of the surrounding,
Therefore, the ring diffusion region 232 ₁ and the guard ring region 15
The electric field distribution between and is uniform, and the breakdown voltage does not decrease.

When a high voltage is applied to the MOSFET 8 thus configured, a ring-shaped PN junction 285 formed between the small ring diffusion region 275 having the same potential as the ring diffusion region 232 ₁ and the buried region 271. ₃ and the ring diffusion region 232 ₁ is avalanche breakdown, a current also flows to the small ring diffusion region 270 around the pad diffusion regions 232 ₂ and the small ring buried region 271.

Further, in the above-described embodiment, the embedded region 22 is provided below the body region 32, and the body region 32 is formed.
The PN junction 85 between the buried region 22 and the buried region 22 causes the avalanche breakdown so that the current flows. However, the present invention is not limited to this, and the buried region 22 is provided below the body region 32. You don't have to. In this case, a ring-shaped PN junction 285 formed between the ring diffusion region 232 ₁ and the buried region 222.
Only ₁ avalanche breakdown, ring-shaped P
A current flows only in the N-junction 285 _1, but the current flows uniformly in the ring-shaped PN junction 285 ₁ without concentration, so if the area of the ring-shaped PN junction 285 ₁ is large,
Element destruction due to current concentration does not occur.

In the above, M is used as a field effect transistor.
Although the case of manufacturing the OSFET has been described, FIG.
As shown by reference numeral 2 in (a) and (b), a collector layer 95 is formed by using a P-type silicon single crystal substrate instead of the substrate body 11 made of N ⁺ -type silicon. When a collector electrode 96 which is in ohmic contact with 95 is formed, an IGBT (Insulated gate) using a PN junction is formed.
A bipolar transistor) type field effect transistor can be obtained. This field effect transistor 2 is also included in the present invention.

The present invention also includes a Schottky junction type IGBT element as indicated by reference numeral 3 in FIGS. 44 (a) and 44 (b). In this Schottky junction type IGBT element 3, the substrate body 11 is not provided, and the Schottky electrode film 97 is arranged on the back surface side of the epitaxial layer 12.

This Schottky electrode film 97 forms a Schottky junction with the epitaxial layer 12, and a Schottky diode in which the Schottky electrode film 97 serves as an anode and the epitaxial layer 12 side serves as a cathode is formed. There is.

The source electrode film 45a is connected to the ground potential,
When a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode film 28 with the positive voltage applied to the Schottky electrode film 97, the portion near the surface of the channel region 80 is inverted into N type.

The second high-concentration region 25 is in contact with the epitaxial layer 12, and when the surface portion of the channel region is inverted to N type, the inversion layer connects the source region 36 and the epitaxial layer 12. In this state, the Schottky junction is forward biased, so a current flows from the epitaxial layer 12 side toward the source region 36, and the Schottky junction type IGBT element 3 is brought into a conductive state.

Further, in the above-mentioned embodiment, the ring diffusion region 232 ₁ connected to the source electrode film 45a and the pad diffusion region 232 ₂ placed at the floating potential are provided.
The buried regions 222 and 223 were arranged at the bottoms of the diffusion regions 232 ₁ and 232 ₂ , respectively, but the present invention is not limited to this, and the cross section is indicated by reference numeral 4 in FIGS. 45 (a) and 45 (b). As shown, a large area ring diffusion region 23
It is not necessary to provide only 2 and not form the pad diffusion region placed at the floating potential.

FIG. 49 shows a plan view of the substrate surface in a state where all the thin films formed on the substrate surface have been removed. 45 (a) and 45 (b) respectively correspond to the MM line sectional view and the NN line sectional view of FIG. In this case, as compared with the case where the pad diffusion region is provided, the ring diffusion region 23
2 can be made wide, and the area of the ring diffusion region 232 can be made large. If the buried region 220a is arranged along the bottom of the large ring diffused region 232, the ring diffused region 232 and the buried region 220a are formed.
The area of the ring-shaped PN junction 285 formed between and becomes large, and even if a considerably large current flows due to the avalanche breakdown, the element is not destroyed.

Further, in the above-described embodiment, the cell region 7
Although the comb-shaped body region 32 and the buried region 22 are formed in FIG. 1, the present invention is not limited to this. For example, as shown in the plan view of the cell region in FIG. A plurality of cells 205 may be arranged in the vicinity so as to be separated from each other to form one element 7.

Each cell 205 has its own body region 3
2, the source region 36, the channel region 80, and the buried region 22. In each cell 205, the body region 32, the source region 36, and the channel region 80
The diffusion depth and the impurity concentration of the buried region 22 are the same as those of the element having the comb-shaped body region in plan view.

The source region 36 is formed in a ring shape, the outer edge of which is spaced apart from the edge of the body region 32, and the channel region 80 is located between the outer edge of the source region 36 and the edge of the body region 32. positioned. Embedded area 2
2 has the same shape as the body region 32,
Is located inside.

Although FIG. 46 shows the case where the body regions 32 and the embedding regions 22 have a rectangular plane shape, the plane shapes of the body region 32 and the embedding regions 22 when a plurality of cells 205 are arranged are not limited to this. Instead, it may be formed in a circular shape, a triangular shape, or a hexagonal shape, for example.

In the above embodiment, the first conductivity type in the present invention is N type and the second conductivity type is P type. However, the first and second conductivity types in the present invention are not limited to this. Alternatively, conversely, the first conductivity type may be P type and the second conductivity type may be N type.

[0115]

The device breakdown due to avalanche breakdown is less likely to occur.

[Brief description of drawings]

1A is a first cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention; FIG. 1B is a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention. 1st sectional drawing explaining a process

FIG. 2A is a second cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. FIG. 2B is a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention. Second cross-sectional view illustrating the process

FIG. 3A is a third cross-sectional view illustrating the manufacturing process in the pad region of the field-effect transistor of the example of the invention; FIG. 3B is the manufacturing process in the cell region and the peripheral region of the field-effect transistor of the example of the invention. Third cross-sectional view illustrating the process

FIG. 4A is a fourth cross-sectional view for explaining the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 4B: Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. Fourth cross-sectional view illustrating the process

5A is a fifth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. FIG. 5B: Manufacturing in a cell region and a peripheral region of a field effect transistor of an example of the present invention. Fifth cross-sectional view illustrating the process

6A is a sixth cross-sectional view for explaining the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 6B: Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. 6th sectional view explaining process

7A is a seventh cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor according to an example of the present invention. FIG. 7B is a manufacturing process in a cell region and a peripheral region of a field effect transistor according to an example of the present invention. 7th sectional view explaining process

8A is an eighth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. FIG. 8B: Manufacturing in a cell region and a peripheral region of a field effect transistor of an example of the present invention. Eighth cross-sectional view illustrating the process

9A is a ninth cross-sectional view for explaining the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 9B: Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. 9th sectional view explaining process

10A is a tenth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. FIG. 10B: Manufacturing in a cell region and a peripheral region of a field effect transistor of an example of the present invention. 10th sectional view explaining process

11A is an eleventh cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. FIG. 11B: Manufacturing in a cell region and a peripheral region of a field effect transistor of an example of the present invention. Eleventh cross-sectional view illustrating a process

FIG. 12 (a): A twelfth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. (B): Manufacturing in a cell region and a peripheral region of a field effect transistor of an example of the present invention. 12th cross-sectional view illustrating a process

13A is a thirteenth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. FIG. 13B is a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention. 13th sectional view explaining process

14A is a fourteenth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. FIG. 14B is a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention. Fourteenth cross-sectional view illustrating a process

15A is a fifteenth cross-sectional view for explaining the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 15B: Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. Fifteenth cross-sectional view illustrating a process

16 (a): Sixteenth cross-sectional view explaining the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 16 (b): Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. 16th sectional view explaining a process

FIG. 17A is a seventeenth cross-sectional view illustrating the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 17B: Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. 17th sectional view explaining process

FIG. 18 (a): An eighteenth sectional view for explaining a manufacturing process in a pad region of a field effect transistor of an example of the present invention. (B): Manufacturing in a cell region and a peripheral region of a field effect transistor of an example of the present invention. 18th sectional view explaining a process

19 (a): A nineteenth cross-sectional view illustrating the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 19 (b): Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. 19th sectional view explaining process

FIG. 20 (a): A twentieth cross-sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. (B): Manufacturing in a cell region and a peripheral region of a field effect transistor of an example of the present invention. 20th cross-sectional view illustrating a process

FIG. 21 (a) is a twenty-first sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. FIG. 21 (b): Manufacturing in a cell region and a peripheral region of a field effect transistor of an example of the present invention. 21st sectional view explaining a process

22A is a twenty-second sectional view illustrating a manufacturing process in a pad region of a field effect transistor of an example of the present invention. FIG. 22B is a manufacturing process in a cell region and a peripheral region of a field effect transistor of an example of the present invention. 22nd sectional view explaining a process

23 (a): A twenty-third cross-sectional view illustrating the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 23 (b): Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. 23rd sectional view explaining a process

24 (a): A twenty-fourth cross-sectional view illustrating the manufacturing process in the pad region of the field-effect transistor of the example of the present invention. FIG. 24 (b): Manufacturing in the cell region and the peripheral region of the field-effect transistor of the example of the present invention. 24th cross-sectional view illustrating a process

25 (a): A twenty-fifth cross-sectional view explaining the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 25 (b): Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. 25th sectional view illustrating a step

FIG. 26 (a): A twenty-sixth cross-sectional view explaining the manufacturing process in the pad region of the field effect transistor of the example of the present invention. (B): Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. The 26th sectional view explaining the process

27 (a): A twenty-seventh cross-sectional view illustrating the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 27 (b): Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. The 27th sectional view explaining the process

28 (a): A twenty-eighth cross-sectional view illustrating the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 28 (b): Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. The 28th sectional view explaining the process

29 (a): A twenty-ninth cross-sectional view illustrating the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 29 (b): Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. 29th sectional view explaining a process

30 (a): A thirtieth sectional view illustrating the manufacturing process in the pad region of the field effect transistor of the example of the present invention. FIG. 30 (b): Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. 30th sectional view explaining a process

31A is a 31st cross-sectional view illustrating the manufacturing process in the pad region of the field-effect transistor of the example of the present invention, and FIG. 31B: Manufacturing the cell region and the peripheral region of the field-effect transistor of the example of the present invention. 31st sectional view explaining a process

32A is a thirty-second sectional view illustrating the manufacturing process in the pad region of the field-effect transistor of the example of the invention; FIG. 32B is the manufacturing process in the cell region and the peripheral region of the field-effect transistor of the example of the invention. 32nd sectional view explaining a process

33 (a): A thirty-third cross-sectional view illustrating the manufacturing process in the pad region of the field-effect transistor of the example of the invention, and (b): Manufacturing the cell region and the peripheral region of the field-effect transistor of the example of the invention. 33rd sectional view explaining a process

34 (a): A thirty-fourth cross-sectional view illustrating the manufacturing process in the pad region of the field-effect transistor of the example of the present invention. (B): Manufacturing in the cell region and the peripheral region of the field-effect transistor of the example of the present invention. 34th sectional view explaining a process

FIG. 35 (a): A thirty-fifth sectional view for explaining the manufacturing process in the pad region of the field effect transistor of the example of the present invention. (B): Manufacturing in the cell region and the peripheral region of the field effect transistor of the example of the present invention. 35th sectional view explaining a process

FIG. 36 (a): A thirty-sixth cross-sectional view illustrating the manufacturing process in the pad region of the field-effect transistor of the example of the present invention. (B): Manufacturing in the cell region and the peripheral region of the field-effect transistor of the example of the present invention. 36th sectional view explaining a process

37A is a sectional view showing a structure in a pad region of an example field effect transistor of the present invention; FIG. 37B is a sectional view showing a structure in a cell region and a peripheral region of an example field effect transistor of the present invention.

FIG. 38 is a first plan view illustrating a manufacturing process of the field effect transistor of the example of the present invention.

FIG. 39 is a second plan view illustrating the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 40 is a third plan view illustrating the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 41 is a fourth plan view explaining the manufacturing process of the field effect transistor of the example of the present invention.

FIG. 42 is a fifth plan view illustrating the manufacturing process of the field effect transistor of the example of the present invention.

43 (a): a sectional view for explaining the structure in the pad region of an IGBT field effect transistor which is another example of the present invention (b): an IGBT field effect transistor which is another example of the present invention Cross-sectional view for explaining the structure in the cell region and the peripheral region of

FIG. 44 (a) is another example of the present invention, and is a cross-sectional view for explaining the structure in the pad region of the IGBT field effect transistor using the Schottky junction. (B): Another example of the present invention. FIG. 3 is a cross-sectional view illustrating a structure in a cell region and a peripheral region of an IGBT field effect transistor using a Schottky junction.

45 (a): Another example of the present invention, which is a cross-sectional view for explaining the structure in the pad region of the field effect transistor having a structure in which only the ring diffusion region is provided (b): Another example of the present invention FIG. 4 is a cross-sectional view illustrating a structure in a cell region and a peripheral region of a field effect transistor having a structure where only a ring diffusion region is provided.

FIG. 46 is a view for explaining a field effect transistor in which a plurality of cells are arranged in a matrix, which is another example of the present invention.

FIG. 47 is a cross-sectional view illustrating the structure of a conventional field effect transistor.

FIG. 48 is a plan view illustrating an arrangement state of conventional field effect transistors.

FIG. 49 is another example of the present invention, which is a plan view for explaining the state of the substrate surface of a field effect transistor having a structure in which only a ring diffusion region is provided.

50 (a): Another example of the present invention, which is a cross-sectional view for explaining the structure in the pad region of the field effect transistor having a structure in which the pad diffusion region is surrounded by the small ring diffusion region (b): the present invention FIG. 6 is another example of a cross-sectional view illustrating a structure in a cell region and a peripheral region of a field effect transistor having a structure where a pad diffusion region is surrounded by a small ring diffusion region

51 is another example of the present invention, which is a plan view for explaining a field effect transistor having a structure in which a pad diffusion region is surrounded by a small ring diffusion region. FIG.

[Explanation of symbols]

11 ... Substrate body 12 ... Epitaxial layers 22, 222, 223 ... Embedded region 27 ... Gate insulating film 28 ... Gate electrode film 32 ... Body region 45 ... Source electrode film 80 ... Channel region 91 ... Drain electrode film 232 ₁ ...... Ring diffusion region 232 ₂ ...... Pad diffusion region 150 ...... Surface protective film

Claims (11)

[Claims] 1. A drain layer of the first conductivity type, an insulating film disposed on one surface of the drain layer, a pad electrode film disposed on the insulating film and having a bonding wire fixed thereto, the pad electrode Located in the drain layer below the membrane,
A field effect transistor having a pad diffusion region including a diffusion region formed by diffusing an impurity of a second conductivity type opposite to the first conductivity type from one surface side of the drain layer. A field effect transistor having a first conductivity type buried region located inside the drain layer at a position deeper than the bottom surface of the pad diffusion region and in contact with the bottom surface of the pad diffusion region. 2. A body region formed of a diffusion region formed by diffusing impurities of the second conductivity type from one surface side of the drain layer, and impurities of the first conductivity type from the surface side of the body region. And a source region disposed inside the body region, which is a part of the body region and is between the edge of the body region and the edge of the source region. A channel region located at, a gate insulating film disposed at least on the surface of the channel region, a gate electrode film disposed on the surface of the gate insulating film, and a source electrode film connected to the source region. When the surface of the channel region is inverted by a voltage applied to the gate electrode film having a cell, the drain layer and the source region located outside the channel region are separated from each other. Field effect transistor of claim 1, wherein the gas-connected. 3. The field effect transistor according to claim 1, wherein an outer peripheral edge portion of the embedded region is located inside an outer peripheral edge portion of the pad diffusion region. 4. The field effect transistor according to claim 1, wherein the impurity concentration of the buried region is higher than the impurity concentration of the drain layer. 5. A drain layer of the first conductivity type, a body region formed by diffusing impurities of the second conductivity type from one surface side of the drain layer, and a body region from the surface side of the body region. A source region formed of a diffusion region formed by diffusing one conductivity type impurity, the source region being disposed inside the body region, a part of the body region, and an edge of the body region and the source region. A channel region located between an edge of the gate region, a gate insulating film disposed on at least the surface of the channel region, a gate electrode film disposed on the surface of the gate insulating film, and disposed on the surface of the source region. When the surface of the channel region is inverted by the voltage applied to the gate electrode film, the cell including the source electrode film and the drain layer located outside the channel region and the front surface are formed. A field effect transistor electrically connected to the source region, wherein the drain region is formed by diffusing impurities of the second conductivity type from one surface side, and the planar shape is a ring shape, The ring diffusion region is arranged such that the inner end portion is located outside the cell and is connected to the source electrode film, and the ring diffusion region is located inside the drain layer at a position deeper than the bottom surface of the ring diffusion region. A buried region of the first conductivity type in contact with the bottom surface of the diffusion region, an insulating film disposed on one surface of the drain layer, and an insulating film disposed outside the region surrounded by the ring diffusion region. , A field effect transistor having a pad electrode film to which a bonding wire is fixed. 6. The field effect transistor according to claim 5, wherein the buried region is located at a center of a bottom surface of the ring diffusion region in a width direction. 7. The field effect transistor according to claim 1, wherein the pad diffusion region is connected to the source region. 8. A drain layer of a first conductivity type, a body region formed by diffusing impurities of a second conductivity type from one surface side of the drain layer, and a body region from a surface side of the body region. A source region, which is formed of a diffusion region formed by diffusing one conductivity type impurity, is disposed inside the body region, and a portion of the body region, the edge of the body region and the source region. A channel region located between the edge of the gate region, a gate insulating film disposed on at least the surface of the channel region, a gate electrode film disposed on the surface of the gate insulating film, and a gate region disposed on the surface of the source region. When the surface of the channel region is inverted by the voltage applied to the gate electrode film, the cell including the source electrode film and the drain layer located outside the channel region and the front surface are formed. A field effect transistor electrically connected to the source region, wherein the drain layer is formed by diffusing impurities of the second conductivity type from one surface side thereof, and has a ring-shaped planar shape. The ring diffusion region is arranged such that the inner end portion is located outside the cell and is connected to the source electrode film, and the ring diffusion region is located inside the drain layer at a position deeper than the bottom surface of the ring diffusion region. A buried region of the first conductivity type in contact with the bottom surface of the diffusion region, an insulating film disposed on one surface of the drain layer, and an insulating film disposed outside the region surrounded by the ring diffusion region. A pad electrode film to which a bonding wire is fixed, and a pad electrode film located below the pad electrode film in the drain layer,
A pad diffusion region formed of a diffusion region formed by diffusing an impurity of a second conductivity type opposite to the first conductivity type from the one surface side of the drain layer; and one surface of the drain layer A small ring diffusion region that is formed by diffusing the second conductivity type impurity from the side, has a ring-shaped planar shape, and is connected to the ring diffusion region; and is deeper than a bottom surface of the small ring diffusion region. A first conductivity type small ring buried region located inside the drain layer at a position and in contact with the bottom surface of the small ring diffusion region, wherein the pad diffusion region is arranged in a portion surrounded by the small ring diffusion region. Field effect transistor. 9. A semiconductor substrate of a first conductivity type is provided on a surface of the drain layer opposite to a surface on which the insulating film is located, and the surface of the semiconductor substrate is ohmic-connected to the semiconductor substrate. The field effect transistor according to claim 1, further comprising a drain electrode. 10. A collector layer of the second conductivity type is provided on a surface of the drain layer opposite to a surface on which the insulating film is located, and the collector layer surface is in ohmic contact with the semiconductor substrate. The field effect transistor according to claim 1, further comprising a collector electrode. 11. The Schottky electrode forming a Schottky junction with the drain layer is provided on a surface of the drain layer opposite to a surface on which the insulating film is located. A field effect transistor according to item 1.