CA1091360A - Dispositifs d'interconnexion normalises - Google Patents
Dispositifs d'interconnexion normalisesInfo
- Publication number
- CA1091360A CA1091360A CA268,155A CA268155A CA1091360A CA 1091360 A CA1091360 A CA 1091360A CA 268155 A CA268155 A CA 268155A CA 1091360 A CA1091360 A CA 1091360A
- Authority
- CA
- Canada
- Prior art keywords
- pattern
- connection
- connection pattern
- patterns
- normalized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15900475A JPS6058588B2 (ja) | 1975-12-29 | 1975-12-29 | 半導体装置の製造方法 |
JP159004/75 | 1975-12-29 | ||
JP2141976A JPS52104883A (en) | 1976-02-28 | 1976-02-28 | Manufacture for semiconductor device |
JP2141876A JPS5858809B2 (ja) | 1976-02-28 | 1976-02-28 | 半導体装置の製造方法 |
JP21418/76 | 1976-02-28 | ||
JP21419/76 | 1976-02-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1091360A true CA1091360A (fr) | 1980-12-09 |
Family
ID=27283424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA268,155A Expired CA1091360A (fr) | 1975-12-29 | 1976-12-17 | Dispositifs d'interconnexion normalises |
Country Status (3)
Country | Link |
---|---|
CA (1) | CA1091360A (fr) |
DE (1) | DE2659246C2 (fr) |
ES (1) | ES454684A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1102009A (fr) * | 1977-09-06 | 1981-05-26 | Algirdas J. Gruodis | Schema de circuit integre a regions distinctes pour le cablage et pour les circuits actifs |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1282177A (en) * | 1968-09-25 | 1972-07-19 | Hughes Aircraft Co | Integrated circuit interconnections |
-
1976
- 1976-12-17 CA CA268,155A patent/CA1091360A/fr not_active Expired
- 1976-12-28 DE DE19762659246 patent/DE2659246C2/de not_active Expired
- 1976-12-29 ES ES454684A patent/ES454684A1/es not_active Expired
Also Published As
Publication number | Publication date |
---|---|
ES454684A1 (es) | 1978-03-16 |
DE2659246A1 (de) | 1977-07-07 |
DE2659246C2 (de) | 1982-04-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4197555A (en) | Semiconductor device | |
EP0739540B1 (fr) | Procede de fabrication d'un circuit tridimensionnel | |
EP0250269A2 (fr) | Dispositif semi-conducteur à circuit intégré ayant une structure d'interconnexion améliorée | |
US5436198A (en) | Method of manufacturing semiconductor device having straight wall bump | |
EP0339315B1 (fr) | Méthode de fabrication de dispositifs semi-conducteurs protégés contre la contamination due aux étapes de configuration | |
EP0210397A1 (fr) | Circuits LSI, adaptables à des méthodes de configurations personnalisées | |
CN113707540B (zh) | 晶圆对准曝光方法及半导体器件 | |
CA1091360A (fr) | Dispositifs d'interconnexion normalises | |
US6127733A (en) | Check pattern for via-hole opening examination | |
KR19990022039A (ko) | 반도체칩및반도체칩의제조방법 | |
KR100410812B1 (ko) | 반도체장치의제조방법 | |
US6218263B1 (en) | Method of forming an alignment key on a semiconductor wafer | |
JP2993339B2 (ja) | 半導体装置の製造方法 | |
JPS61140149A (ja) | 半導体集積回路装置 | |
JP3634596B2 (ja) | 半導体装置 | |
JPS60105251A (ja) | 半導体集積回路 | |
KR970005700B1 (ko) | 반도체 소자의 중첩오차 방지방법 | |
JP2911980B2 (ja) | 半導体集積回路装置 | |
US3561108A (en) | Alternated orientation of chips on semiconductor wafers | |
KR100258204B1 (ko) | 화합물 반도체 소자의 공중 배선 형성방법 | |
KR100273677B1 (ko) | 다중금속배선구조를갖는반도체장치제조방법 | |
JPS6058588B2 (ja) | 半導体装置の製造方法 | |
JPH04318957A (ja) | 半導体集積回路 | |
JPH03136351A (ja) | 半導体集積回路 | |
JPS6079746A (ja) | 半導体装置及びその機能変更方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MKEX | Expiry |