BRPI0514899A - comutador cmos de baixa tensão com novo esquema de intensificação de relógio - Google Patents

comutador cmos de baixa tensão com novo esquema de intensificação de relógio

Info

Publication number
BRPI0514899A
BRPI0514899A BRPI0514899-5A BRPI0514899A BRPI0514899A BR PI0514899 A BRPI0514899 A BR PI0514899A BR PI0514899 A BRPI0514899 A BR PI0514899A BR PI0514899 A BRPI0514899 A BR PI0514899A
Authority
BR
Brazil
Prior art keywords
pmos
nmos
voltage
vgnd
low voltage
Prior art date
Application number
BRPI0514899-5A
Other languages
English (en)
Inventor
Mustafa Keskin
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BRPI0514899A publication Critical patent/BRPI0514899A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

COMUTADOR CMOS DE BAIXA TENSãO COM NOVO ESQUEMA DE INTENSIFICAçãO DE RELóGIO São descritos um método e um equipamento para intensificar as tensões de porta de um comutador CMOS utilizado em um circuito integrado designado a um processo CMOS sub-micrométrico. O comutador CMOS é acoplado a nós Ventrada e Vsaída e contém portas PMOS e NMOS. Dois circuitos de intensificação são utilizados para alterar a tensão nas portas PMOS e NMOS, respectivamente. A tensão na porta NMOS é intensificada de V~ DD~ até (V~ DD~ + K x V~ DD~). A tensão na porta PMOS é diminuída de VGND até (VGND - k x VGND). O fator k é escolhido de modo que Vsaída possa ser amostrada através de toda a faixa de Ventrada = V~ GND~ a V~ DD~, mesmo no caso de V~ DD~ se aproximar da soma dos valores absolutos das tensões limite dos respectivos transistores PMOS e NMOS.
BRPI0514899-5A 2004-09-03 2005-08-30 comutador cmos de baixa tensão com novo esquema de intensificação de relógio BRPI0514899A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US60694204P 2004-09-03 2004-09-03
US10/986,630 US7268610B2 (en) 2004-09-03 2004-11-12 Low-voltage CMOS switch with novel clock boosting scheme
PCT/US2005/032064 WO2006029286A1 (en) 2004-09-03 2005-08-30 Low-voltage cmos switch with novel clock boosting scheme

Publications (1)

Publication Number Publication Date
BRPI0514899A true BRPI0514899A (pt) 2008-06-24

Family

ID=35613776

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0514899-5A BRPI0514899A (pt) 2004-09-03 2005-08-30 comutador cmos de baixa tensão com novo esquema de intensificação de relógio

Country Status (5)

Country Link
US (1) US7268610B2 (pt)
KR (1) KR20070088563A (pt)
BR (1) BRPI0514899A (pt)
IL (1) IL181688A0 (pt)
WO (1) WO2006029286A1 (pt)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7199641B2 (en) * 2005-06-30 2007-04-03 Silicon Laboratories Inc. Selectably boosted control signal based on supply voltage
US7304530B2 (en) * 2005-06-30 2007-12-04 Silicon Laboratories Inc. Utilization of device types having different threshold voltages
US8492796B2 (en) * 2007-03-13 2013-07-23 Infineon Technologies Ag MuGFET switch
KR100941843B1 (ko) 2008-04-14 2010-02-11 삼성모바일디스플레이주식회사 인버터 및 이를 구비한 표시장치
US8461880B2 (en) * 2009-04-02 2013-06-11 Silicon Labs Spectra, Inc. Buffer with an output swing created using an over-supply voltage
US8493255B2 (en) 2011-02-24 2013-07-23 Texas Instruments Incorporated High speed, high voltage multiplexer
US20130049847A1 (en) * 2011-08-31 2013-02-28 Analog Devices, Inc. Bootstrapping techniques for control of cmos transistor switches
JP2021527358A (ja) 2018-06-11 2021-10-11 ザ・トラスティーズ・オブ・コロンビア・ユニバーシティ・イン・ザ・シティ・オブ・ニューヨーク 複数の相殺パスを含むサーキュレータ用の回路及び方法
WO2020150745A1 (en) 2019-01-19 2020-07-23 The Trustees Of Columbia University In The City Of New York Magnetic-free non-reciprocal circuits based on sub-harmonic spatio-temporal conductance modulation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5558776A (en) 1978-10-26 1980-05-01 Seiko Instr & Electronics Ltd Boosting circuit
JP4354056B2 (ja) * 1999-10-12 2009-10-28 株式会社 沖マイクロデザイン 半導体集積回路
US6404237B1 (en) * 2000-12-29 2002-06-11 Intel Corporation Boosted multiplexer transmission gate
US7233194B2 (en) 2003-01-06 2007-06-19 Texas Instruments Incorporated CMOS voltage booster circuits
DE60308346D1 (de) * 2003-07-03 2006-10-26 St Microelectronics Srl Mit Spannungserhöhung betriebene Abtastschaltung und zugehöriges Ansteuerverfahren

Also Published As

Publication number Publication date
WO2006029286A1 (en) 2006-03-16
US20060049865A1 (en) 2006-03-09
IL181688A0 (en) 2007-07-04
KR20070088563A (ko) 2007-08-29
US7268610B2 (en) 2007-09-11

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2166 DE 10/07/2012.