BR9915456A - Sistema de processamento de vetor tipo de memória compartilhada e método para compartilhá-la - Google Patents

Sistema de processamento de vetor tipo de memória compartilhada e método para compartilhá-la

Info

Publication number
BR9915456A
BR9915456A BR9915456-0A BR9915456A BR9915456A BR 9915456 A BR9915456 A BR 9915456A BR 9915456 A BR9915456 A BR 9915456A BR 9915456 A BR9915456 A BR 9915456A
Authority
BR
Brazil
Prior art keywords
cpu
vector processing
instruction
vector
cpus
Prior art date
Application number
BR9915456-0A
Other languages
English (en)
Inventor
Satoshi Nakazato
Original Assignee
Nec Corparation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corparation filed Critical Nec Corparation
Publication of BR9915456A publication Critical patent/BR9915456A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8092—Array of vector units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

"SISTEMA DE PROCESSAMENTO DE VETOR TIPO MEMóRIA COMPARTILHADA E MéTODO PARA CONTROLE DO MESMO". Um sistema de processamento de vetores do tipo de memória compartilhada no qual CPUs são conectadas por um barramento para transferir uma instrução de processamento de vetor gerada a partir de cada CPU para cada CPU e as respectivas CPUs são agrupadas em uma CPU mestra que emite uma instrução de processamento de vetor para outra CPU e CPUs escravas operando como um canal de suprimento de multivetores em sincronismo com uma unidade de processamento de vetor na CPU mestra, a CPU mestra incluindo uma unidade de controle de acesso de memória para emitir a citada instrução de processamento de vetor com informação de CPU de fonte emissora ligada para identificar uma CPU de fonte emissora, e transferir a citada instrução para todas as CPUs inlcuindo sua própria CPU através de um barramento, e a CPU mestra e a CPU escrava incluindo uma unidde de controle de instrução de processamento de vetor para comparar informação de CPU de fonte emissora contida em uma instrução de processamento de vetor e informação de CPU mestra determinada em sua própria CPU e conduzir emissão de instrução baseada na instrução de processamento de vetor quando as informações concordarem entre si e invalidar a instrução de processamento de vetor quando as informações falharem em concordar entre si.
BR9915456-0A 1998-12-15 1999-12-15 Sistema de processamento de vetor tipo de memória compartilhada e método para compartilhá-la BR9915456A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP37541098A JP3344345B2 (ja) 1998-12-15 1998-12-15 共有メモリ型ベクトル処理システムとその制御方法及びベクトル処理の制御プログラムを格納する記憶媒体

Publications (1)

Publication Number Publication Date
BR9915456A true BR9915456A (pt) 2001-08-07

Family

ID=18505478

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9915456-0A BR9915456A (pt) 1998-12-15 1999-12-15 Sistema de processamento de vetor tipo de memória compartilhada e método para compartilhá-la

Country Status (6)

Country Link
US (1) US6782468B1 (pt)
EP (1) EP1011052A3 (pt)
JP (1) JP3344345B2 (pt)
AU (1) AU765469B2 (pt)
BR (1) BR9915456A (pt)
CA (1) CA2292230A1 (pt)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3564445B2 (ja) 2001-09-20 2004-09-08 松下電器産業株式会社 プロセッサ、コンパイル装置及びコンパイル方法
US7577816B2 (en) * 2003-08-18 2009-08-18 Cray Inc. Remote translation mechanism for a multinode system
US6877832B2 (en) * 2003-03-11 2005-04-12 Hewlett-Packard Development Company, L.P. Instruction architecture using two instruction stacks
US7735088B1 (en) 2003-08-18 2010-06-08 Cray Inc. Scheduling synchronization of programs running as streams on multiple processors
US7543133B1 (en) * 2003-08-18 2009-06-02 Cray Inc. Latency tolerant distributed shared memory multiprocessor computer
US7334110B1 (en) 2003-08-18 2008-02-19 Cray Inc. Decoupled scalar/vector computer architecture system and method
US7366873B1 (en) 2003-08-18 2008-04-29 Cray, Inc. Indirectly addressed vector load-operate-store method and apparatus
US7437521B1 (en) 2003-08-18 2008-10-14 Cray Inc. Multistream processing memory-and barrier-synchronization method and apparatus
US7421565B1 (en) * 2003-08-18 2008-09-02 Cray Inc. Method and apparatus for indirectly addressed vector load-add -store across multi-processors
US7519771B1 (en) 2003-08-18 2009-04-14 Cray Inc. System and method for processing memory instructions using a forced order queue
US7743223B2 (en) * 2003-08-18 2010-06-22 Cray Inc. Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system
US8307194B1 (en) 2003-08-18 2012-11-06 Cray Inc. Relaxed memory consistency model
US7937557B2 (en) * 2004-03-16 2011-05-03 Vns Portfolio Llc System and method for intercommunication between computers in an array
US7478769B1 (en) 2005-03-09 2009-01-20 Cray Inc. Method and apparatus for cooling electronic components
US7904695B2 (en) 2006-02-16 2011-03-08 Vns Portfolio Llc Asynchronous power saving computer
US20070074008A1 (en) * 2005-09-28 2007-03-29 Donofrio David D Mixed mode floating-point pipeline with extended functions
EP1821211A3 (en) * 2006-02-16 2008-06-18 Technology Properties Limited Cooperative multitasking method in a multiprocessor system
US7913069B2 (en) 2006-02-16 2011-03-22 Vns Portfolio Llc Processor and method for executing a program loop within an instruction word
EP1821199B1 (en) * 2006-02-16 2012-07-04 VNS Portfolio LLC Execution of microloop computer instructions received from an external source
US7904615B2 (en) 2006-02-16 2011-03-08 Vns Portfolio Llc Asynchronous computer communication
GB2484899A (en) * 2010-10-21 2012-05-02 Bluwireless Tech Ltd Data processing system with a plurality of data processing units and a task-based scheduling scheme
GB2484902A (en) * 2010-10-21 2012-05-02 Bluwireless Tech Ltd Data processing system with a plurality of data processing units each with scalar processor, vector processor array, parity and FFT accelerator units
WO2012052773A1 (en) * 2010-10-21 2012-04-26 Bluwireless Technology Limited Data processing systems
GB2484901A (en) * 2010-10-21 2012-05-02 Bluwireless Tech Ltd Data processing unit with scalar processor, vector processor array, parity and FFT accelerator units
GB2484905B (en) * 2010-10-21 2014-07-16 Bluwireless Tech Ltd Data processing systems
GB2484907B (en) * 2010-10-21 2014-07-16 Bluwireless Tech Ltd Data processing systems
GB2484904A (en) * 2010-10-21 2012-05-02 Bluwireless Tech Ltd Data processing system with a plurality of data processing units and a task-based scheduling scheme
US9285793B2 (en) 2010-10-21 2016-03-15 Bluewireless Technology Limited Data processing unit including a scalar processing unit and a heterogeneous processor unit
GB2484906A (en) * 2010-10-21 2012-05-02 Bluwireless Tech Ltd Data processing unit with scalar processor and vector processor array
US9727526B2 (en) 2011-01-25 2017-08-08 Nxp Usa, Inc. Apparatus and method of vector unit sharing
EP2757468A1 (en) * 2013-01-22 2014-07-23 Siemens Aktiengesellschaft Apparatus and method for managing a software development and maintenance system
US10140122B2 (en) 2015-09-23 2018-11-27 Hanan Potash Computer processor with operand/variable-mapped namespace
US10095641B2 (en) 2015-09-23 2018-10-09 Hanan Potash Processor with frames/bins structure in local high speed memory
US10067878B2 (en) 2015-09-23 2018-09-04 Hanan Potash Processor with logical mentor
US10061511B2 (en) 2015-09-23 2018-08-28 Hanan Potash Computing device with frames/bins structure, mentor layer and plural operand processing
TWI588658B (zh) * 2015-10-20 2017-06-21 旺宏電子股份有限公司 I/o匯流排共用記憶體系統
US11093286B2 (en) * 2016-04-26 2021-08-17 Hanan Potash Computing device with resource manager and civilware tier
CA3194408A1 (en) 2017-04-21 2018-10-25 Zenimax Media Inc. Player input motion compensation by anticipating motion vectors
CN110889081A (zh) * 2019-11-25 2020-03-17 国网河南省电力公司驻马店供电公司 一种新能源并网系统谐波谐振快速获取方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59106075A (ja) 1982-12-10 1984-06-19 Hitachi Ltd デ−タ処理システム
JPS6310263A (ja) 1986-07-02 1988-01-16 Hitachi Ltd ベクトル処理装置
US5010477A (en) * 1986-10-17 1991-04-23 Hitachi, Ltd. Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations
JP2900359B2 (ja) * 1986-10-30 1999-06-02 株式会社日立製作所 マルチプロセッサシステム
JPH06103494B2 (ja) 1986-11-18 1994-12-14 株式会社日立製作所 ベクトル処理装置の制御方式
JP2646113B2 (ja) 1988-07-23 1997-08-25 富士通株式会社 マシンチェック処理方法および装置
JP2658397B2 (ja) 1989-06-13 1997-09-30 日本電気株式会社 マルチプロセッサシステム
JPH0346078A (ja) 1989-07-13 1991-02-27 Fujitsu Ltd ベクトル処理システム
JPH0484256A (ja) 1990-07-26 1992-03-17 Fujitsu Ltd 使用権切換え制御方式
US5734921A (en) * 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
US5828894A (en) * 1990-11-13 1998-10-27 International Business Machines Corporation Array processor having grouping of SIMD pickets
US5361367A (en) * 1991-06-10 1994-11-01 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors
CA2073516A1 (en) * 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
JP3502216B2 (ja) * 1995-07-13 2004-03-02 富士通株式会社 情報処理装置
US5737328A (en) * 1995-10-04 1998-04-07 Aironet Wireless Communications, Inc. Network communication system with information rerouting capabilities
US5822606A (en) * 1996-01-11 1998-10-13 Morton; Steven G. DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word

Also Published As

Publication number Publication date
US6782468B1 (en) 2004-08-24
JP3344345B2 (ja) 2002-11-11
EP1011052A2 (en) 2000-06-21
CA2292230A1 (en) 2000-06-15
JP2000181878A (ja) 2000-06-30
AU6450899A (en) 2000-06-22
EP1011052A3 (en) 2007-01-03
AU765469B2 (en) 2003-09-18

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Legal Events

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B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

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B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 DE RPI 1999 DE 28/04/2009.