BR9910924A - Processo de sintonizar uma largura de banda de circuito fechado travado em fase a um nìvel desejado, aparelho, e, artigo de manufatura - Google Patents
Processo de sintonizar uma largura de banda de circuito fechado travado em fase a um nìvel desejado, aparelho, e, artigo de manufaturaInfo
- Publication number
- BR9910924A BR9910924A BR9910924-7A BR9910924A BR9910924A BR 9910924 A BR9910924 A BR 9910924A BR 9910924 A BR9910924 A BR 9910924A BR 9910924 A BR9910924 A BR 9910924A
- Authority
- BR
- Brazil
- Prior art keywords
- phase
- locked loop
- bandwidth
- loop bandwidth
- locked
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
- H03L7/0898—Details of the current generators the source or sink current values being variable
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Processing Of Color Television Signals (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Electrotherapy Devices (AREA)
Abstract
''PROCESSO DE SINTONIZAR UMA LARGURA DE BANDA DE CIRCUITO FECHADO TRAVADO EM FASE A UM NìVEL DESEJADO, APARELHO, E, ARTIGO DE MANUFATURA'' Uma largura de banda de um circuito fechado travado em fase é sintonizada a um nível desejado operando o circuito fechado travado em fase numa condição travada em fase a uma primeira freq³ência e aplicar uma resposta de etapa ao circuito fechado travado em fase levando o circuito fechado travado em fase a principiar a travar com uma segunda freq³ência que é diferente da primeira freq³ência. Um parâmetro é então detectado que está relacionado com a resposta de etapa aplicada e que é indicativo do fato da largura de banda do circuito fechado travado em fase estar ao nível desejado. A Largura de banda do circuito fechado travado em fase é ajustada, e as etapas de operar à primeira freq³ência, aplicar a resposta de etapa, detectar o parâmetro e ajustar a largura de banda do circuito fechado travado em fase são repetidas até a largura de banda do circuito fechado travado em fase estar ao nível desejado. Onde o nível de largura de banda desejado para sintonia não é a largura de banda operacional, a largura de banda do circuito fechado travado em fase é adicionalmente ajustada por um valor predeterminado, desse modo sintonizando a largura de banda do circuito fechado travado em fase com um nível operacional. A resposta de etapa pode ser aplicada alterando um valor de divisão de freq³ência em um trajeto de realimentação do circuito fechado travado em fase. O parâmetro detectado pode ser um salto de pulso, que indica a largura de banda do circuito fechado travado em fase ainda não está ao nível da largura de banda desejada.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/090,914 US6049255A (en) | 1998-06-05 | 1998-06-05 | Tuning the bandwidth of a phase-locked loop |
PCT/SE1999/000953 WO1999065146A1 (en) | 1998-06-05 | 1999-06-02 | Method for tuning the bandwidth of a phase-locked loop |
Publications (2)
Publication Number | Publication Date |
---|---|
BR9910924A true BR9910924A (pt) | 2001-03-06 |
BR9910924B1 BR9910924B1 (pt) | 2013-02-05 |
Family
ID=22224938
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BRPI9910924-7A BR9910924B1 (pt) | 1998-06-05 | 1999-06-02 | processo para sintonizar largura de banda de um pll a um nÍvel desejado, e, respectivo aparelho. |
Country Status (15)
Country | Link |
---|---|
US (1) | US6049255A (pt) |
EP (1) | EP1095457B1 (pt) |
JP (1) | JP4455757B2 (pt) |
KR (1) | KR100624599B1 (pt) |
CN (1) | CN1315080B (pt) |
AT (1) | ATE315286T1 (pt) |
AU (1) | AU754639B2 (pt) |
BR (1) | BR9910924B1 (pt) |
DE (1) | DE69929339T2 (pt) |
EE (1) | EE200000708A (pt) |
HK (1) | HK1040841B (pt) |
IL (1) | IL140068A0 (pt) |
MY (1) | MY118898A (pt) |
PL (1) | PL195271B1 (pt) |
WO (1) | WO1999065146A1 (pt) |
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US6459253B1 (en) * | 2000-09-05 | 2002-10-01 | Telefonaktiebolaget Lm Ericsson (Publ) | Bandwidth calibration for frequency locked loop |
JP3696077B2 (ja) * | 2000-11-13 | 2005-09-14 | シャープ株式会社 | 電圧変換回路及びこれを備えた半導体集積回路装置 |
US7003065B2 (en) * | 2001-03-09 | 2006-02-21 | Ericsson Inc. | PLL cycle slip detection |
KR100725935B1 (ko) * | 2001-03-23 | 2007-06-11 | 삼성전자주식회사 | 프랙셔널-앤 주파수 합성기용 위상 고정 루프 회로 |
US6603329B1 (en) | 2001-08-29 | 2003-08-05 | Altera Corporation | Systems and methods for on-chip impedance termination |
US6806733B1 (en) | 2001-08-29 | 2004-10-19 | Altera Corporation | Multiple data rate interface architecture |
US7200769B1 (en) | 2001-08-29 | 2007-04-03 | Altera Corporation | Self-compensating delay chain for multiple-date-rate interfaces |
US7167023B1 (en) | 2001-08-29 | 2007-01-23 | Altera Corporation | Multiple data rate interface architecture |
US6946872B1 (en) | 2003-07-18 | 2005-09-20 | Altera Corporation | Multiple data rate interface architecture |
US6798237B1 (en) | 2001-08-29 | 2004-09-28 | Altera Corporation | On-chip impedance matching circuit |
US7382838B2 (en) * | 2001-09-17 | 2008-06-03 | Digeo, Inc. | Frequency drift compensation across multiple broadband signals in a digital receiver system |
US6812732B1 (en) | 2001-12-04 | 2004-11-02 | Altera Corporation | Programmable parallel on-chip parallel termination impedance and impedance matching |
US6836144B1 (en) | 2001-12-10 | 2004-12-28 | Altera Corporation | Programmable series on-chip termination impedance and impedance matching |
US7109744B1 (en) | 2001-12-11 | 2006-09-19 | Altera Corporation | Programmable termination with DC voltage level control |
US6812734B1 (en) | 2001-12-11 | 2004-11-02 | Altera Corporation | Programmable termination with DC voltage level control |
US6768955B2 (en) * | 2002-05-17 | 2004-07-27 | Sun Microsystems, Inc. | Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump |
FR2840469A1 (fr) * | 2002-05-28 | 2003-12-05 | Koninkl Philips Electronics Nv | Boucle a verrouillage de phase |
US6836167B2 (en) * | 2002-07-17 | 2004-12-28 | Intel Corporation | Techniques to control signal phase |
GB0220616D0 (en) * | 2002-09-05 | 2002-10-16 | Koninkl Philips Electronics Nv | Improvements relating to phase-lock loops |
US6788155B2 (en) * | 2002-12-31 | 2004-09-07 | Intel Corporation | Low gain phase-locked loop circuit |
US7023285B2 (en) * | 2003-07-15 | 2006-04-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Self-calibrating controllable oscillator |
US6888369B1 (en) | 2003-07-17 | 2005-05-03 | Altera Corporation | Programmable on-chip differential termination impedance |
US6859064B1 (en) | 2003-08-20 | 2005-02-22 | Altera Corporation | Techniques for reducing leakage current in on-chip impedance termination circuits |
US6888370B1 (en) | 2003-08-20 | 2005-05-03 | Altera Corporation | Dynamically adjustable termination impedance control techniques |
US6998922B2 (en) * | 2003-09-08 | 2006-02-14 | Broadcom Corp. | Phase locked loop modulator calibration techniques |
US7236753B2 (en) * | 2003-12-29 | 2007-06-26 | Intel Corporation | Direct outphasing modulator |
US7234069B1 (en) | 2004-03-12 | 2007-06-19 | Altera Corporation | Precise phase shifting using a DLL controlled, multi-stage delay chain |
US7126399B1 (en) | 2004-05-27 | 2006-10-24 | Altera Corporation | Memory interface phase-shift circuitry to support multiple frequency ranges |
US7123051B1 (en) | 2004-06-21 | 2006-10-17 | Altera Corporation | Soft core control of dedicated memory interface hardware in a programmable logic device |
US7030675B1 (en) | 2004-08-31 | 2006-04-18 | Altera Corporation | Apparatus and method for controlling a delay chain |
US7218155B1 (en) | 2005-01-20 | 2007-05-15 | Altera Corporation | Techniques for controlling on-chip termination resistance using voltage range detection |
US7221193B1 (en) | 2005-01-20 | 2007-05-22 | Altera Corporation | On-chip termination with calibrated driver strength |
JP4638806B2 (ja) * | 2005-03-29 | 2011-02-23 | ルネサスエレクトロニクス株式会社 | 位相同期ループ回路、オフセットpll送信機、通信用高周波集積回路及び無線通信システム |
US7405633B2 (en) * | 2005-07-18 | 2008-07-29 | Tellabs Reston, Inc. | Methods and apparatus for loop bandwidth control for a phase-locked loop |
US7679397B1 (en) | 2005-08-05 | 2010-03-16 | Altera Corporation | Techniques for precision biasing output driver for a calibrated on-chip termination circuit |
CN100446392C (zh) * | 2006-04-27 | 2008-12-24 | 电子科技大学 | 一种脉冲跨周期调制开关稳压电源控制器 |
US7881401B2 (en) * | 2006-11-17 | 2011-02-01 | Infineon Technologies Ag | Transmitter arrangement and signal processing method |
US8483985B2 (en) * | 2007-01-05 | 2013-07-09 | Qualcomm, Incorporated | PLL loop bandwidth calibration |
US7995697B2 (en) * | 2007-06-18 | 2011-08-09 | Infineon Technologies Ag | Polar modulation / one-point frequency modulation with flexible reference frequency |
DE602008005794D1 (de) * | 2007-11-02 | 2011-05-05 | St Ericsson Sa | Pll-kalibration |
US7737739B1 (en) * | 2007-12-12 | 2010-06-15 | Integrated Device Technology, Inc. | Phase step clock generator |
KR101201116B1 (ko) | 2010-08-17 | 2012-11-13 | 성균관대학교산학협력단 | 동적 루프 대역을 갖는 위상고정루프 및 동적 루프 대역을 사용하여 기준신호에 동기하는 출력신호를 생성하는 방법 |
CN105610434B (zh) * | 2016-02-26 | 2018-08-10 | 西安紫光国芯半导体有限公司 | 一种自适应的延迟锁相环 |
CN112362976B (zh) * | 2020-11-10 | 2024-04-26 | 张国俊 | 在线实时电缆参数测试系统 |
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US4771249A (en) * | 1987-05-26 | 1988-09-13 | Motorola, Inc. | Phase locked loop having a filter with controlled variable bandwidth |
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US5448763A (en) * | 1993-11-09 | 1995-09-05 | Motorola | Apparatus and method for operating a phase locked loop frequency synthesizer responsive to radio frequency channel spacing |
US5703539A (en) * | 1993-12-17 | 1997-12-30 | Motorola, Inc. | Apparatus and method for controlling the loop bandwidth of a phase locked loop |
US5631587A (en) * | 1994-05-03 | 1997-05-20 | Pericom Semiconductor Corporation | Frequency synthesizer with adaptive loop bandwidth |
-
1998
- 1998-06-05 US US09/090,914 patent/US6049255A/en not_active Expired - Lifetime
-
1999
- 1999-05-26 MY MYPI99002083A patent/MY118898A/en unknown
- 1999-06-02 DE DE69929339T patent/DE69929339T2/de not_active Expired - Lifetime
- 1999-06-02 AU AU46678/99A patent/AU754639B2/en not_active Expired
- 1999-06-02 AT AT99930067T patent/ATE315286T1/de not_active IP Right Cessation
- 1999-06-02 EP EP99930067A patent/EP1095457B1/en not_active Expired - Lifetime
- 1999-06-02 CN CN998093327A patent/CN1315080B/zh not_active Expired - Lifetime
- 1999-06-02 WO PCT/SE1999/000953 patent/WO1999065146A1/en active IP Right Grant
- 1999-06-02 BR BRPI9910924-7A patent/BR9910924B1/pt not_active IP Right Cessation
- 1999-06-02 PL PL99346360A patent/PL195271B1/pl unknown
- 1999-06-02 JP JP2000554054A patent/JP4455757B2/ja not_active Expired - Lifetime
- 1999-06-02 EE EEP200000708A patent/EE200000708A/xx unknown
- 1999-06-02 KR KR1020007013682A patent/KR100624599B1/ko not_active IP Right Cessation
- 1999-06-02 IL IL14006899A patent/IL140068A0/xx not_active IP Right Cessation
-
2002
- 2002-03-19 HK HK02102103.8A patent/HK1040841B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1095457A1 (en) | 2001-05-02 |
HK1040841A1 (en) | 2002-06-21 |
WO1999065146A1 (en) | 1999-12-16 |
ATE315286T1 (de) | 2006-02-15 |
JP2002518869A (ja) | 2002-06-25 |
PL195271B1 (pl) | 2007-08-31 |
AU4667899A (en) | 1999-12-30 |
MY118898A (en) | 2005-02-28 |
AU754639B2 (en) | 2002-11-21 |
HK1040841B (zh) | 2011-02-18 |
CN1315080B (zh) | 2010-06-23 |
DE69929339T2 (de) | 2006-09-07 |
CN1315080A (zh) | 2001-09-26 |
PL346360A1 (en) | 2002-02-11 |
EP1095457B1 (en) | 2006-01-04 |
DE69929339D1 (de) | 2006-03-30 |
BR9910924B1 (pt) | 2013-02-05 |
KR20010052536A (ko) | 2001-06-25 |
JP4455757B2 (ja) | 2010-04-21 |
EE200000708A (et) | 2002-04-15 |
KR100624599B1 (ko) | 2006-09-18 |
IL140068A0 (en) | 2002-02-10 |
US6049255A (en) | 2000-04-11 |
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Legal Events
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B06A | Patent application procedure suspended [chapter 6.1 patent gazette] | ||
B09A | Decision: intention to grant [chapter 9.1 patent gazette] | ||
B09X | Republication of the decision to grant [chapter 9.1.3 patent gazette] |
Free format text: REPUBLICACAO DA PUBLICACAO DE DEFERIMENTO FEITA NA RPI NO 2176 DE 18/09/2012 POR TER SIDO EFETUADA COM INCORRECAO. |
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B16A | Patent or certificate of addition of invention granted [chapter 16.1 patent gazette] |
Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 05/02/2013, OBSERVADAS AS CONDICOES LEGAIS. |
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B21A | Patent or certificate of addition expired [chapter 21.1 patent gazette] |
Free format text: PATENTE EXTINTA EM 05/02/2023. |