BR9811564A - Processo para fabricação de um módulo de chip - Google Patents

Processo para fabricação de um módulo de chip

Info

Publication number
BR9811564A
BR9811564A BR9811564-2A BR9811564A BR9811564A BR 9811564 A BR9811564 A BR 9811564A BR 9811564 A BR9811564 A BR 9811564A BR 9811564 A BR9811564 A BR 9811564A
Authority
BR
Brazil
Prior art keywords
chip carrier
chip module
manufacturing
fixing section
given distance
Prior art date
Application number
BR9811564-2A
Other languages
English (en)
Inventor
Frank Pueschner
Juergen Fischer
Erik Heinemann
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=7837429&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=BR9811564(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of BR9811564A publication Critical patent/BR9811564A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Credit Cards Or The Like (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

Patente de Invenção: <B>"PROCESSO PARA FABRICAçãO DE UM MóDULO DE CHIP"<D>. Em um processo para a fabricação de um módulo de chip, depois de estampagem de um suporte de chip (1), a distância (a) entre o segmento de fixação de suporte de chip (6) e os segmentos de contato de suporte de chip (4) é reduzida, por um processo de cunhagem realizado ao menos na região próxima à fenda, para uma medida impedindo a passagem de fluxo da massa de fundição (5).
BR9811564-2A 1997-07-30 1998-07-21 Processo para fabricação de um módulo de chip BR9811564A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19732915A DE19732915C1 (de) 1997-07-30 1997-07-30 Verfahren zur Herstellung eines Chipmoduls
PCT/DE1998/002046 WO1999006947A1 (de) 1997-07-30 1998-07-21 Verfahren zur herstellung eines chipmoduls

Publications (1)

Publication Number Publication Date
BR9811564A true BR9811564A (pt) 2000-09-12

Family

ID=7837429

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9811564-2A BR9811564A (pt) 1997-07-30 1998-07-21 Processo para fabricação de um módulo de chip

Country Status (12)

Country Link
US (1) US6472250B1 (pt)
EP (1) EP0998724B1 (pt)
JP (1) JP3490680B2 (pt)
KR (1) KR100366678B1 (pt)
CN (1) CN1207688C (pt)
AT (1) ATE233418T1 (pt)
BR (1) BR9811564A (pt)
DE (2) DE19732915C1 (pt)
ES (1) ES2193553T3 (pt)
RU (1) RU2181504C2 (pt)
UA (1) UA48314C2 (pt)
WO (1) WO1999006947A1 (pt)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8088386B2 (en) * 1998-03-20 2012-01-03 Genentech, Inc. Treatment of complement-associated disorders
JP3876953B2 (ja) * 1998-03-27 2007-02-07 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP3664045B2 (ja) * 2000-06-01 2005-06-22 セイコーエプソン株式会社 半導体装置の製造方法
DE10202727A1 (de) * 2002-01-24 2003-08-21 Infineon Technologies Ag Trägersubstrat für ein Chipmodul, Chipmodul und Chipkarte
EP1380634B1 (de) * 2002-07-09 2007-08-15 Clariant Produkte (Deutschland) GmbH Oxidationsstabilisierte Schmieradditive für hochentschwefelte Brennstofföle
US7400049B2 (en) * 2006-02-16 2008-07-15 Stats Chippac Ltd. Integrated circuit package system with heat sink
RU2414749C1 (ru) * 2008-08-08 2011-03-20 Вячеслав Олегович Долгих Персональный носитель данных
ES2439508T3 (es) * 2011-08-25 2014-01-23 Textilma Ag Módulo de chip RFID
CN104600172A (zh) * 2014-09-10 2015-05-06 广东长盈精密技术有限公司 倒装芯片型led支架及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5122860A (en) * 1987-08-26 1992-06-16 Matsushita Electric Industrial Co., Ltd. Integrated circuit device and manufacturing method thereof
JPH01106456A (ja) 1987-10-19 1989-04-24 Matsushita Electric Ind Co Ltd 半導体集積回路装置
FR2636453B1 (fr) * 1988-09-14 1992-01-17 Sgs Thomson Microelectronics Procede d'encapsulation de circuits-integres notamment pour cartes a puces
FR2659157B2 (fr) 1989-05-26 1994-09-30 Lemaire Gerard Procede de fabrication d'une carte dite carte a puce, et carte obtenue par ce procede.
US5028741A (en) * 1990-05-24 1991-07-02 Motorola, Inc. High frequency, power semiconductor device
KR940010548B1 (ko) * 1991-12-05 1994-10-24 삼성전자 주식회사 반도체 리드 프레임
DE4336501A1 (de) * 1993-10-26 1995-04-27 Giesecke & Devrient Gmbh Verfahren zur Herstellung von Ausweiskarten mit elektronischen Modulen
DE4443767A1 (de) * 1994-12-08 1996-06-13 Giesecke & Devrient Gmbh Elektronisches Modul und Datenträger mit elektrischem Modul
DE19513797A1 (de) * 1995-04-11 1996-10-24 Siemens Ag Verfahren zum Herstellen eines Trägerelementes und Vorrichtung zur Durchführung des Verfahrens

Also Published As

Publication number Publication date
DE19732915C1 (de) 1998-12-10
CN1207688C (zh) 2005-06-22
DE59807325D1 (de) 2003-04-03
JP2001512289A (ja) 2001-08-21
US6472250B1 (en) 2002-10-29
ATE233418T1 (de) 2003-03-15
KR100366678B1 (ko) 2003-01-09
RU2181504C2 (ru) 2002-04-20
EP0998724B1 (de) 2003-02-26
JP3490680B2 (ja) 2004-01-26
ES2193553T3 (es) 2003-11-01
KR20010022252A (ko) 2001-03-15
WO1999006947A1 (de) 1999-02-11
UA48314C2 (uk) 2002-08-15
CN1265759A (zh) 2000-09-06
EP0998724A1 (de) 2000-05-10

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A, 8A E 9A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1909 DE 07/08/2007.