WO2000000929A3 - Chipmodul zum einbau in einen chipkartenträger sowie verfahren zu dessen herstellung - Google Patents

Chipmodul zum einbau in einen chipkartenträger sowie verfahren zu dessen herstellung Download PDF

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Publication number
WO2000000929A3
WO2000000929A3 PCT/DE1999/001744 DE9901744W WO0000929A3 WO 2000000929 A3 WO2000000929 A3 WO 2000000929A3 DE 9901744 W DE9901744 W DE 9901744W WO 0000929 A3 WO0000929 A3 WO 0000929A3
Authority
WO
WIPO (PCT)
Prior art keywords
chip
installation
card carrier
production
semiconductor chip
Prior art date
Application number
PCT/DE1999/001744
Other languages
English (en)
French (fr)
Other versions
WO2000000929A2 (de
Inventor
Frank Pueschner
Erik Heinemann
Original Assignee
Siemens Ag
Frank Pueschner
Erik Heinemann
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Frank Pueschner, Erik Heinemann filed Critical Siemens Ag
Publication of WO2000000929A2 publication Critical patent/WO2000000929A2/de
Publication of WO2000000929A3 publication Critical patent/WO2000000929A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Theoretical Computer Science (AREA)
  • Die Bonding (AREA)

Abstract

Ein Chipmodul (1) zum Einbau in einen Chipkartenträger weist einen Halbleiterchip (5) sowie ein als Metallschicht ausgebildetes Leadframe (2) auf. Zwischen Metallschicht und Halbleiterchip (5) ist eine Schicht aus Klebstoff (11) vorgesehen, der in nicht-erhärtetem Zustand fließfähig ist und sich aufgrund einer Kapillarwirkung ausbreitet. Der Halbleiterchip (5) ist mit einer sich vom Leadframe (2) aus erstreckenden Hotmelt-Klebstoffschicht (7) bedeckt.
PCT/DE1999/001744 1998-06-26 1999-06-15 Chipmodul zum einbau in einen chipkartenträger sowie verfahren zu dessen herstellung WO2000000929A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19828653.8 1998-06-26
DE19828653A DE19828653A1 (de) 1998-06-26 1998-06-26 Chipmodul zum Einbau in einen Chipkartenträger sowie Verfahren zu dessen Herstellung

Publications (2)

Publication Number Publication Date
WO2000000929A2 WO2000000929A2 (de) 2000-01-06
WO2000000929A3 true WO2000000929A3 (de) 2000-03-16

Family

ID=7872189

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/001744 WO2000000929A2 (de) 1998-06-26 1999-06-15 Chipmodul zum einbau in einen chipkartenträger sowie verfahren zu dessen herstellung

Country Status (2)

Country Link
DE (1) DE19828653A1 (de)
WO (1) WO2000000929A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2805639B1 (fr) * 2000-02-29 2002-05-24 Schlumberger Systems & Service Procede de fixation d'un module a un corps de carte
DE10016135A1 (de) * 2000-03-31 2001-10-18 Infineon Technologies Ag Gehäusebaugruppe für ein elektronisches Bauteil
DE10111028A1 (de) * 2001-03-07 2002-09-19 Infineon Technologies Ag Chipkartenmodul
DE10139395A1 (de) * 2001-08-10 2003-03-06 Infineon Technologies Ag Kontaktierung von Halbleiterchips in Chipkarten

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4143456A (en) * 1976-06-28 1979-03-13 Citizen Watch Commpany Ltd. Semiconductor device insulation method
US5232962A (en) * 1991-10-09 1993-08-03 Quantum Materials, Inc. Adhesive bonding composition with bond line limiting spacer system
DE4325458A1 (de) * 1993-07-29 1995-02-09 Orga Bond Technik Gmbh Trägerelement für einen IC-Baustein

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD214721A1 (de) * 1983-04-15 1984-10-17 Funkwerk Erfurt Veb K Montage-anordnung fuer halbleiterbauelemente
US5214307A (en) * 1991-07-08 1993-05-25 Micron Technology, Inc. Lead frame for semiconductor devices having improved adhesive bond line control
JP3825475B2 (ja) * 1995-06-30 2006-09-27 株式会社 東芝 電子部品の製造方法
JP3689159B2 (ja) * 1995-12-01 2005-08-31 ナミックス株式会社 導電性接着剤およびそれを用いた回路
DE19622684A1 (de) * 1996-06-05 1997-12-11 Siemens Ag Verfahren zur Herstellung mechanisch fester Klebstoffverbindungen zwischen Oberflächen
DE19651862A1 (de) * 1996-12-13 1998-06-18 Bosch Gmbh Robert Verfahren zum Reflowlöten von mit SMD-Bauelementen bestückten Leiterplatten

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4143456A (en) * 1976-06-28 1979-03-13 Citizen Watch Commpany Ltd. Semiconductor device insulation method
US5232962A (en) * 1991-10-09 1993-08-03 Quantum Materials, Inc. Adhesive bonding composition with bond line limiting spacer system
DE4325458A1 (de) * 1993-07-29 1995-02-09 Orga Bond Technik Gmbh Trägerelement für einen IC-Baustein

Also Published As

Publication number Publication date
WO2000000929A2 (de) 2000-01-06
DE19828653A1 (de) 2000-01-05

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