BR9807450A - Corretor de base de tempo de saìda, processo de correção de base de tempo de saìda e dispositivo de vìdeo - Google Patents

Corretor de base de tempo de saìda, processo de correção de base de tempo de saìda e dispositivo de vìdeo

Info

Publication number
BR9807450A
BR9807450A BR9807450-4A BR9807450A BR9807450A BR 9807450 A BR9807450 A BR 9807450A BR 9807450 A BR9807450 A BR 9807450A BR 9807450 A BR9807450 A BR 9807450A
Authority
BR
Brazil
Prior art keywords
time base
video
signal
output time
asynchronous
Prior art date
Application number
BR9807450-4A
Other languages
English (en)
Inventor
Jeroen H C J Stessen
Antonius H H J Nillesen
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of BR9807450A publication Critical patent/BR9807450A/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/93—Regeneration of the television signal or of selected parts thereof
    • H04N5/95—Time-base error compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Television Signal Processing For Recording (AREA)
  • Details Of Television Scanning (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

"CORRETOR DE BASE DE TEMPO DE SAìDA, PROCESSO DE CORREçãO DE BASE DE TEMPO DE SAìDA E DISPOSITIVO DE VìDEO". Um corretor de base de tempo de saída converte vídeo amostrado ortogonal (VS) em vídeo amostrado assíncrono (VOS) com valores de amostra assíncronos ocorrendo em instantes de relógio (TC) de um sinal de relógio (CLK). O vídeo amostrado assíncrono (VOS) é exibido sobre uma tela de exibição de um dispositivo de vídeo (DD). Um oscilador de tempo discreto (DTO) de um circuito em anel de retenção de fase (PLL) de tempo discreto fornece um sinal de base de tempo (OS). O circuito em anel de retenção de fase (PLL) de tempo discreto determina uma diferença de fase (PE) entre o sinal de base de tempo (OS) e instantes de referência (FB) indicando uma temporização de uma deflexão de linha do dispositivo de vídeo (DD) para obter o sinal de base de tempo (OS) sendo sincronizado com os instantes de referência (FB). O sinal de base de tempo (OS) controla um conversor de taxa de amostra (SRC) de tal maneira que os valores de vídeo assíncronos (VOS) que ocorrem nos instantes de relógio (TC) são interpolados do vídeo amostrado ortogonal (VS) pelo conversor de taxa de amostrada (SRC) de tal maneira que o sinal de vídeo é exibido na posição correta sobre a tela de exibição. No coretor de base de tempo de saída de acordo com a invenção todos os circuitos são incrementados por sinais de relógio (CLK) se originando de um e mesmo gerador de sinais de relógio (OSC).
BR9807450-4A 1997-12-22 1998-12-07 Corretor de base de tempo de saìda, processo de correção de base de tempo de saìda e dispositivo de vìdeo BR9807450A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP97204066 1997-12-22
EP98200912 1998-03-23
PCT/IB1998/001962 WO1999033267A2 (en) 1997-12-22 1998-12-07 Output timebase corrector

Publications (1)

Publication Number Publication Date
BR9807450A true BR9807450A (pt) 2000-04-25

Family

ID=26147198

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9807450-4A BR9807450A (pt) 1997-12-22 1998-12-07 Corretor de base de tempo de saìda, processo de correção de base de tempo de saìda e dispositivo de vìdeo

Country Status (10)

Country Link
US (1) US6297849B1 (pt)
EP (1) EP0962095B1 (pt)
JP (1) JP4277938B2 (pt)
KR (1) KR100604103B1 (pt)
CN (1) CN1135839C (pt)
BR (1) BR9807450A (pt)
DE (1) DE69804431T2 (pt)
ES (1) ES2175818T3 (pt)
MY (1) MY132970A (pt)
WO (1) WO1999033267A2 (pt)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6542150B1 (en) * 1996-06-28 2003-04-01 Cirrus Logic, Inc. Method and apparatus for asynchronous display of graphic images
DE10046920C2 (de) * 2000-09-21 2003-08-14 Siemens Ag Verfahren zum gesteuerten Einsynchronisieren auf ein nicht stabiles Taktsystem und hiermit korrespondierende Empfangseinheit
GB0212430D0 (en) * 2002-05-29 2002-07-10 Snell & Wilcox Ltd Video signal processing
US7605867B1 (en) * 2003-05-20 2009-10-20 Pixelworks, Inc. Method and apparatus for correction of time base errors
US7701512B1 (en) 2003-05-20 2010-04-20 Pixelworks, Inc. System and method for improved horizontal and vertical sync pulse detection and processing
US7365796B1 (en) 2003-05-20 2008-04-29 Pixelworks, Inc. System and method for video signal decoding using digital signal processing
US7304688B1 (en) 2003-05-20 2007-12-04 Pixelworks, Inc. Adaptive Y/C separator
US7532254B1 (en) 2003-05-20 2009-05-12 Pixelworks, Inc. Comb filter system and method
US7420625B1 (en) 2003-05-20 2008-09-02 Pixelworks, Inc. Fuzzy logic based adaptive Y/C separation system and method
EP1634374B1 (en) * 2003-06-04 2006-10-04 Koninklijke Philips Electronics N.V. Bit-detection arrangement and apparatus for reproducing information
US7567641B2 (en) * 2004-06-16 2009-07-28 Cirrus Logic, Inc. Sample rate conversion systems with an independent internal oscillator
CN100397356C (zh) * 2004-12-17 2008-06-25 上海环达计算机科技有限公司 Pci测试卡及其测试方法
US7280930B2 (en) * 2005-02-07 2007-10-09 Lecroy Corporation Sequential timebase
US7649569B2 (en) * 2005-05-24 2010-01-19 Texas Instruments Incorporated Time base correction in video systems

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4011241B4 (de) * 1990-04-06 2005-06-02 Micronas Gmbh Digitale Fernsehsignalverarbeitungsschaltung mit orthogonalem Ausgangstakt
DE59010510D1 (de) 1990-06-30 1996-10-24 Itt Ind Gmbh Deutsche Digitale Phasenregelungsschleife
DE4102993A1 (de) 1991-02-01 1992-08-06 Philips Patentverwaltung Schaltungsanordnung zur zeitbasis-transformation eines digitalen bildsignals
TW221083B (pt) 1992-06-26 1994-02-11 Philips Nv
GB2268656B (en) * 1992-07-03 1995-10-18 British Broadcasting Corp Synchronising signal separator
US5335074A (en) * 1993-02-08 1994-08-02 Panasonic Technologies, Inc. Phase locked loop synchronizer for a resampling system having incompatible input and output sample rates
US5404173A (en) * 1993-03-10 1995-04-04 Brooktree Corporation Method to synchronize video modulation using a constant time base
US5574407A (en) * 1993-04-20 1996-11-12 Rca Thomson Licensing Corporation Phase lock loop with error consistency detector
BE1007909A3 (nl) 1993-12-24 1995-11-14 Philips Electronics Nv Niet-geheeltallige vertraging.
US5600379A (en) * 1994-10-13 1997-02-04 Yves C. Faroudia Television digital signal processing apparatus employing time-base correction
FR2742926B1 (fr) * 1995-12-22 1998-02-06 Alsthom Cge Alcatel Procede et dispositif de preparation de faces de laser
EP0835583B1 (en) 1996-04-26 2002-01-09 Koninklijke Philips Electronics N.V. Spline waveform generation
DE69814822T2 (de) * 1997-12-22 2004-04-08 Koninklijke Philips Electronics N.V. Zeitdiskreter phasenregelkreis

Also Published As

Publication number Publication date
KR100604103B1 (ko) 2006-07-26
CN1135839C (zh) 2004-01-21
WO1999033267A2 (en) 1999-07-01
ES2175818T3 (es) 2002-11-16
JP4277938B2 (ja) 2009-06-10
JP2001513303A (ja) 2001-08-28
KR20000075604A (ko) 2000-12-26
US6297849B1 (en) 2001-10-02
CN1253695A (zh) 2000-05-17
EP0962095A2 (en) 1999-12-08
WO1999033267A3 (en) 1999-09-02
DE69804431D1 (de) 2002-05-02
EP0962095B1 (en) 2002-03-27
MY132970A (en) 2007-10-31
DE69804431T2 (de) 2002-12-12

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 10A , 11A E 12A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2073 DE 28/09/2010.