BR9102549A - Controlador de acesso a memoria para controlar acesso de uma fonte de solicitacao selecionada a uma memoria principal e sistema multiprocessador - Google Patents

Controlador de acesso a memoria para controlar acesso de uma fonte de solicitacao selecionada a uma memoria principal e sistema multiprocessador

Info

Publication number
BR9102549A
BR9102549A BR919102549A BR9102549A BR9102549A BR 9102549 A BR9102549 A BR 9102549A BR 919102549 A BR919102549 A BR 919102549A BR 9102549 A BR9102549 A BR 9102549A BR 9102549 A BR9102549 A BR 9102549A
Authority
BR
Brazil
Prior art keywords
source
memory
multiprocessor system
main memory
access
Prior art date
Application number
BR919102549A
Other languages
English (en)
Inventor
Ikuo Yamada
Tadashi Hara
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Publication of BR9102549A publication Critical patent/BR9102549A/pt

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • AHUMAN NECESSITIES
    • A47FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47CCHAIRS; SOFAS; BEDS
    • A47C7/00Parts, details, or accessories of chairs or stools
    • A47C7/62Accessories for chairs
    • A47C7/68Arm-rest tables ; or back-rest tables
    • A47C7/70Arm-rest tables ; or back-rest tables of foldable type

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
BR919102549A 1990-06-11 1991-06-11 Controlador de acesso a memoria para controlar acesso de uma fonte de solicitacao selecionada a uma memoria principal e sistema multiprocessador BR9102549A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2150065A JPH0444136A (ja) 1990-06-11 1990-06-11 メモリアクセス制御装置

Publications (1)

Publication Number Publication Date
BR9102549A true BR9102549A (pt) 1991-10-08

Family

ID=15488750

Family Applications (1)

Application Number Title Priority Date Filing Date
BR919102549A BR9102549A (pt) 1990-06-11 1991-06-11 Controlador de acesso a memoria para controlar acesso de uma fonte de solicitacao selecionada a uma memoria principal e sistema multiprocessador

Country Status (5)

Country Link
EP (1) EP0465847B1 (pt)
JP (1) JPH0444136A (pt)
BR (1) BR9102549A (pt)
CA (1) CA2044207C (pt)
DE (1) DE69127782T2 (pt)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11262936B2 (en) 2015-10-30 2022-03-01 Sony Corporation Memory controller, storage device, information processing system, and memory control method

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5537555A (en) * 1993-03-22 1996-07-16 Compaq Computer Corporation Fully pipelined and highly concurrent memory controller
US5761720A (en) * 1996-03-15 1998-06-02 Rendition, Inc. Pixel engine pipeline processor data caching mechanism
US7013305B2 (en) 2001-10-01 2006-03-14 International Business Machines Corporation Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange
WO2014178846A1 (en) * 2013-04-30 2014-11-06 Hewlett-Packard Development Company, L.P. Coalescing memory access requests

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6049952B2 (ja) * 1981-03-24 1985-11-06 富士通株式会社 メモリ制御装置のビジ−制御方式
JPS5899857A (ja) * 1981-12-09 1983-06-14 Fujitsu Ltd パイプライン処理方式のアクセス処理装置
JPS616746A (ja) * 1984-06-21 1986-01-13 Fujitsu Ltd 部分書込み制御方式
US4773041A (en) * 1986-06-02 1988-09-20 Unisys Corporation System for executing a sequence of operation codes with some codes being executed out of order in a pipeline parallel processor
JPS62290949A (ja) * 1986-06-10 1987-12-17 Fujitsu Ltd 主記憶制御方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11262936B2 (en) 2015-10-30 2022-03-01 Sony Corporation Memory controller, storage device, information processing system, and memory control method

Also Published As

Publication number Publication date
CA2044207A1 (en) 1991-12-12
EP0465847A2 (en) 1992-01-15
DE69127782D1 (de) 1997-11-06
CA2044207C (en) 1998-08-11
DE69127782T2 (de) 1998-03-19
JPH0444136A (ja) 1992-02-13
EP0465847A3 (en) 1992-03-25
EP0465847B1 (en) 1997-10-01

Similar Documents

Publication Publication Date Title
DE69132539D1 (de) EDV-System mit Speichersteuerungseinheit für direkten oder verschachtelten Speicherzugriff
DE69224571D1 (de) Mehrprozessorrechnersystem
DE69230093T2 (de) Multiprozessorsystem
BR9104956A (pt) Controlador multi-canal de dma(acesso direto a memoria)para controlar o acesso a memoria de um sistema de processamento de dados
DE69328841T2 (de) Mehrfachprozessorrechnersystem
DE69730164D1 (de) Steuerung von speicherzugriffsanordnung in einem multiprozessorsystem
DE4191157T1 (de) Zeilenspeicher mit Steuersystem
BR9307500A (pt) Sistema de controle de acesso seguro
DE69131659D1 (de) Mauszeigersteuersystem
DE69332058T2 (de) Mehrprozessorsystem
BR8707421A (pt) Sistema para controlar o acesso a uma memoria de informacoes
DE69129101D1 (de) Steuerungsanordnung für Cachespeichereinheit
ATA263582A (de) Speicherzugriff-steuereinrichtung
BR9201974A (pt) Sistema de computador pessoal com sinalizacao antecipada de controle de memoria
DE68917647D1 (de) Multiprozessorsteuerungssystem.
DE69406628T2 (de) Zugangskontrollsystem
DE69213143D1 (de) Rechnerspeichersteuerungsanordnung
DE69427512D1 (de) Direktspeicherzugriffssteuerung
BR9102549A (pt) Controlador de acesso a memoria para controlar acesso de uma fonte de solicitacao selecionada a uma memoria principal e sistema multiprocessador
DE69032511D1 (de) Multiprozessor-Steuereinrichtung mit gemeinsamem Steuerungsspeicher
DE69031529D1 (de) Speichersteuerungssystem
DE69122738T2 (de) Luftschraubersteuersystem
DE69224489D1 (de) Speicherzugriffssteuerung
DE69227272D1 (de) Multiprozessorssystem
DE9319568U1 (de) Zugangskontrollanlage

Legal Events

Date Code Title Description
FB36 Technical and formal requirements: requirement - article 36 of industrial property law
FF Decision: intention to grant
FG9A Patent or certificate of addition granted
B21A Expiry acc. art. 78, item i of ipl- expiry of the term of protection

Free format text: PATENTE EXTINTA EM 11/06/2011