DE69224489D1 - Speicherzugriffssteuerung - Google Patents

Speicherzugriffssteuerung

Info

Publication number
DE69224489D1
DE69224489D1 DE69224489T DE69224489T DE69224489D1 DE 69224489 D1 DE69224489 D1 DE 69224489D1 DE 69224489 T DE69224489 T DE 69224489T DE 69224489 T DE69224489 T DE 69224489T DE 69224489 D1 DE69224489 D1 DE 69224489D1
Authority
DE
Germany
Prior art keywords
access control
memory access
memory
control
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69224489T
Other languages
English (en)
Other versions
DE69224489T2 (de
Inventor
Kazumasa Hamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of DE69224489D1 publication Critical patent/DE69224489D1/de
Application granted granted Critical
Publication of DE69224489T2 publication Critical patent/DE69224489T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69224489T 1991-03-20 1992-03-18 Speicherzugriffssteuerung Expired - Fee Related DE69224489T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03081445A JP3105283B2 (ja) 1991-03-20 1991-03-20 メモリ・アクセス制御装置

Publications (2)

Publication Number Publication Date
DE69224489D1 true DE69224489D1 (de) 1998-04-02
DE69224489T2 DE69224489T2 (de) 1998-07-02

Family

ID=13746599

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69224489T Expired - Fee Related DE69224489T2 (de) 1991-03-20 1992-03-18 Speicherzugriffssteuerung

Country Status (4)

Country Link
US (1) US5577218A (de)
EP (1) EP0505157B1 (de)
JP (1) JP3105283B2 (de)
DE (1) DE69224489T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0613087B1 (de) * 1993-02-24 2002-11-20 Matsushita Electric Industrial Co., Ltd. Vorrichtung und Verfahren zum Speicherlesezugriff mit hoher Geschwindigkeit
CN1044750C (zh) * 1994-10-20 1999-08-18 联华电子股份有限公司 可变宽度内存数据实时读取装置
US6021472A (en) * 1995-08-21 2000-02-01 Canon Kabushiki Kaisha Information processing device and control method thereof
US5860110A (en) * 1995-08-22 1999-01-12 Canon Kabushiki Kaisha Conference maintenance method for cache memories in multi-processor system triggered by a predetermined synchronization point and a predetermined condition
EP0782079A1 (de) * 1995-12-18 1997-07-02 Texas Instruments Incorporated Stoss-Zugriff in Datenverarbeitungssystemen
JPH10154100A (ja) * 1996-11-25 1998-06-09 Canon Inc 情報処理システム及び装置及びその制御方法
US6167499A (en) * 1997-05-20 2000-12-26 Vlsi Technology, Inc. Memory space compression technique for a sequentially accessible memory
JP5446384B2 (ja) * 2009-03-30 2014-03-19 富士通セミコンダクター株式会社 インターフェース回路、メモリシステム、およびアクセス制御方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63220342A (ja) * 1987-03-10 1988-09-13 Fujitsu Ltd ブロツクアクセス方式
US5179687A (en) * 1987-09-26 1993-01-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device containing a cache and an operation method thereof
US4860325A (en) * 1988-06-24 1989-08-22 Advanced Micro Devices, Inc. Counter tester
US4870622A (en) * 1988-06-24 1989-09-26 Advanced Micro Devices, Inc. DRAM controller cache
US5134699A (en) * 1988-06-24 1992-07-28 Advanced Micro Devices, Inc. Programmable burst data transfer apparatus and technique
US5159676A (en) * 1988-12-05 1992-10-27 Micron Technology, Inc. Semi-smart DRAM controller IC to provide a pseudo-cache mode of operation using standard page mode draws

Also Published As

Publication number Publication date
JP3105283B2 (ja) 2000-10-30
US5577218A (en) 1996-11-19
EP0505157B1 (de) 1998-02-25
JPH04293134A (ja) 1992-10-16
DE69224489T2 (de) 1998-07-02
EP0505157A1 (de) 1992-09-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee