DE69227433T2 - Speicherzugriffseinrichtung - Google Patents

Speicherzugriffseinrichtung

Info

Publication number
DE69227433T2
DE69227433T2 DE69227433T DE69227433T DE69227433T2 DE 69227433 T2 DE69227433 T2 DE 69227433T2 DE 69227433 T DE69227433 T DE 69227433T DE 69227433 T DE69227433 T DE 69227433T DE 69227433 T2 DE69227433 T2 DE 69227433T2
Authority
DE
Germany
Prior art keywords
memory access
access facility
facility
memory
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69227433T
Other languages
English (en)
Other versions
DE69227433D1 (de
Inventor
Hideyuki Iino
Hiromasa Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69227433D1 publication Critical patent/DE69227433D1/de
Application granted granted Critical
Publication of DE69227433T2 publication Critical patent/DE69227433T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69227433T 1991-11-19 1992-11-19 Speicherzugriffseinrichtung Expired - Fee Related DE69227433T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30357891 1991-11-19

Publications (2)

Publication Number Publication Date
DE69227433D1 DE69227433D1 (de) 1998-12-03
DE69227433T2 true DE69227433T2 (de) 1999-03-18

Family

ID=17922692

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69227433T Expired - Fee Related DE69227433T2 (de) 1991-11-19 1992-11-19 Speicherzugriffseinrichtung

Country Status (4)

Country Link
US (1) US5551010A (de)
EP (1) EP0543652B1 (de)
KR (1) KR950014177B1 (de)
DE (1) DE69227433T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6021471A (en) * 1994-11-15 2000-02-01 Advanced Micro Devices, Inc. Multiple level cache control system with address and data pipelines
JP3019767B2 (ja) * 1995-12-28 2000-03-13 ヤマハ株式会社 デジタル信号処理装置
US5761736A (en) * 1996-05-16 1998-06-02 Advanced Micro Devices, Inc. Apparatus and method for implementing multiple scaled states in a state machine
KR100280285B1 (ko) 1996-08-19 2001-02-01 윤종용 멀티미디어 신호에 적합한 멀티미디어 프로세서
US6175908B1 (en) 1998-04-30 2001-01-16 Advanced Micro Devices, Inc. Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte
US6141745A (en) * 1998-04-30 2000-10-31 Advanced Micro Devices, Inc. Functional bit identifying a prefix byte via a particular state regardless of type of instruction
US6496902B1 (en) * 1998-12-31 2002-12-17 Cray Inc. Vector and scalar data cache for a vector multiprocessor
US7213095B2 (en) * 2004-06-08 2007-05-01 Arm Limited Bus transaction management within data processing systems
JP4691335B2 (ja) * 2004-07-30 2011-06-01 富士通株式会社 記憶制御装置、中央処理装置、情報処理装置及び記憶制御装置の制御方法
US7305335B2 (en) * 2004-11-23 2007-12-04 Schweitzer Engineering Laboratories, Inc. Permanent three-pole independent pole operation recloser simulator feature in a single-pole trip capable recloser control
US20070168646A1 (en) * 2006-01-17 2007-07-19 Jean-Francois Collard Data exchange between cooperating processors
CN102880143B (zh) * 2012-09-27 2014-10-22 中国船舶重工集团公司第七一九研究所 单can控制器热冗余can总线系统及其实现方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594682A (en) * 1982-12-22 1986-06-10 Ibm Corporation Vector processing
IT1206331B (it) * 1983-10-25 1989-04-14 Honeywell Inf Systems Architettura di sistema di elaborazione dati.
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
US4724519A (en) * 1985-06-28 1988-02-09 Honeywell Information Systems Inc. Channel number priority assignment apparatus
US4888679A (en) * 1988-01-11 1989-12-19 Digital Equipment Corporation Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements
JP2504512B2 (ja) * 1988-03-09 1996-06-05 富士通株式会社 Ｄｍａコントロ―ラ
IT1228728B (it) * 1989-03-15 1991-07-03 Bull Hn Information Syst Sistema multiprocessore con replicazione di dati globali e due livelli di unita' di traduzione indirizzi.
US5276818A (en) * 1989-04-24 1994-01-04 Hitachi, Ltd. Bus system for information processing system and method of controlling the same

Also Published As

Publication number Publication date
DE69227433D1 (de) 1998-12-03
KR930010742A (ko) 1993-06-23
US5551010A (en) 1996-08-27
KR950014177B1 (ko) 1995-11-22
EP0543652B1 (de) 1998-10-28
EP0543652A1 (de) 1993-05-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee