BR112023021017A2 - Pacotes de circuito integrado (ic) que empregam um substrato de camada de redistribuição (rdl) embutido em capacitor para interfacear um chip(s) de ic para um substrato de pacote, e métodos relacionados - Google Patents

Pacotes de circuito integrado (ic) que empregam um substrato de camada de redistribuição (rdl) embutido em capacitor para interfacear um chip(s) de ic para um substrato de pacote, e métodos relacionados

Info

Publication number
BR112023021017A2
BR112023021017A2 BR112023021017A BR112023021017A BR112023021017A2 BR 112023021017 A2 BR112023021017 A2 BR 112023021017A2 BR 112023021017 A BR112023021017 A BR 112023021017A BR 112023021017 A BR112023021017 A BR 112023021017A BR 112023021017 A2 BR112023021017 A2 BR 112023021017A2
Authority
BR
Brazil
Prior art keywords
substrate
rdl
chip
capacitor
package substrate
Prior art date
Application number
BR112023021017A
Other languages
English (en)
Portuguese (pt)
Inventor
Ahmer Syed
Giridhar Nallapati
Jianwen Xu
Jihong Choi
Jonghae Kim
Periannan Chidambaram
William Stone
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112023021017A2 publication Critical patent/BR112023021017A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
BR112023021017A 2021-04-22 2022-04-08 Pacotes de circuito integrado (ic) que empregam um substrato de camada de redistribuição (rdl) embutido em capacitor para interfacear um chip(s) de ic para um substrato de pacote, e métodos relacionados BR112023021017A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/237,828 US12218041B2 (en) 2021-04-22 2021-04-22 Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods
PCT/US2022/071621 WO2022226465A1 (en) 2021-04-22 2022-04-08 Integrated circuit (ic) packages employing a capacitor-embedded, redistribution layer (rdl) substrate for interfacing an ic chip(s) to a package substrate, and related methods

Publications (1)

Publication Number Publication Date
BR112023021017A2 true BR112023021017A2 (pt) 2023-12-19

Family

ID=81392673

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112023021017A BR112023021017A2 (pt) 2021-04-22 2022-04-08 Pacotes de circuito integrado (ic) que empregam um substrato de camada de redistribuição (rdl) embutido em capacitor para interfacear um chip(s) de ic para um substrato de pacote, e métodos relacionados

Country Status (8)

Country Link
US (2) US12218041B2 (enExample)
EP (1) EP4327361A1 (enExample)
JP (1) JP2024514601A (enExample)
KR (1) KR20240000470A (enExample)
CN (1) CN117043943A (enExample)
BR (1) BR112023021017A2 (enExample)
TW (1) TW202247306A (enExample)
WO (1) WO2022226465A1 (enExample)

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US20240079352A1 (en) * 2022-09-02 2024-03-07 Qualcomm Incorporated Integrated circuit (ic) packages employing capacitor interposer substrate with aligned external interconnects, and related fabrication methods
US20240113073A1 (en) * 2022-09-29 2024-04-04 Intel Corporation Side of a die that is coplanar with a side of a molding
US20240145447A1 (en) * 2022-10-28 2024-05-02 Psemi Corporation Integration of Discrete Embeddable Capacitors on Integrated Circuit Chips
CN120727696B (zh) * 2025-09-01 2026-01-13 浙江大学 一种正交堆叠的双面冷却功率模块及其制备方法

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US8362599B2 (en) 2009-09-24 2013-01-29 Qualcomm Incorporated Forming radio frequency integrated circuits
JP5429019B2 (ja) 2010-04-16 2014-02-26 富士通株式会社 キャパシタ及びその製造方法
US8748284B2 (en) 2011-08-12 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing decoupling MIM capacitor designs for interposers
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US9275955B2 (en) * 2013-12-18 2016-03-01 Intel Corporation Integrated circuit package with embedded bridge
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CN109314095B (zh) * 2017-04-10 2023-07-21 默升科技集团有限公司 笼式屏蔽中介层电感
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CN110634750A (zh) * 2018-06-22 2019-12-31 台湾积体电路制造股份有限公司 半导体装置及其制造方法
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Also Published As

Publication number Publication date
WO2022226465A1 (en) 2022-10-27
US20220344250A1 (en) 2022-10-27
US20250118645A1 (en) 2025-04-10
JP2024514601A (ja) 2024-04-02
CN117043943A (zh) 2023-11-10
TW202247306A (zh) 2022-12-01
EP4327361A1 (en) 2024-02-28
KR20240000470A (ko) 2024-01-02
US12218041B2 (en) 2025-02-04

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