JP2024514601A - 集積回路（ｉｃ）チップをパッケージ基板にインターフェースするためのキャパシタ埋込み、再配線層（ｒｄｌ）基板を採用するｉｃパッケージ、および関係する方法 - Google Patents

集積回路（ｉｃ）チップをパッケージ基板にインターフェースするためのキャパシタ埋込み、再配線層（ｒｄｌ）基板を採用するｉｃパッケージ、および関係する方法 Download PDF

Info

Publication number
JP2024514601A
JP2024514601A JP2023562736A JP2023562736A JP2024514601A JP 2024514601 A JP2024514601 A JP 2024514601A JP 2023562736 A JP2023562736 A JP 2023562736A JP 2023562736 A JP2023562736 A JP 2023562736A JP 2024514601 A JP2024514601 A JP 2024514601A
Authority
JP
Japan
Prior art keywords
rdl
substrate
package
layer
interconnects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023562736A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024514601A5 (enExample
Inventor
チェ、ジホン
ナッラパティ、ジリダール
ストーン、ウィリアム
シュ、ジエンウェン
キム、ジョンヘ
チダムバラム、ペリアンナン
シェイド、アフメル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2024514601A publication Critical patent/JP2024514601A/ja
Publication of JP2024514601A5 publication Critical patent/JP2024514601A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2023562736A 2021-04-22 2022-04-08 集積回路（ｉｃ）チップをパッケージ基板にインターフェースするためのキャパシタ埋込み、再配線層（ｒｄｌ）基板を採用するｉｃパッケージ、および関係する方法 Pending JP2024514601A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/237,828 2021-04-22
US17/237,828 US12218041B2 (en) 2021-04-22 2021-04-22 Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods
PCT/US2022/071621 WO2022226465A1 (en) 2021-04-22 2022-04-08 Integrated circuit (ic) packages employing a capacitor-embedded, redistribution layer (rdl) substrate for interfacing an ic chip(s) to a package substrate, and related methods

Publications (2)

Publication Number Publication Date
JP2024514601A true JP2024514601A (ja) 2024-04-02
JP2024514601A5 JP2024514601A5 (enExample) 2025-03-31

Family

ID=81392673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023562736A Pending JP2024514601A (ja) 2021-04-22 2022-04-08 集積回路（ｉｃ）チップをパッケージ基板にインターフェースするためのキャパシタ埋込み、再配線層（ｒｄｌ）基板を採用するｉｃパッケージ、および関係する方法

Country Status (8)

Country Link
US (2) US12218041B2 (enExample)
EP (1) EP4327361A1 (enExample)
JP (1) JP2024514601A (enExample)
KR (1) KR20240000470A (enExample)
CN (1) CN117043943A (enExample)
BR (1) BR112023021017A2 (enExample)
TW (1) TW202247306A (enExample)
WO (1) WO2022226465A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI806490B (zh) * 2022-03-14 2023-06-21 巨擘科技股份有限公司 封裝基板結構
US20240079352A1 (en) * 2022-09-02 2024-03-07 Qualcomm Incorporated Integrated circuit (ic) packages employing capacitor interposer substrate with aligned external interconnects, and related fabrication methods
US20240113073A1 (en) * 2022-09-29 2024-04-04 Intel Corporation Side of a die that is coplanar with a side of a molding
US20240145447A1 (en) * 2022-10-28 2024-05-02 Psemi Corporation Integration of Discrete Embeddable Capacitors on Integrated Circuit Chips
CN120727696B (zh) * 2025-09-01 2026-01-13 浙江大学 一种正交堆叠的双面冷却功率模块及其制备方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0646954A3 (en) * 1993-09-29 1997-08-27 Fujitsu Ltd One-step etching process with minor defects.
JP2005039243A (ja) 2003-06-24 2005-02-10 Ngk Spark Plug Co Ltd 中間基板
JP2005327984A (ja) * 2004-05-17 2005-11-24 Shinko Electric Ind Co Ltd 電子部品及び電子部品実装構造の製造方法
US8362599B2 (en) 2009-09-24 2013-01-29 Qualcomm Incorporated Forming radio frequency integrated circuits
JP5429019B2 (ja) 2010-04-16 2014-02-26 富士通株式会社 キャパシタ及びその製造方法
US8748284B2 (en) 2011-08-12 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing decoupling MIM capacitor designs for interposers
US9478474B2 (en) 2012-12-28 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for forming package-on-packages
US9275955B2 (en) * 2013-12-18 2016-03-01 Intel Corporation Integrated circuit package with embedded bridge
US9935052B1 (en) 2014-11-26 2018-04-03 Altera Corporation Power line layout in integrated circuits
US9859258B2 (en) 2016-05-17 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
CN109314095B (zh) * 2017-04-10 2023-07-21 默升科技集团有限公司 笼式屏蔽中介层电感
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
US10535636B2 (en) 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
CN110634750A (zh) * 2018-06-22 2019-12-31 台湾积体电路制造股份有限公司 半导体装置及其制造方法
US10879183B2 (en) * 2018-06-22 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
KR102595865B1 (ko) 2019-03-04 2023-10-30 삼성전자주식회사 하이브리드 인터포저를 갖는 반도체 패키지
US11063013B2 (en) 2019-05-15 2021-07-13 Advanced Semiconductor Engineering, Inc. Semiconductor package structure
US12341129B2 (en) * 2019-06-13 2025-06-24 Intel Corporation Substrateless double-sided embedded multi-die interconnect bridge
TWI725452B (zh) 2019-06-20 2021-04-21 矽品精密工業股份有限公司 電子封裝件及其製法
US11133258B2 (en) * 2019-07-17 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package with bridge die for interconnection and method forming same
US11854984B2 (en) * 2019-09-25 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US12439616B2 (en) * 2021-03-26 2025-10-07 Intel Corporation Integrated circuit package redistribution layers with metal-insulator-metal (MIM) capacitors

Also Published As

Publication number Publication date
WO2022226465A1 (en) 2022-10-27
US20220344250A1 (en) 2022-10-27
US20250118645A1 (en) 2025-04-10
CN117043943A (zh) 2023-11-10
TW202247306A (zh) 2022-12-01
EP4327361A1 (en) 2024-02-28
KR20240000470A (ko) 2024-01-02
BR112023021017A2 (pt) 2023-12-19
US12218041B2 (en) 2025-02-04

Similar Documents

Publication Publication Date Title
JP2024514601A (ja) 集積回路（ｉｃ）チップをパッケージ基板にインターフェースするためのキャパシタ埋込み、再配線層（ｒｄｌ）基板を採用するｉｃパッケージ、および関係する方法
KR102643781B1 (ko) 3차원(3d) 다이 적층을 위한 fs-beol 대 bs-beol 적층을 채용하는 집적 회로(ic) 패키지들 및 관련 제조 방법들
US20230317677A1 (en) Three-dimensional (3d) integrated circuit (ic) (3dic) package employing a redistribution layer (rdl) interposer facilitating semiconductor die stacking, and related fabrication methods
TW202335240A (zh) 採用轉用晶種層形成至後端製程（ｂｅｏｌ）結構的額外信號路徑的半導體晶粒、以及相關積體電路（ｉｃ）封裝和製造方法
JP2024508636A (ja) 受動部品を形成するために金属化構造内で受動部品デバイスを導電性トレースに結合するために導電性ピラーを使用するチップモジュール
TW202412247A (zh) 採用具有對準的外部互連的電容器中介層基板的積體電路（ｉｃ）封裝以及相關製造方法
US20240038753A1 (en) DEEP TRENCH CAPACITORS (DTCs) EMPLOYING BYPASS METAL TRACE SIGNAL ROUTING, AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS
JP2024537996A (ja) ダイ側埋め込みトレース基板（ｅｔｓ）層内の埋め込み金属トレースに結合された補助金属層を採用する集積回路（ｉｃ）パッケージ、及び関連する製造方法
TWI914389B (zh) 用於改進連通性的具有重構晶粒中介體的積體電路（ｉｃ）及相關製造方法
US11769732B2 (en) Integrated circuit (IC) with reconstituted die interposer for improved connectivity, and related methods of fabrication
US12381174B2 (en) Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods
US20250239518A1 (en) PACKAGE SUBSTRATE WITH EMBEDDED CAPACITOR PACKAGE HAVING REDISTRIBUTION LAYER(S) (RDL(s)) FOR ALIGNING CAPACITOR TERMINALS CONNECTIONS TO SEMICONDUCTOR DIE IN AN INTEGRATED CIRCUIT (IC) PACKAGE, AND RELATED FABRICATION METHODS
US20260090465A1 (en) RADIO-FREQUENCY (RF) INTEGRATED CIRCUITS (ICs) EMPLOYING MULTIPLE COUPLED DIES FOR FACILITATING ELECTRICAL ISOLATION OF RF DEVICES, AND RELATED FABRICATION METHODS
TW202303890A (zh) 積體電路晶粒的互連層上的層間媒體中的深溝槽電容器及相關方法
WO2025212267A1 (en) Semiconductor die having a die interconnect and a die level distribution metallization layer including a metal line and a metal pad
KR20240046873A (ko) 패키지 높이 감소를 위해 패키지 기판에 상부 적층형 다이(들)를 커플링시키기 위한 인터포저를 채용한 적층형 다이 집적 회로(ic) 패키지, 및 관련 제조 방법들

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250321

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20250321

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20260331

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20260421