BR112023012153A2 - Arquitetura de circuito de memória - Google Patents
Arquitetura de circuito de memóriaInfo
- Publication number
- BR112023012153A2 BR112023012153A2 BR112023012153A BR112023012153A BR112023012153A2 BR 112023012153 A2 BR112023012153 A2 BR 112023012153A2 BR 112023012153 A BR112023012153 A BR 112023012153A BR 112023012153 A BR112023012153 A BR 112023012153A BR 112023012153 A2 BR112023012153 A2 BR 112023012153A2
- Authority
- BR
- Brazil
- Prior art keywords
- quadrant
- memory circuit
- bit cell
- cell core
- quadrants
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Abstract
arquitetura de circuito de memória. um dispositivo semicondutor inclui: um circuito de memória tendo uma pluralidade de quadrantes dispostos em cantos do circuito de memória e circundando um componente de controle de banco; em que um primeiro quadrante da pluralidade de quadrantes inclui um primeiro núcleo de célula de bit e um primeiro conjunto de circuitos de entrada e saída configurados para acessar o primeiro núcleo de célula de bit, o primeiro quadrante definido por um limite retangular que encerra porções de duas bordas perpendiculares do circuito de memória; em que um segundo quadrante da pluralidade de quadrantes inclui um segundo núcleo de célula de bit e um segundo conjunto de circuitos de entrada e saída configurados para acessar o segundo núcleo de célula de bit, o segundo quadrante estando adjacente ao primeiro quadrante, em que uma fronteira entre o primeiro quadrante e o segundo quadrante define um primeiro eixo em torno do qual o primeiro quadrante e o segundo quadrante são simétricos.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/136,616 US11600307B2 (en) | 2020-12-29 | 2020-12-29 | Memory circuit architecture |
PCT/US2021/062470 WO2022146643A1 (en) | 2020-12-29 | 2021-12-08 | Memory circuit architecture |
Publications (1)
Publication Number | Publication Date |
---|---|
BR112023012153A2 true BR112023012153A2 (pt) | 2023-11-28 |
Family
ID=79316990
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112023012153A BR112023012153A2 (pt) | 2020-12-29 | 2021-12-08 | Arquitetura de circuito de memória |
Country Status (7)
Country | Link |
---|---|
US (2) | US11600307B2 (pt) |
EP (1) | EP4272213A1 (pt) |
KR (1) | KR20230125203A (pt) |
CN (1) | CN116490925A (pt) |
BR (1) | BR112023012153A2 (pt) |
TW (1) | TW202230352A (pt) |
WO (1) | WO2022146643A1 (pt) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11600307B2 (en) | 2020-12-29 | 2023-03-07 | Qualcomm Incorporated | Memory circuit architecture |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6212089B1 (en) * | 1996-03-19 | 2001-04-03 | Hitachi, Ltd. | Semiconductor memory device and defect remedying method thereof |
US5617555A (en) | 1995-11-30 | 1997-04-01 | Alliance Semiconductor Corporation | Burst random access memory employing sequenced banks of local tri-state drivers |
AU7706198A (en) | 1997-05-30 | 1998-12-30 | Micron Technology, Inc. | 256 meg dynamic random access memory |
US6237130B1 (en) * | 1998-10-29 | 2001-05-22 | Nexabit Networks, Inc. | Chip layout for implementing arbitrated high speed switching access of pluralities of I/O data ports to internally cached DRAM banks and the like |
US6963515B2 (en) | 2003-05-08 | 2005-11-08 | Lsi Logic Corporation | Method and device for a scalable memory building block |
KR100855586B1 (ko) | 2006-11-10 | 2008-09-01 | 삼성전자주식회사 | 반도체 메모리 장치 및 그의 레이아웃 방법 |
US7817470B2 (en) | 2006-11-27 | 2010-10-19 | Mosaid Technologies Incorporated | Non-volatile memory serial core architecture |
US8913440B2 (en) | 2011-10-05 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tracking mechanisms |
US8929154B2 (en) | 2011-10-06 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout of memory cells |
US8780652B2 (en) | 2012-03-13 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Signal tracking in write operations of memory cells |
US8988948B2 (en) | 2013-07-24 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Memory macro with a voltage keeper |
KR102421299B1 (ko) | 2016-09-12 | 2022-07-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 기억 장치, 이의 구동 방법, 반도체 장치, 전자 부품, 및 전자 기기 |
US11600307B2 (en) | 2020-12-29 | 2023-03-07 | Qualcomm Incorporated | Memory circuit architecture |
-
2020
- 2020-12-29 US US17/136,616 patent/US11600307B2/en active Active
-
2021
- 2021-12-02 TW TW110144961A patent/TW202230352A/zh unknown
- 2021-12-08 KR KR1020237020990A patent/KR20230125203A/ko unknown
- 2021-12-08 CN CN202180079495.XA patent/CN116490925A/zh active Pending
- 2021-12-08 EP EP21840739.3A patent/EP4272213A1/en active Pending
- 2021-12-08 WO PCT/US2021/062470 patent/WO2022146643A1/en active Application Filing
- 2021-12-08 BR BR112023012153A patent/BR112023012153A2/pt unknown
-
2023
- 2023-02-01 US US18/163,146 patent/US11908537B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US11600307B2 (en) | 2023-03-07 |
TW202230352A (zh) | 2022-08-01 |
CN116490925A (zh) | 2023-07-25 |
US20230178118A1 (en) | 2023-06-08 |
US20220208232A1 (en) | 2022-06-30 |
US11908537B2 (en) | 2024-02-20 |
WO2022146643A1 (en) | 2022-07-07 |
KR20230125203A (ko) | 2023-08-29 |
EP4272213A1 (en) | 2023-11-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
BR112023012153A2 (pt) | Arquitetura de circuito de memória | |
KR102231294B1 (ko) | 복수의 레벨의 오류 정정을 제공하는 정보 처리 장치 및 시스템, 및 그것의 동작 방법 | |
US20090168483A1 (en) | Ultra low voltage and minimum operating voltage tolerant register file | |
BR112014018350A8 (pt) | Disposição de semicondutor com zona de deriva ativa | |
JP2007172811A (ja) | 可変的アクセス経路を有するマルチポート半導体メモリ装置及びその方法 | |
US9646684B1 (en) | PCM memory with margin current addition and related methods | |
BR112022021777A2 (pt) | Transistor de nanofolhas com pilha de porta assimétrica | |
GB1336981A (en) | Digital electric information processing system | |
BR112018001991B8 (pt) | Célula solar | |
US8044695B2 (en) | Semiconductor integrated circuit including a master-slave flip-flop | |
BR112023013290A2 (pt) | Pacote compreendendo um substrato e dispositivo de interconexão configurado para roteamento diagonal | |
KR940020427A (ko) | 반도체 기억소자의 테스트 모드회로 | |
CN107680631B (zh) | 带有余量电流相加的pcm存储器以及相关方法 | |
US7975246B2 (en) | MEEF reduction by elongation of square shapes | |
US11816351B2 (en) | Write operation circuit, semiconductor memory, and write operation method | |
KR860006875A (ko) | 반도체 장치 | |
US9123438B2 (en) | Configurable delay circuit and method of clock buffering | |
EP3896694B1 (en) | Write operation circuit, semiconductor memory, and write operation method | |
KR20130073234A (ko) | 반도체 장치 | |
JP2010033692A (ja) | 負電圧生成回路及びこれを用いた半導体メモリ装置 | |
ATE487181T1 (de) | Fehlererkennungsvorrichtung mit niedrigleistungsmodus und entsprechendes verfahren | |
KR100731080B1 (ko) | 에스램 소자의 구조 | |
US20230053536A1 (en) | Integrated circuit memory and the method of forming the same | |
JP5025785B2 (ja) | 半導体記憶装置 | |
JP4964907B2 (ja) | 記憶体制御器及び復号器 |